434 Drc Jobs - Page 7

If you are looking for a challenging and exciting career in the world of technology, then look no further. Skyworks is an innovator of high performance analog semiconductors whose solutions are powering the wireless networking revolution. At Skyworks, you will find a fast-paced environment with a strong focus on global collaboration, minimal layers of management and the freedom to make meaningful contributions in a setting that encourages creativity and out-of-the-box thinking. Our work culture values diversity, social responsibility, open communication, mutual trust and respect. We are excited about the opportunity to work with you and glad you want to be part of a team of talented individuals who together can change the way the world communicates. Requisition ID: 74461 Job Description Architects, designs and verifies circuits, logic, systems, algorithms, etc. to meet product requirements Determine design approaches and parameters Develops innovative new designs for patenting or protecting as trade secret Demonstrates good judgment in solving a broad range of issues, based on an advanced understanding of industry practices and company policies and procedures Responsible for custom layout, including overseeing the work of layout designers Reports on design results through design reviews, in accordance with company quality requirements and resolves action items generated as a result of these reviews Attends design reviews to provide input and learn from other designers’ experiences Research design techniques through technical publications and seminars Supports marketing in product definition Having a wide-ranging experience uses professional concepts and company objectives to resolve complex issues in creative and effective way Determines methods and procedures on new assignments and may coordinate the activities of other personnel Job Requirements A technology-related master’s degree or equivalent training and 8 or more years of analog/mixed-signal design experience developing mixed-signal ICs Proven leadership in analog/mixed signal design projects Strong knowledge of engineering fundamentals Advanced knowledge of CMOS fabrication processes Advanced knowledge of MOS transistors and analog/digital circuit design Knowledge of complex AD/DC analysis (poles, zeros, compensation) Advanced signal analysis knowledge Basic understanding of CMOS and BCD parasitic junctions and the risks associated with them Strong parasitic analysis knowledge (capacitance, resistance, power grid) Advanced knowledge of circuit building blocks (e.g., OPAMP, gm-C filters, switch capacitors, ADC, DAC, state-machines, and bus interfaces) Advanced design skills in system modeling Strong knowledge of UNIX, Matlab, and circuit simulation tools Proficiency in layout verification, DRC, LVS Additional skills (one or more of these are highly desirable) Working knowledge of device physics Working knowledge of digital design and design flows System knowledge (e.g., High Performance PLLs) Knowledge of scripting language (python, shell, skill) Advanced laboratory measurement skills (analog, digital) Knowledge of MS Office documentation, spreadsheet, presentation tools or equivalent tools Excellent written and verbal presentation skills Skyworks is an Equal Opportunity Employer. All qualified applicants will receive consideration for employment without regard to race, color, religion, age, sex, sexual orientation, gender identity, national origin, disability, protected veteran status, or any other characteristic protected by law.

If you are looking for a challenging and exciting career in the world of technology, then look no further. Skyworks is an innovator of high performance analog semiconductors whose solutions are powering the wireless networking revolution. At Skyworks, you will find a fast-paced environment with a strong focus on global collaboration, minimal layers of management and the freedom to make meaningful contributions in a setting that encourages creativity and out-of-the-box thinking. Our work culture values diversity, social responsibility, open communication, mutual trust and respect. We are excited about the opportunity to work with you and glad you want to be part of a team of talented individuals who together can change the way the world communicates. Requisition ID: 74458 Job Description Architects, designs and verifies circuits, logic, systems, algorithms, etc. to meet product requirements Determine design approaches and parameters Develops innovative new designs for patenting or protecting as trade secret Demonstrates good judgment in solving a broad range of issues, based on an advanced understanding of industry practices and company policies and procedures Responsible for custom layout, including overseeing the work of layout designers Reports on design results through design reviews, in accordance with company quality requirements and resolves action items generated as a result of these reviews Attends design reviews to provide input and learn from other designers’ experiences Research design techniques through technical publications and seminars Supports marketing in product definition Having a wide-ranging experience uses professional concepts and company objectives to resolve complex issues in creative and effective way Determines methods and procedures on new assignments and may coordinate the activities of other personnel Job Requirements A technology-related master’s degree or equivalent training and 3 or more years of analog/mixed-signal design experience developing mixed-signal ICs Strong knowledge of engineering fundamentals Advanced knowledge of CMOS fabrication processes Advanced knowledge of MOS transistors and analog/digital circuit design Knowledge of complex AD/DC analysis (poles, zeros, compensation) Advanced signal analysis knowledge Basic understanding of CMOS and BCD parasitic junctions and the risks associated with them Strong parasitic analysis knowledge (capacitance, resistance, power grid) Advanced knowledge of circuit building blocks (e.g., OPAMP, gm-C filters, switch capacitors, ADC, DAC, state-machines, and bus interfaces) Advanced understanding of layout tradeoffs for performance and size Advanced design skills in system modeling Strong knowledge of UNIX, Matlab, and circuit simulation tools Proficiency in layout verification, DRC, LVS Additional skills (one or more of these are highly desirable): Working knowledge of device physics Working knowledge of digital design and design flows System knowledge (e.g., High Performance PLLs) Knowledge of scripting language (python, shell, skill) Advanced laboratory measurement skills (analog, digital) Knowledge of MS Office documentation, spreadsheet, presentation tools or equivalent tools Excellent written and verbal presentation skills Skyworks is an Equal Opportunity Employer. All qualified applicants will receive consideration for employment without regard to race, color, religion, age, sex, sexual orientation, gender identity, national origin, disability, protected veteran status, or any other characteristic protected by law.

Who We Are At Kyndryl, we design, build, manage and modernize the mission-critical technology systems that the world depends on every day. So why work at Kyndryl? We are always moving forward – always pushing ourselves to go further in our efforts to build a more equitable, inclusive world for our employees, our customers and our communities. The Role As a System Administrator at Kyndryl, you’ll solve complex problems and identify potential future issues across the spectrum of platforms and services. Do you want to be at the forefront of designing and implementing cutting-edge network solutions? Within our Network Services team at Kyndryl, you will be the go-to expert for providing top-of-the-line technical solutions throughout the entire solution lifecycle. You will be responsible for creating local and wide-area network solutions that utilize multiple platforms and protocols, ensuring that our customers have the best possible network infrastructure to support their business needs. Your skills in routers, networking controllers, bridges, and networking software will be essential as you troubleshoot network issues and coordinate with vendors to install the latest hardware and software, such as routers and switches. Not only will you help keep our customer’s networks running smoothly, but you will also work on project implementation, conduct project planning and cost analysis, and build proof-of-concept solutions with networking system technology. In this role, you will have the opportunity to review project requirements, communicate them accurately to the team, and ensure they are appropriately fulfilled. You will use your expertise to design and implement local and wide-area network solutions, including IP and VOIP, that address customer requirements. You will also provide high-quality technical solutions to our customers to prepare them for implementation, go-live, and maintenance. Implement and manage branch side Switch - VLANs, VTP, and trunking , Ensure network availability, performance, and security. Troubleshoot branch WAN issues using tools like ping, traceroute, and SNMP.. Provide L1 support for branch networks, resolving hardware and software issues for Network devices. Ensure branch network devices are compliant with customer security policies. Participate in network upgrades, migrations, and projects. Collaborate with cross-functional teams to resolve network-related issues. Identify and resolve network-related issues using logical troubleshooting methodologies. Analyse network logs, packet captures, and performance metrics , Escalate complex issues to senior engineers. If you are excited about using your technical expertise to create innovative network solutions and provide outstanding customer service, then this is the role for you! Your Future at Kyndryl At Kyndryl, we understand the importance of investing in our employees' professional growth and development. In Network Services, you can expect to receive a lot of support for training programs to keep your skills and knowledge up to date with the latest industry trends and technologies. By joining our team, you will have the opportunity to work on cutting-edge projects and contribute to the development of innovative solutions for our customers – including new wireless and 5G technologies – not yet adopted by most companies. Who You Are You’re good at what you do and possess the required experience to prove it. However, equally as important – you have a growth mindset; keen to drive your own personal and professional development. You are customer-focused – someone who prioritizes customer success in their work. And finally, you’re open and borderless – naturally inclusive in how you work with others. Required Technical and Professional Expertise 3 years of experience in Network support covering WAN technologies MPLS, SDWAN etc Strong understanding of TCP/IP, routing protocols (OSPF, EIGRP), and switching fundamentals. Experience with Cisco IOS and network management tools , Familiarity with WAN technologies (MPLS, VPNs). Monitor branch WAN links for availability, latency, and packet loss. Configure and troubleshoot network devices, including routers, switches, modems etc. Collaborate with telecom DC & DRC teams to resolve branches WAN-related issues Configure, monitor , and troubleshoot Cisco, Juniper, HP ant other OEM routers and switches. Preferred Technical and Professional Experience CCNP or equivalent certification. Experience with SDWAN, and VPNs. Familiarity with ITIL or similar service management frameworks. Being You Diversity is a whole lot more than what we look like or where we come from, it’s how we think and who we are. We welcome people of all cultures, backgrounds, and experiences. But we’re not doing it single-handily: Our Kyndryl Inclusion Networks are only one of many ways we create a workplace where all Kyndryls can find and provide support and advice. This dedication to welcoming everyone into our company means that Kyndryl gives you – and everyone next to you – the ability to bring your whole self to work, individually and collectively, and support the activation of our equitable culture. That’s the Kyndryl Way. What You Can Expect With state-of-the-art resources and Fortune 100 clients, every day is an opportunity to innovate, build new capabilities, new relationships, new processes, and new value. Kyndryl cares about your well-being and prides itself on offering benefits that give you choice, reflect the diversity of our employees and support you and your family through the moments that matter – wherever you are in your life journey. Our employee learning programs give you access to the best learning in the industry to receive certifications, including Microsoft, Google, Amazon, Skillsoft, and many more. Through our company-wide volunteering and giving platform, you can donate, start fundraisers, volunteer, and search over 2 million non-profit organizations. At Kyndryl, we invest heavily in you, we want you to succeed so that together, we will all succeed. Get Referred! If you know someone that works at Kyndryl, when asked ‘How Did You Hear About Us’ during the application process, select ‘Employee Referral’ and enter your contact's Kyndryl email address.

Role & responsibilities Physical Design Engineer (PD/STA/Synthesis) Must-Haves: •Tools: Cadence Innovus, Synopsys ICC2/Fusion Compiler, PrimeTime for STA •Flow Experience: •Floorplanning •Power planning •Placement •Clock Tree Synthesis (CTS) •Routing •Physical Verification (DRC/LVS) •Timing Closure •Knowledge of: •Low-power design (UPF/CPF) •ECOs •IR Drop, EM Analysis •STA constraints and timing analysis Nice-to-Haves: •Experience with block-level and/or full-chip PD •Familiarity with scripting (Tcl, Perl, Python)

Responsibilities: * Ensure physical verification with Caliber and LVS tools * Collaborate on layout planning and execution using Virtuoso software * Perform DRC checks for design compliance Annual bonus

Physical Design Engineer (PD/STA/Synthesis) Must-Haves: • Tools: Cadence Innovus, Synopsys ICC2/Fusion Compiler, PrimeTime for STA • Flow Experience: • Floorplanning • Power planning • Placement • Clock Tree Synthesis (CTS) • Routing • Physical Verification (DRC/LVS) • Timing Closure • Knowledge of: • Low-power design (UPF/CPF) • ECOs • IR Drop, EM Analysis • STA constraints and timing analysis Nice-to-Haves: • Experience with block-level and/or full-chip PD • Familiarity with scripting (Tcl, Perl, Python) Show more Show less

Senior Analog Layout Engineer Exp : 5 to 8 years Work Location: Phoenix Aquila, Hyderabad, India Joining Timeline: Immediate to 15 Days preferred Maximum Notice Period: 30 Days (Strict) Job Description: Xeedo Technologies is seeking experienced Senior Analog Layout Engineers to work on-site for a global semiconductor leader – Micron Technology. The role involves end-to-end ownership of analog/custom layout blocks, physical verification, and collaboration with global design teams for successful project execution and tape-outs. Key Responsibilities: Design and development of analog and custom digital layout blocks in advanced CMOS technologies. Perform full physical verification using Mentor Graphics Calibre – including DRC, LVS, and Antenna checks. Ensure first-pass silicon success through high-quality layout practices and thorough verification. Interpret circuit schematics to create optimized layouts for power, area, performance, and reliability. Plan, estimate, and track layout tasks to meet project milestones and delivery schedules. Collaborate with cross-functional and global teams to resolve design and integration issues. Review work and mentor junior layout engineers when required. Required Skills: 5 to 8 years of hands-on experience in analog/custom layout design. Proficient in Cadence VLE/VXL layout tools. Strong experience with Mentor Graphics Calibre for DRC/LVS/Antenna verification. Hands-on layout experience in one or more of the following analog blocks: PLL, Bandgap, LDO, Temperature Sensors, ADC, DAC, Charge Pumps, Current Mirrors, Comparators, etc. Strong knowledge of layout principles such as: Matching, IR-drop, Electromigration, Parasitics, Latch-up, Crosstalk, and Coupling. Experience with multi-project environments and multiple successful tape-outs. Preferred Skills: Familiarity with custom memory layout methodologies. Experience in designing layout for: Bit cells, leaf cells, sense amps, decoders, and control logic. Educational Qualification: BE/BTech or ME/MTech in Electronics, Electrical, or VLSI Engineering. This is an exciting opportunity for engineers who are passionate about Analog Layout and eager to contribute to complex and cutting-edge semiconductor designs for a global client. Show more Show less

ASIC/SOC Front End Design Engineer Job description: 1. Setup ASIC QA flows for RTL design quality checks. 2. Understand the design: top level interfaces, clock structure, reset structure, RAMs, CDC boundaries, power domains. 3. Running Lint, Synthesis, LEC, Static timing analysis, CDC, RDC, DFT, CLP steps. 4. Come up with clock constraints, false paths, multi-cycle paths, IO delays, exceptions and waivers. 5. Checking the flow errors, design errors & violations and reviewing the reports. 6. Debugging CDC, RDC issues and come up with the RTL fixes. 7. Supporting DFX team for DFX controller integration, Scan insertion, MBIST insertion and DFT DRC & MBIST checks. 8. Handling multiple PNR blocks, building wrappers and propagating constraints, waivers, etc. 9. Flows or Design porting to different technology libraries. 10. Generating RAMs based on targeted memory compilers and integrating with the RTL. 11. Running functional verification simulations as needed. Job Requirements: 1. B.E/M.E/M.Tech or B.S/M.S in EE/CE with 3 to 5 years of relevant experience 2. ASIC design flow and direct experience with ASIC design in sub-20nm technology nodes 3. Modern SOC tools including Spyglass, Synopsys design compiler & primetime, Questa CDC, Cadence Conformal, VCS simulation 4. Experience in signoff of front end quality checks & metrics for various milestones of the project 5. TCL, Perl, Python scripting Experience: 3 to 5 years Location: Hyderabad Notice Period: Immediate Show more Show less

Job Title: PCB Designer – IoT & Battery-Powered Devices Job Description: WCO Global is seeking a skilled and detail-oriented PCB Designer with experience in designing hardware for IoT-based and battery-operated devices. The ideal candidate will have a strong foundation in electronics design, PCB layout, and an understanding of low-power embedded systems. This role involves close collaboration with the hardware, firmware, and mechanical engineering teams to create reliable and manufacturable PCB designs that meet product and performance specifications. Responsibilities: Design and develop PCB layouts and schematics for IoT and battery-powered devices. Develop and maintain component libraries including footprints and symbols. Collaborate with electrical and mechanical engineers to finalize board dimensions, mounting, and placement. Perform design rule checks (DRC), electrical rule checks (ERC), and ensure compliance with IPC standards. Optimize PCB layouts for low power consumption, thermal performance, signal integrity, and electromagnetic compatibility. Generate Gerber files, Bill of Materials (BOM), and assembly files for prototype and production. Coordinate with fabrication and assembly vendors to ensure designs meet manufacturing requirements. Participate in design reviews and implement feedback. Required Skills: Proficiency in PCB design tools such as Altium Designer, OrCAD, or KiCad. Strong understanding of analog and digital circuit design. Experience in designing for battery-powered, low-power devices. Familiarity with IoT technologies and wireless protocols such as BLE, Wi-Fi, or LoRa. Good understanding of power management techniques and considerations. Knowledge of high-speed layout techniques, impedance control, and EMI/EMC best practices. Qualifications: Bachelor’s or Master’s degree in Electronics Engineering, Electrical Engineering, or a related field. 1–3 years of relevant experience in PCB design, preferably in the IoT or embedded systems domain. Experience working on end-to-end product development cycles is a plus. Show more Show less

If you are looking for a challenging and exciting career in the world of technology, then look no further. Skyworks is an innovator of high performance analog semiconductors whose solutions are powering the wireless networking revolution. At Skyworks, you will find a fast-paced environment with a strong focus on global collaboration, minimal layers of management and the freedom to make meaningful contributions in a setting that encourages creativity and out-of-the-box thinking. We are excited about the opportunity to work with you and glad you want to be part of a team of talented individuals who together can change the way the world communicates. Requisition ID: 74459 Job Description Description Seeking an experienced analog/mixed-signal design engineer for developing complex mixed-signal ICs for Timing and Infrastructure applications. The position requires a strong analog mixed-signal design background including a strong history of innovative product and IP definition and design. Depending on experience level, the individual will participate in product roadmaps, definition, technology selection, design, and verification. The individual will have a role in defining and implementing the overall system architecture, designing transistor-level analog circuit blocks, simulating sub-system performance, creating and using behavioral models of blocks and the entire IC, doing and/or supervising physical layout, verifying circuit and chip-level operation and performance, and assisting with tape-out related activities. Responsibilities will also include detailed documentation, silicon evaluation and debugging, production test development support, customer support, and other activities as required for the achievement of high volume production. Responsibilities Architects, designs and verifies circuits, logic, systems, algorithms, etc. to meet product requirements Determine design approaches and parameters Develops innovative new designs for patenting or protecting as trade secret Demonstrates good judgment in solving a broad range of issues, based on an advanced understanding of industry practices and company policies and procedures Responsible for custom layout, including overseeing the work of layout designers Reports on design results through design reviews, in accordance with company quality requirements and resolves action items generated as a result of these reviews Attends design reviews to provide input and learn from other designers’ experiences Research design techniques through technical publications and seminars Supports marketing in product definition Having a wide-ranging experience uses professional concepts and company objectives to resolve complex issues in creative and effective way Determines methods and procedures on new assignments and may coordinate the activities of other personnel Education Requirements A technology-related master’s degree or equivalent training and 3 or more years of analog/mixed-signal design experience developing mixed-signal ICs An advanced degree may reduce the minimum experience required. Minimum Requirements Strong knowledge of engineering fundamentals Advanced knowledge of CMOS fabrication processes Advanced knowledge of MOS transistors and analog/digital circuit design Knowledge of complex AD/DC analysis (poles, zeros, compensation) Advanced signal analysis knowledge Basic understanding of CMOS and BCD parasitic junctions and the risks associated with them Strong parasitic analysis knowledge (capacitance, resistance, power grid) Advanced knowledge of circuit building blocks (e.g., OPAMP, gm-C filters, switch capacitors, ADC, DAC, state-machines, and bus interfaces) Advanced understanding of layout tradeoffs for performance and size Advanced design skills in system modeling Strong knowledge of UNIX, Matlab, and circuit simulation tools Proficiency in layout verification, DRC, LVS Additional skills (one or more of these are highly desirable) Working knowledge of device physics Working knowledge of digital design and design flows System knowledge (e.g., High Performance PLLs) Knowledge of scripting language (python, shell, skill) Advanced laboratory measurement skills (analog, digital) Knowledge of MS Office documentation, spreadsheet, presentation tools or equivalent tools Excellent written and verbal presentation skills Skyworks is an Equal Opportunity Employer. All qualified applicants will receive consideration for employment without regard to race, color, religion, age, sex, sexual orientation, gender identity, national origin, disability, protected veteran status, or any other characteristic protected by law.

Expert in implementing Scan insertion, LPCT, LBIST, Hybrid-TK, Compression Logic and DRC analysis of implemented Testability logic structures. In your new role you will: Responsible for SoC DFT Architecture definition/implementation/verification/silicon debug of SoC/Full Chip. Need to implement Scan insertion, LPCT, LBIST, Hybrid-TK, Compression Logic and DRC analysis of implemented Testability logic structures. Responsible for ATPG, DRC analysis, Test coverage debug, Memory BIST implementation and verification. Owner ship of JTAG/BSCAN/iJTAG, P1500 implementation and verification, Stuck-at/TDF/Bridging/Cell-aware/iddq fault models. Good debug skills in ZERO delay and SDF based scan/MBIST/JTAG simulations. Hands on experience in analysis and debug of above-mentioned test domains. Hands of experience in post silicon debug of scan/MBIST patterns/yield fall out You are best equipped for this task if you have: ASIC flow understanding. Experienced in LEC, CLP, power analysis flow is preferred The ability to work as an individual and as part of a team to deliver complex SoCs starting from the creation of the DFT spec, implementation, verification, and Post silicon debug. In addition, be self-motivated with the initiative to seek constant improvements in the DFT design methodologies. The candidate must also possess strong initiative, analytical/problem solving skills, team working skills, ability to multitask and be able to work within a diverse team environment. Scripting skills such as PERL/TCL/Python are preferred Degree & Discipline: BE/B.Tech Electrical/Electronic or ME/M Tech in VLSI design. Experience in Industry: 12+ years of in DFT implementation, verification and post silicon debug areas. #WeAreIn for driving decarbonization and digitalization. As a global leader in semiconductor solutions in power systems and IoT, Infineon enables game-changing solutions for green and efficient energy, clean and safe mobility, as well as smart and secure IoT. Together, we drive innovation and customer success, while caring for our people and empowering them to reach ambitious goals. Be a part of making life easier, safer and greener. Are you in? We are on a journey to create the best Infineon for everyone. This means we embrace diversity and inclusion and welcome everyone for who they are. At Infineon, we offer a working environment characterized by trust, openness, respect and tolerance and are committed to give all applicants and employees equal opportunities. We base our recruiting decisions on the applicant´s experience and skills. Please let your recruiter know if they need to pay special attention to something in order to enable your participation in the interview process. Click here for more information about Diversity & Inclusion at Infineon. Show more Show less

WHAT YOU DO AT AMD CHANGES EVERYTHING We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences - the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world’s most important challenges. We strive for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives. AMD together we advance_ SMTS SILICON DESIGN ENGINEER The Role The position will involve working with a very experienced CPU physical design team. The person is responsible for delivering the physical design of critical CPU units to meet challenging goals for frequency, power, and other design requirements for AMD's next-generation processors in a fast-paced environment with cutting-edge technology. The Person Engineer with a good attitude, strong analytical skills, effective communication, and excellent problem-solving abilities. Key Responsibilities Own critical CPU units and drive to convergence from RTL-to-GDSII - synthesis, floor-planning, place and route, timing closure, and signoff Understand the micro-architecture to perform feasibility studies on performance, power, and area (PPA) tradeoffs for design closure. Develop and improve physical design methodologies and customize recipes across various implementation steps to optimize PPA. Implement floor plan, synthesis, placement, CTS, Timing Closure, Routing, Extraction, Physical Verification (DRC & LVS), EM/IR and signoff. Handling different PNR tools - Synopsys fusion compiler, Cadence, PrimeTime, StarRC, Calibre, Apache Redhawk Preferred Experience 12+ years of professional experience in physical design, preferably with high-performance designs. Must have closed high-performance IPs- CPU/GPU/DPU/memory controller, etc. Strong experience with tools for logic synthesis, place and route, timing analysis, and design checks for physical and electrical quality; familiarity with tools for schematics, layout, and circuit/logic simulation Versatility with scripts to automate design flow - Perl/Tcl/Python Strong communication skills, ability to multi-task across projects, and work with geographically spread out teams Experience in advanced sub 7nm nodes Excellent physical design and timing background. A good understanding of computer architecture is preferred. Strong analytical/problem-solving skills and pronounced attention to detail. Academic Credentials Qualification: Bachelors or Masters in Electronics/Electrical Engineering Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process. Show more Show less

Job Title: PCB Designer (Cadence Allegro) – 2 to 3 Years Experience Location: Bengaluru Job Type: Full-Time Experience: 2–3 Years Industry: Electronics / Semiconductor / Hardware Department: Engineering / Hardware Design Job Description: We are seeking a motivated and detail-oriented PCB Designer with 2–3 years of hands-on experience in Cadence Allegro to join our hardware design team. The ideal candidate will be responsible for translating schematic diagrams into precise PCB layouts that meet electrical, mechanical, and manufacturing requirements. Key Responsibilities: Create multi-layer PCB layouts using Cadence Allegro PCB Designer software. Collaborate with hardware engineers to interpret schematics and define layout constraints. Perform component placement, routing, and optimization based on electrical and thermal considerations. Generate and validate manufacturing outputs (Gerber, ODB++, drill files, BOM). Perform DRC (Design Rule Check), ERC (Electrical Rule Check), and resolve design issues. Work with the fabrication and assembly teams to resolve design-related manufacturing concerns. Maintain PCB libraries and ensure adherence to company design standards. Support design reviews and make necessary modifications based on feedback. Requirements: Bachelor’s Degree or Diploma in Electronics Engineering or a related field. 2–3 years of proven experience in PCB layout design using Cadence Allegro . Good understanding of signal integrity, power distribution, and EMI/EMC best practices. Familiarity with high-speed design, differential pairs, impedance control, and HDI boards is a plus. Strong attention to detail and ability to handle multiple design projects simultaneously. Effective communication and teamwork skills. Preferred Skills: Experience with schematic capture tools (e.g., OrCAD Capture). Knowledge of IPC standards and DFM/DFT practices. Experience in working with contract manufacturers and fabrication houses. Show more Show less

Job description Orbitt Space is building sustainable satellite platforms powered by cutting-edge electric propulsion technology to enable long-duration missions in Ultra Low Earth Orbit (ULEO). Your Role You will be responsible for designing, laying out, prototyping, and validating printed circuit boards (PCBs) from initial concept to full production. You will own the entire board development lifecycle, ensuring each design is delivered reliably and on schedule. Responsibilities Design schematics and multilayer PCB layouts optimizing performance, cost, and reliability Choose components with focus on performance, cost, lifecycle, and maintain clean CAD component and part libraries Perform stack-up, impedance, and signal integrity checks; ensure first-pass success with DRC/DFM Generate fab/assembly files (Gerbers, BOMs, pick-and-place) and document all design work Apply design rules for signal/power integrity across digital, analog, and mixed-signal circuits Work closely with cross-functional teams to define, review, and integrate PCB designs Manage vendors, create test plans, bring up boards, and debug with lab tools Good to have : Experience with aerospace PCB design and library management Core Requirements Minimum 3 years of end-to-end PCB design and layout experience with production hardware in volume manufacturing. Expertise with at least one modern PCB CAD suite (e.g. Altium Designer) and familiarity with basic simulation tools for PI/SI analysis. Solid understanding of PCB stack-ups, controlled-impedance routing, differential pairs, power distribution, grounding, EMC/EMI mitigation, and DFM / DFA best practices. Strong written and verbal communication skills, excellent organizational habits, and the initiative to drive designs from concept to production with minimal supervision. Why Join Orbitt Space? Competitive salary based on experience and expertise. Performance-based bonuses. Health and wellness benefits. Training and professional development opportunities. 📧 If you're excited about this role, we’d love to hear from you! Reach out to us at hr@orbitt.space Show more Show less

Primary & Mandatory Skill: Python, Docker/Kubernetes Level: SA Client Round (Yes/ No): No Location Constraint if any : No Shift timing: 2-11pm JD: Good hands in Python scripting Experience in Docker & Kubernetes

Company Description At Front End Solutions, we are committed to providing global Printed Circuit Board (PCB) manufacturers with high-quality CAM editing solutions with partner CAM TOOL Soft Services.Our team of experts leverages cutting-edge technology to offer customized solutions that help businesses cut costs and expedite production. Role Description This is a full-time PCB CAM Engineer role at CAM TOOL Soft Services located in Ahmedabad and Rajkot branch. The PCB CAM Engineer will be responsible for designing and programming to generate tool for manufacturing and working closely with other teams to ensure optimal designs for PCBs. They will also be responsible for DFM requirements for the company. Qualifications • Bachelor's degree in Electrical Engineering or related field, or equivalent work experience • Proficiency with CAM tools such as Genesis, CAM350 and UCAM • Experience with PCB DRC, including layer stackup and planning • Knowledge of manufacturing processes for PCB • Strong troubleshooting and problem-solving skills • Able to work all shifts with rotation policy. • Excellent communication and collaboration skills • Ability to work effectively in a team enviroment Show more Show less

Sr. Manager Analog Design Hyderabad, India Engineering 63804 Job Description WHAT YOU DO AT AMD CHANGES EVERYTHING We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences – the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world’s most important challenges. We strive for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives. AMD together we advance_ PREFERRED EXPERIENCE: Analog/Mixed signal design lead with 16+ years of professional experience in the semiconductor industry with focus on analog/mixed signal silicon IP design and development. Experience successfully leading small to medium size analog/mixed signal design engineering teams. Able to lead a team effectively, with good interpersonal skills, enthusiasm and positive energy. Analytical thinking, inventive, and Quality-oriented mindset. Strong and effective technical and management communication at the peer and upward management levels. Hand-on design experience in high-speed serial and/or parallel (memory, SerDes, die-to-die interfaces) PHY/IO designs. Strong fundamentals and knowledge of mixed signal circuit architecture and design techniques for IO receiver/transmitter analog-front-end (AFE) and PLL/DLL/clocking (PCIE, USB,…,LPDDR, HBM, gDDR, …, UCIE, …) Design Experience in FinFET nodes such as 16/14/10/7/5/3nm nodes with a solid understanding of transistor device performance and fundamentals A track record of successful design and productization of analog/mixed signal silicon IPs. Direct hands-on experience in the following PHY/IO-AFE/PLL/Clocking circuits architecture and design. In-depth knowledge of analog, digital, and semi-digital circuit architecture Experience in high-speed custom digital and low power design techniques is highly desirable. knowledge of AMS EDA industry-standard tools and best-in-class design practices/methodologies for analog/mixed signal design. Proficient in AMS design flows, tools, and methodologies. Familiar with Cadence schematic capture/virtuoso, Spectre/HSPICE/other circuit simulation tools Excellent written and verbal communication skills able to operate without direct supervision but also work cross-functionally, cross-geographies collaborating and being part of a multi-disciplinary team in a dynamic environment. strong initiative and ownership. Seek help proactively as well as share and pass on knowledge Master’s degree in electrical engineering. PhD is preferred KEY RESPONSIBILITIES: Lead and manage a team of analog/mixed signal silicon designers Responsibilities include detailed circuit design schedule planning, work breakdown, design tasks assignments and progress tracking, prioritization, team members performance review, technical mentoring for junior team members. Work with project/IP director, and other cross-functional leads, system architects, SOC designers and physical designers to guarantee quality/timely deliverables meeting schedule and technical requirements Contribute to the definition of analog circuit architecture for the various AMS blocks. Work with other design functions domains across different geographies and time zones, to ensure successful cross-functional team engagement and high-quality execution Ensure quality of work within schedule and mitigate overall risk. Proven Track record of successfully taking designs to production Contribute to the definition of AMS design flows toward improving team productivity, efficiency and quality of execution. Influence development of AMS design workflows and methodology for best in-class/best PPA circuits designs. Complete bottom-up schedule planning and manage analog/mixed circuit design/verification activities guaranteeing AMS IP/sub-blocks designs meets performance, power, reliability and timing requirements. Work closely with the layout design teams to deliver the DRC rules compliant physical design GDSII Deliver AMS Block production/bench-level test plans for post-silicon characterization/validation. Enable/Support Post-Silicon teams’ activities toward validation and characterization of mixed IP (Performance, Power, Functionality, ..) ensuring production silicon meets all committed design and compliance specifications. #LI-PK2 AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

Sr. Silicon Design Engineer Hyderabad, India Engineering 64959 Job Description WHAT YOU DO AT AMD CHANGES EVERYTHING We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences – the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world’s most important challenges. We strive for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives. AMD together we advance_ SE NIOR SILICON DESIGN ENGINEER THE ROLE: The position will involve working with a very experienced physical design team of Server SOC and is responsible for delivering the physical design of tiles to meet challenging goals for frequency, power and other design requirements for AMD next generation processors in a fast-paced environment on cutting edge technology. THE PERSON: Engineer with good attitude who seeks new challenges and has good analytical and and problem-solving skills. Candidate needs to have the ability and desire to learn quickly and should be a good team player who has excellent communication skills and experience collaborating with other engineers located in different sites/timezones. KEY RESPONSIBILITIES: Implementing RTL to GDS2 flow Handling Floor-plan, Physical Implementation of Power-plan, Synthesis, Placement, CTS, Timing Closure, Routing, Extraction, Physical Verification (DRC & LVS), Crosstalk Analysis, EM/IR Handling different PNR tools - Synopsys ICC2, ICC, Design Compiler, PrimeTime, StarRC, Mentor Graphics Calibre, Apache Redhawk PREFERRED EXPERIENCE: 4+ years of professional experience in physical design, preferably with high performance designs. Experience in automated synthesis and timing driven place and route of RTL blocks for high speed datapath and control logic applications. Experience in automated design flows for clock tree synthesis, clock and power gating techniques, scan stitching, design optimization for improved timing/power/area, and design cycle time reduction. Experience in floorplanning, establishing design methodology, IP integration, checks for logic equivalence, physical/timing/electrical quality, and final signoff for large IP delivery Strong experience with tools for logic synthesis, place and route, timing analysis, and design checks for physical and electrical quality, familiarity with tools for schematics, layout, and circuit/logic simulation Versatility with scripts to automate design flow. Strong communication skills, ability to multi-task across projects, and work with geographically spread out teams Experience in FinFET & Dual Patterning nodes such as 16/14/10/7/5nm Excellent physical design and timing background. Good understanding of computer organization/architecture is preferred. Strong analytical/problem solving skills and pronounced attention to details. ACADEMIC CREDENTIALS: Qualification: Bachelors or Masters in Electronics/Electrical Engineering LOCATION: Hyderabad / Bangalore #LI-PK2 AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

PMTS Silicon Design Engineer Hyderabad, India Engineering 64620 Job Description WHAT YOU DO AT AMD CHANGES EVERYTHING We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences – the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world’s most important challenges. We strive for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives. AMD together we advance_ PMTS SILICON DESIGN ENGINEER THE ROLE: The position will involve working with a very experienced physical design team of Server SOC and is responsible for delivering the physical design of tiles and FullChip to meet challenging goals for frequency, power and other design requirements for AMD next generation processors in a fast-paced environment on cutting edge technology. THE PERSON: The ideal candidate has significant experience in industry, with good attitude who seeks new challenges and has good analytical and problem-solving skills. You have excellent communication and presentation skills, demonstrated through technical publications, presentations, trainings, executive briefings, etc. You are meticulous about Power, Performance and Area while driving schedule and managing cost. You are highly adept at collaboration among top-thinkers and engineers alike, ready to mentor and guide, and help to elevate the knowledge and skills of the team around you. KEY RESPONSIBILITIES: RTL to GDS2 flow Handling Floor-plan, Physical Implementation of Power-plan, Synthesis, Placement, CTS, , Routing, Extraction, Timing Closure (Tile level, Full chip), Physical Verification (DRC & LVS), Crosstalk Analysis, EM/IR Handling different PNR tools - Synopsys FusionCompiler, Cadence Innovus, PrimeTime, StarRC, Mentor Graphics Calibre, Apache Redhawk Identify and implement opportunities for improving PPA PREFERRED EXPERIENCE: 16+ years of professional experience in physical design, preferably with high performance designs. Experience in automated synthesis and timing driven place and route of RTL blocks for high speed datapath and control logic applications. Experience in automated design flows for clock tree synthesis, clock and power gating techniques, scan stitching, design optimization for improved timing/power/area, and design cycle time reduction. Experience in floorplanning, establishing design methodology, IP integration, checks for logic equivalence, physical/timing/electrical quality, and final signoff for large IP delivery Strong experience with tools for logic synthesis, place and route, timing analysis, and design checks for physical and electrical quality, familiarity with tools for schematics, layout, and circuit/logic simulation Experience in STA, full chip timing Versatility with scripts to automate design flow. Proficiency in scripting language, such as, Perl and Tcl. Strong communication skills, ability to multi-task across projects, and work with geographically spread out teams Experience in FinFET & Dual Patterning nodes such as 16/14/10/7/5nm/3nm Excellent physical design and timing background. Good understanding of computer organization/architecture is preferred. Strong analytical/problem solving skills and pronounced attention to details. ACADEMIC CREDENTIALS: Qualification: Bachelors or Masters in Electronics/Electrical Engineering #LI-PK2 AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

RTL Design Engineer Hyderabad, India Engineering 58632 Job Description WHAT YOU DO AT AMD CHANGES EVERYTHING We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences – the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world’s most important challenges. We strive for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives. AMD together we advance_ Sr SILICON DESIGN ENGINEER THE ROLE: As a Silicon Design Engineer, you will work with formal experts and designers to verify formal properties and drive convergence. THE PERSON: You have a passion for modern, complex processor architecture, digital design, and verification in general. You are a team player who has excellent communication skills. You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems. Job deliverables: Setup ASIC QA flows for RTL design quality checks. Understand the design: top level interfaces, clock structure, reset structure, RAMs, CDC boundaries, power domains. Running Lint, Synthesis, LEC, Static timing analysis, CDC, RDC, DFT, CLP steps. Come up with clock constraints, false paths, multi-cycle paths, IO delays, exceptions and waivers. Checking the flow errors, design errors & violations and reviewing the reports. Debugging CDC, RDC issues and come up with the RTL fixes. Supporting DFX team for DFX controller integration, Scan insertion, MBIST insertion and DFT DRC & MBIST checks. Handling multiple PNR blocks, building wrappers and propagating constraints, waivers, etc. Flows or Design porting to different technology libraries. Generating RAMs based on targeted memory compilers and integrating with the RTL. Running functional verification simulations as needed. Job Requirements: B.E/M.E/M.Tech or B.S/M.S in EE/CE with 5+ years of relevant experience ASIC design flow and direct experience with ASIC design in sub-20nm technology nodes Digital design and experience with RTL design in Verilog/SystemVerilog Modern SOC tools including Spyglass, Questa CDC, Cadence Conformal, VCS simulation Preferred experience in AXI4 or NOC protocols or DRAM memory interfaces. TCL, Perl, Python scripting PREFERRED EXPERIENCE: Project level experience with design concepts and RTL implementation for same Experience or familiarity with formal tools and/or functional verification tools by VCS, Cadence, Mentor Graphics Good understanding of computer organization/architecture ACADEMIC CREDENTIALS: Bachelors or Masters degree in computer engineering/Electrical Engineering #LI-RP1 AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. As an Director-HBM Layout, you will work with an exceptionally talented, passionate core team based in India, lead the team to design for intensive applications such as artificial intelligence and high-performance computing solution, High Bandwidth Memory. You will be collaborating with peer teams crossing Micron global footprint, to meet scheduled milestones in a multiple projects-based environment. Responsibilities Provide leadership in building and growing a Custom and Semi-custom layout team from the ground up to support Micron’s HBM team's requirement. Provide leadership in developing Custom and semicustom layout to meet schedule and milestone. Provide leadership in training the team’s technical skills and cultural healthiness. Effectively communicating with global engineering teams to assure the success HBM roadmap. Organize, prioritize, and manage logistic on tasks and resource allocations for multiple projects. Manage performance and development of team members. Managing hiring and retention. As a critical member of the core HBM leadership team in India, contribute to the overall success of the Micron's HBM India operation. Qualification/Requirements 18 + year experience in analog/custom layout in advanced CMOS process, in various technology nodes (Planar, FinFET ) Minimum 4+ years people management experience. Expertise in Cadence VLE/VXL and Mentor Graphic Calibre DRC/LVS is a must. Must have strong skills in layout and floor planning skills and manual routing. Strong ability to build, and continuously develop a premier analog/mixed-signal layout team. Experienced in managing multiple Custom IC layout projects. Highly motivated with passion, detail oriented, systematic and methodical approach in IC layout design. The ability to work and communicate effectively in a team and to be able to multi-task effectively in a fast-paced working environment. Excellent verbal and written communication skills required. Independent with strong analytical skills, creative thinking and self-motivated. Capable of working in a cross functional, multi-site team environment in multiple time zones. Previous work experience in DRAM/NAND layout design is desirable however not mandatory. Strong passion and ability to attract, hire, retain engineers by motivating them and by inculcating innovation culture. Ability to collaborate with overseas Teams to define strategy, plan, and execute across the larger, global organization. Be accountable for the proper technical solutions implemented by your team. About Micron Technology, Inc. We are an industry leader in innovative memory and storage solutions transforming how the world uses information to enrich life for all . With a relentless focus on our customers, technology leadership, and manufacturing and operational excellence, Micron delivers a rich portfolio of high-performance DRAM, NAND, and NOR memory and storage products through our Micron® and Crucial® brands. Every day, the innovations that our people create fuel the data economy, enabling advances in artificial intelligence and 5G applications that unleash opportunities — from the data center to the intelligent edge and across the client and mobile user experience. To learn more, please visit micron.com/careers All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, veteran or disability status. To request assistance with the application process and/or for reasonable accommodations, please contact hrsupport_india@micron.com Micron Prohibits the use of child labor and complies with all applicable laws, rules, regulations, and other international and industry labor standards. Micron does not charge candidates any recruitment fees or unlawfully collect any other payment from candidates as consideration for their employment with Micron.

Company: Qualcomm India Private Limited Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. Qualcomm Noida CPU team is hiring for developing high performance and power optimized custom CPU cores. Individuals to Handle hardening complex HMs from RTL to GDS [ Synthesis, PNR, Timing ]. We are excited to add folks with us for the most cutting-edge work. Here, individuals would have the opportunity to work with some of the most talented and passionate engineers in the world to create designs that push the envelope on performance, energy efficiency and scalability. We offer a fun, creative and flexible work environment, with a shared vision to build products to change the world. Desired experience: 5+ years experience in physical verification post BTECH / MTECH. Expertise in DRC, LVS, PERC, ERC, SOFTCHECK, DFM etc. Efficient fixing of DRCs in INNOVUS OR FC. Completely aware about CALIBRE , VIRTUSO Good scripting skills and automation. Applicants : Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries). Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law. To all Staffing and Recruiting Agencies : Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications. If you would like more information about this role, please contact Qualcomm Careers.

We Are: At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation. You Are: You are a skilled Layout Engineer with 3-6 years of experience, specializing in Analog and Mixed-Signal IP layout. You have a background in Electronics or Electrical Engineering, holding a B.Tech or M.Tech degree. You possess a strong understanding of high-speed analog layout and have a solid grasp of CMOS and FinFET layouts. Your expertise extends to using CAD tools such as Custom Designer/Cadence Virtuoso, Calibre, ICV, and STAR-RCXT. You are adept at working independently, determining and developing solutions with minimal supervision. You frequently collaborate with senior personnel and are proactive in learning new technologies, demonstrating excellent analytical and problem-solving skills. Your strong communication skills enable effective interaction with internal development teams. What You’ll Be Doing: Developing physical layout of high-speed Analog Integrated Circuits for the Analog and Mixed Signal IP group. Collaborating with a team of Analog/Mixed Signal Custom Layout Design Engineers on SerDes and Analog Mixed Signal IP blocks. Using advanced floor-planning techniques to optimize layout designs. Performing verification flows and ensuring compliance with DRC/LVS, LPE standards. Debugging and troubleshooting layout issues, utilizing your analytical skills. Providing regular updates to the manager on project status and networking with internal and external personnel. The Impact You Will Have: Contributing to the development of high-performance silicon chips that drive modern technology. Enhancing the reliability and efficiency of Analog and Mixed-Signal IP blocks. Ensuring the successful integration of high-speed signal layouts in cutting-edge applications. Improving the verification and validation processes through meticulous layout designs. Supporting the continuous innovation of Synopsys’ product offerings. Playing a key role in the development of next-generation electronic devices. What You’ll Need: Experience in Analog Mixed-signal IP layout and verification of high-speed analog layout. Advanced understanding of Deep submicron effects and mitigation techniques. Expertise in CMOS and FinFET layouts and process technology. Familiarity with ESD and latchup layout design considerations. Proficiency in CAD tool usage, including Custom Designer/Cadence Virtuoso, Calibre, ICV, and STAR-RCXT. Who You Are: You are a dedicated and detail-oriented professional with a strong desire to learn and explore new technologies. Your excellent analytical and problem-solving skills enable you to address complex layout challenges. You are a proactive communicator, capable of interacting effectively with internal teams and external personnel. Your ability to work independently and collaboratively ensures the successful completion of projects. The Team You’ll Be A Part Of: You will join the Analog and Mixed Signal IP group, a dynamic team focused on developing high-performance Analog Integrated Circuits. The team consists of skilled Layout Design Engineers who are passionate about innovation and excellence. Together, you will work on cutting-edge projects, contributing to the advancement of Synopsys’ technology. Rewards and Benefits: We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process. Show more Show less

Responsibilities: * Create detailed layout designs using Virtuoso software. * Perform physical verification through DRC, LVS, ESD checks. * Collaborate with cross-functional teams on floor planning and antenna integration. Annual bonus

www.Sevyamultimedia.com Physical Design Manager / Senior Manager About Us We are a technology consulting company delivering best-in class Chip Design Services. Founded in 2008, we partner with top semiconductor companies in building a connected, safer tomorrow. With over 40+ tapeouts and expertise spanning the breadth of chip design, we offer a wide variety of Semiconductor skills SoC Design RTL Design, Integration, Lint/CDC/RDC, UPF IP/SoC UVM Verification PPA, Synthesis, Constraints Management Physical Design, Timing Closure, ECOs Sign-off - Timing, Power, EM/IR, DRC/LVS/ERC Approach We support a mix of engagement models to support diverse client requirements. Engagement Models Turnkey (SoW) Engagement Staff Augmentation (T&M) Offshore Design Center Key Enablers Hands on Leadership Proven Industry Experts TSMC DCA Parternship Collaboration with Academia ================ Physical Design Manager / Senior Manager #### **Job Summary:** We are seeking a highly experienced, hands-on and motivated Physical Design Manager/ Director to lead our physical design team. The ideal candidate will have extensive experience in block and top-level implementation, RDL/bump, pad location, EM/IR analysis, timing closure, physical verification closure, CAD flow bring-up, automation, planning, and estimation. This role involves managing complex design projects, leading a team of engineers, and ensuring the successful execution of physical design tasks from planning to tape-out. #### **Key Responsibilities:** - **Team Leadership:** - Lead, mentor, and manage a team of physical design engineers. - Foster a collaborative and innovative team environment. - Develop team skills through training and professional development initiatives. - **Project Management:** - Plan and estimate physical design tasks, resources, and schedules. - Track and report on project progress, ensuring timely delivery of milestones. - Coordinate with cross-functional teams, including design, verification, and packaging, to align physical design activities with project goals. - **Block and Top-Level Implementation:** - Perform and oversee block-level and top-level physical design implementation. - Ensure designs meet performance, power, area, and manufacturability requirements. - Perform detailed floorplanning, placement, and routing. - Constraints clean up, robustness of implementation - Timing feedback to design team and sign-off timing. - **RDL/Bump and Pad Location:** - Manage redistribution layer (RDL) and bump design for advanced packaging. - Optimize pad location for signal integrity and manufacturability. - **EM/IR Analysis and Timing Closure:** - Conduct electromigration (EM) and IR drop analysis to ensure robust power delivery. - Achieve timing closure through detailed static timing analysis (STA) and optimization. - **Physical Verification Closure:** - Perform physical verification (PV) closure, including design rule checking (DRC) and layout versus schematic (LVS). - Ensure designs comply with foundry and industry standards. - **CAD Flow and Automation:** - Develop and bring up CAD flows for physical design tasks. - Implement automation scripts to enhance efficiency and productivity. - **Continuous Improvement:** - Stay updated with the latest industry trends, tools, and methodologies in physical design. - Drive continuous improvement initiatives to enhance design processes and methodologies. - Implement best practices for physical design and contribute to the development of standards and processes. #### **Qualifications:** - **Education:** - Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related field. - **Experience:** - 10-15+ years of experience in physical design, with at least 3 years in a managerial or leadership role. - **Technical Skills:** - Extensive experience in block and top-level physical design implementation. - Proficiency in RDL/bump design and pad location optimization. - Strong knowledge of EM/IR analysis and timing closure techniques. - Experience with physical verification closure (DRC, LVS). - Familiarity with CAD flow development and automation. - **Soft Skills:** - Excellent leadership and team management abilities. - Strong problem-solving and analytical skills. - Effective communication and interpersonal skills. - Ability to work in a fast-paced, dynamic environment and manage multiple projects simultaneously. #### **Preferred Qualifications:** - Experience with advanced node technologies (e.g., FinFET, SOI). - Knowledge of scripting languages (e.g., Python, Perl) for automation. - Experience with EDA tools such as Cadence, Synopsys, or Mentor Graphics. Contact: Uday Mulya Technologies muday_bhaskar@yahoo.com "Mining The Knowledge Community" Show more Show less