431 Drc Jobs - Page 5

About The Role Role Purpose The purpose of this role is to perform the development of VLSI system by defining the various functionalities, architecture, layout and implementation for a client ? Do 1. Conduct verification of the module/ IP functionality and provide customer support a. Understand the architecture of the module or the IP and create verification environment and the development plan as per Universal Verification Methodology b. Create test bench development and test case coding of the one or multiple module c. Write the codes or check the code as required d. Execute the test cases and debug the test cases if required e. Conduct functional coverage analysis and document the test cases including failures and debugging procedures on SharePoint/ JIRA or any other platform as directed f. Test the entire IP functionality under regression testing and complete the documentation to publish to client g. Troubleshoot, debug and upgrade existing systems on time & with minimum latency and maximum efficiency h. Write scripts for the IP i. Comply with project plans and industry standards 2. Ensure reporting & documentation for the client a. Ensure weekly, monthly status reports for the clients as per requirements b. Maintain documents and create a repository of all design changes, recommendations etc c. Maintain time-sheets for the clients d. Providing written knowledge transfer/ history of the project ? Deliver No. Performance Parameter Measure 1. Verification Timeliness Quality of Code/ Number of defects Customer responsiveness Project documentation (scripts, test cases etc) 2. Self-development Skill test for next level clearance on Trend Nxt ? ? Mandatory Skills: Semiconductor Integration. Experience3-5 Years. Reinvent your world. We are building a modern Wipro. We are an end-to-end digital transformation partner with the boldest ambitions. To realize them, we need people inspired by reinvention. Of yourself, your career, and your skills. We want to see the constant evolution of our business and our industry. It has always been in our DNA - as the world around us changes, so do we. Join a business powered by purpose and a place that empowers you to design your own reinvention. Come to Wipro. Realize your ambitions. Applications from people with disabilities are explicitly welcome.

Wipro Limited (NYSEWIT, BSE507685, NSEWIPRO) is a leading technology services and consulting company focused on building innovative solutions that address clients’ most complex digital transformation needs. Leveraging our holistic portfolio of capabilities in consulting, design, engineering, and operations, we help clients realize their boldest ambitions and build future-ready, sustainable businesses. With over 230,000 employees and business partners across 65 countries, we deliver on the promise of helping our customers, colleagues, and communities thrive in an ever-changing world. For additional information, visit us at www.wipro.com. About The Role _x000D_ Role Purpose The purpose of this role is to perform the development of VLSI system by defining the various functionalities, architecture, layout and implementation for a client ? _x000D_Do 1. Conduct verification of the module/ IP functionality and provide customer support a. Understand the architecture of the module or the IP and create verification environment and the development plan as per Universal Verification Methodology b. Create test bench development and test case coding of the one or multiple module c. Write the codes or check the code as required d. Execute the test cases and debug the test cases if required e. Conduct functional coverage analysis and document the test cases including failures and debugging procedures on SharePoint/ JIRA or any other platform as directed f. Test the entire IP functionality under regression testing and complete the documentation to publish to client g. Troubleshoot, debug and upgrade existing systems on time & with minimum latency and maximum efficiency h. Write scripts for the IP i. Comply with project plans and industry standards 2. Ensure reporting & documentation for the client a. Ensure weekly, monthly status reports for the clients as per requirements b. Maintain documents and create a repository of all design changes, recommendations etc c. Maintain time-sheets for the clients d. Providing written knowledge transfer/ history of the project ? _x000D_ Deliver No. Performance Parameter Measure 1. Verification Timeliness Quality of Code/ Number of defects Customer responsiveness Project documentation (scripts, test cases etc) 2. Self-development Skill test for next level clearance on Trend Nxt ? _x000D_ ? _x000D_ Reinvent your world. We are building a modern Wipro. We are an end-to-end digital transformation partner with the boldest ambitions. To realize them, we need people inspired by reinvention. Of yourself, your career, and your skills. We want to see the constant evolution of our business and our industry. It has always been in our DNA - as the world around us changes, so do we. Join a business powered by purpose and a place that empowers you to design your own reinvention. Come to Wipro. Realize your ambitions. Applications from people with disabilities are explicitly welcome.

 Job Title: Electrical Engineer Experience: 3 to 5 Years Location: Gayatri Building, Technopark, Thiruvananthapuram (Work from Office) Overview: NilaSoft is seeking a skilled and motivated Electrical Engineer to join our growing engineering division. The selected candidate will be part of a collaborative team responsible for delivering high-quality electrical designs and technical documentation. You will contribute across the full product lifecycle—from PCB layout to documentation and design release—ensuring that all outputs align with best practices and industry standards. Key Responsibilities: Take ownership of Altium Designer tool usage and ensure all PCBAs conform to design standards and project requirements. Maintain a cloud-based component footprint library, ensuring complete accuracy and consistency across all NilaSoft PCB designs. Work with PCBA vendors to define design rules (DRC), manufacturing/test guidelines (DFM/DFT), and review protocols. Collaborate with design engineers to perform and review PCB layouts in accordance with project timelines. Standardize PCBA output formats and improve design release processes using version control systems. Create and manage technical documentation including wiring diagrams, cable designs, test protocols, procedures, and reports. Ensure timely document release through the Engineering Change Order (ECO) process, upholding version control and documentation standards. Required Qualifications: Bachelor’s or Master’s degree in Electrical Engineering or a related field. Minimum 3 years of professional experience, particularly in PCB design. Proven ability to work proactively and collaboratively in engineering environments. Strong interpersonal and vendor coordination skills. Experience in developing and maintaining accurate component footprint libraries. Solid understanding of PCB manufacturing and assembly processes. Proficient in Altium Designer for schematic design, layout, and multi-layer board development. Track record of delivering reliable, rework-minimized PCBA designs. Skilled in ECO documentation and managing design release processes. Competent in technical drawing tools (e.g., Microsoft Visio) and committed to producing well-structured engineering documents. Why Join Us? Be part of cutting-edge semiconductor automation projects. Work in a dynamic and growth-focused environment. Competitive compensation and career development opportunities. If you are passionate about creating engineering solutions and want to work in a high-tech industry, we would love to hear from you! Join our team! Rush your resume to hr@nila-soft.com Show more Show less

1. Hands on work on custom layout for analog blocks like High Speed SerDes and General purpose IO designs with Cadence Virtuoso on latest technologies like 5nm and below and also take leadership roles in delivery of IPs 2. Work on Floor planning, power design, signal routing strategy, EMIR awareness andparasitic optimisations 3. Understand and apply analog Layout techniques to ensure the design meets performance with minimum possible area and good yield. 4. Participate in building and enhancing layout flow for faster, higher quality design process. 5. Checking physical verifications like DRC/LVS/ERC/ANT/DFM and other IBM internal checks 6. Collaborate with Circuit Designers to solve challenging problems 7. Writing /PYTHON scripts to automate repetitive tasks 8. Work with Place and Route engineer to integrate custom macros into top level. 9. Able to perform design reviews across global team 10. Work closely with required global teams to ensure the success of the whole product. 11. Leadership in delivery of macros we plan to own from India Job requirements: 1. Experience in doing layouts for analog blocks like SerDes, ADCs, DACs, LDOs, PLLs, BGAP & amplifiers etc. 2. Experience in designing layouts for high-speed circuits is a plus. 3. Layout experience in the following technology nodes3nm, 5nm and 7nm FinFET. 4. Good team worker with multi-discipline, multi-cultural and multi-site environments 5. Strong fundamental knowledge in semiconductor device physics, layout principles, IC reliability and failure mechanisms6. Good problem-solving skills are essential where problems are analysed upfront, identifying gaps, and providing optimum solutions7. Knowledge in Skill/perl/tcl/Python scripting is a plus. Required education Bachelor's Degree Preferred education Master's Degree Required technical and professional expertise The Analog layout design engineer with experience in next generation Ultra high speed serial IO link (HSS) interface for Cognitive, ML,DL, and data center applications. The engineer needs to have knowledge in the design and development full custom analog layouts for ultra high speed 32G/50G/112G IO link interfaces. Preferred technical and professional experience Experience in 3,5,7,14 nm analog layout design. Working on Cutting edge technology and HSS domain . Quick learner, deep layout design knowledge, problem solving skills and good communication skills with cross teams across the Geos.

Sr. Silicon Design Engineer Hyderabad, India Engineering 66192 Job Description WHAT YOU DO AT AMD CHANGES EVERYTHING We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences – the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world’s most important challenges. We strive for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives. AMD together we advance_ SE NIOR SILICON DESIGN ENGINEER THE ROLE: The position will involve working with a very experienced physical design team of Server SOC and is responsible for delivering the physical design of tiles to meet challenging goals for frequency, power and other design requirements for AMD next generation processors in a fast-paced environment on cutting edge technology. THE PERSON: Engineer with good attitude who seeks new challenges and has good analytical and and problem-solving skills. Candidate needs to have the ability and desire to learn quickly and should be a good team player who has excellent communication skills and experience collaborating with other engineers located in different sites/timezones. KEY RESPONSIBILITIES: Implementing RTL to GDS2 flow Handling Floor-plan, Physical Implementation of Power-plan, Synthesis, Placement, CTS, Timing Closure, Routing, Extraction, Physical Verification (DRC & LVS), Crosstalk Analysis, EM/IR Handling different PNR tools - Synopsys ICC2, ICC, Design Compiler, PrimeTime, StarRC, Mentor Graphics Calibre, Apache Redhawk PREFERRED EXPERIENCE: 8+ years of professional experience in physical design, preferably with high performance designs. Experience in automated synthesis and timing driven place and route of RTL blocks for high speed datapath and control logic applications. Experience in automated design flows for clock tree synthesis, clock and power gating techniques, scan stitching, design optimization for improved timing/power/area, and design cycle time reduction. Experience in floorplanning, establishing design methodology, IP integration, checks for logic equivalence, physical/timing/electrical quality, and final signoff for large IP delivery Strong experience with tools for logic synthesis, place and route, timing analysis, and design checks for physical and electrical quality, familiarity with tools for schematics, layout, and circuit/logic simulation Versatility with scripts to automate design flow. Strong communication skills, ability to multi-task across projects, and work with geographically spread out teams Experience in FinFET & Dual Patterning nodes such as 16/14/10/7/5nm Excellent physical design and timing background. Good understanding of computer organization/architecture is preferred. Strong analytical/problem solving skills and pronounced attention to details. ACADEMIC CREDENTIALS: Qualification: Bachelors or Masters in Electronics/Electrical Engineering LOCATION: Hyderabad / Bangalore #LI-PK2 AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

WHAT YOU DO AT AMD CHANGES EVERYTHING We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences - the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world’s most important challenges. We strive for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives. AMD together we advance_ SENIOR SILICON DESIGN ENGINEER The Role The position will involve working with a very experienced physical design team of Server SOC and is responsible for delivering the physical design of tiles to meet challenging goals for frequency, power and other design requirements for AMD next generation processors in a fast-paced environment on cutting edge technology. THE PERSON: Engineer with good attitude who seeks new challenges and has good analytical and and problem-solving skills. Candidate needs to have the ability and desire to learn quickly and should be a good team player who has excellent communication skills and experience collaborating with other engineers located in different sites/timezones. KEY RESPONSIBILITIES: Implementing RTL to GDS2 flow Handling Floor-plan, Physical Implementation of Power-plan, Synthesis, Placement, CTS, Timing Closure, Routing, Extraction, Physical Verification (DRC & LVS), Crosstalk Analysis, EM/IR Handling different PNR tools - Synopsys ICC2, ICC, Design Compiler, PrimeTime, StarRC, Mentor Graphics Calibre, Apache Redhawk PREFERRED EXPERIENCE: 8+ years of professional experience in physical design, preferably with high performance designs. Experience in automated synthesis and timing driven place and route of RTL blocks for high speed datapath and control logic applications. Experience in automated design flows for clock tree synthesis, clock and power gating techniques, scan stitching, design optimization for improved timing/power/area, and design cycle time reduction. Experience in floorplanning, establishing design methodology, IP integration, checks for logic equivalence, physical/timing/electrical quality, and final signoff for large IP delivery Strong experience with tools for logic synthesis, place and route, timing analysis, and design checks for physical and electrical quality, familiarity with tools for schematics, layout, and circuit/logic simulation Versatility with scripts to automate design flow. Strong communication skills, ability to multi-task across projects, and work with geographically spread out teams Experience in FinFET & Dual Patterning nodes such as 16/14/10/7/5nm Excellent physical design and timing background. Good understanding of computer organization/architecture is preferred. Strong analytical/problem solving skills and pronounced attention to details. Academic Credentials Qualification: Bachelors or Masters in Electronics/Electrical Engineering LOCATION: Hyderabad / Bangalore Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process. Show more Show less

Full Chip Physical Design Engineer Job Summary: We are seeking a highly motivated and skilled engineer to join our SoC implementation team. You will be responsible for the physical design of complex ASICs and SoCs, working on full-chip floorplanning, integration, and signoff activities to meet aggressive PPA (Power, Performance, Area) goals. Key Responsibilities: Drive full chip-level physical design flow from RTL to GDSII. Ownership of chip-level floorplanning, partitioning, and integration. Collaborate with RTL, synthesis, DFT, and STA teams to resolve cross-functional issues. Implement place & route flows including timing closure, IR/EM, and congestion optimization. Perform physical verification (LVS/DRC/ERC) and work with foundries to fix violations. Manage static timing analysis (STA) at top level and work closely with timing owners for signoff. Handle power planning and power domain implementation (UPF/CPF-based). Contribute to methodology improvements and automation. Required Qualifications: Bachelor's or Master’s degree in Electrical/Electronics/Computer Engineering or related field. 3–6 years of experience in physical design with at least one full chip tapeout. Hands-on expertise with industry-standard tools such as Synopsys (ICC2, Fusion Compiler, PrimeTime), Cadence (Innovus), and Mentor (Calibre). Strong knowledge of physical design concepts: floorplanning, CTS, routing, timing closure, IR drop, EM, DRC/LVS. Proficiency in scripting languages like Tcl, Perl, Python, or Shell. Familiarity with hierarchical design and ECO flows. Experience: 3 to 6 Years. Location: Bangalore / Hyderabad . Notice Period: Less than 30 days Show more Show less

Contracts manager as per the JD given below for Agra Metro AGCC07. B.E. Civil Engineering PG in Construction/Contracts Management – preferred Sound knowledge in FIDIC red book Sound knowledge in project scheduling, EoT / Delay analysis and programming software like primavera and MSP. Experience in operations with good understanding of infrastructure works (Metros) Identification and monitoring of Project risks and opportunities in a timely manner. Drafting & Vetting of Contractual communications/project correspondences. Ensuring timely notices for various issues arising at site pertaining to Extension of time, variations, settlement of disputes. Handling of Delay and Disruption claims. Experience in Dispute resolution processes such as DAB, DRC, Conciliation, Mediation, Amicable settlement. Show more Show less

Role Description Physical Design Engineer Exp:4 to 7 Handled Netlist to GDS II at block level for multiple tape outs. Hands-on experience on technology nodes like 28nm, 20nm, 14nm, 10nm Good knowledge of EDA tools from Synopsys , Cadence and Mentor, particularly experience with ICC, PTSI, Encounter, Nanoroute, Calibre, StarRC Hands-on experience in floor planning, placement optimizations, CTS and routing. Hands-on experience in block/top level signoff STA, physical verification (DRC/LVS/ERC/antenna) checks and other reliability checks(IR/EM/Xtalk) Exposure in physical implementation of timing/functional ECO’s Good knowledge of VLSI process and device characteristics TCL, perl scripting. Skills Physical Design,DRC,LVS,ERC,antenna Show more Show less

Company Description Sandisk understands how people and businesses consume data and we relentlessly innovate to deliver solutions that enable today’s needs and tomorrow’s next big ideas. With a rich history of groundbreaking innovations in Flash and advanced memory technologies, our solutions have become the beating heart of the digital world we’re living in and that we have the power to shape. Sandisk meets people and businesses at the intersection of their aspirations and the moment, enabling them to keep moving and pushing possibility forward. We do this through the balance of our powerhouse manufacturing capabilities and our industry-leading portfolio of products that are recognized globally for innovation, performance and quality. Sandisk has two facilities recognized by the World Economic Forum as part of the Global Lighthouse Network for advanced 4IR innovations. These facilities were also recognized as Sustainability Lighthouses for breakthroughs in efficient operations. With our global reach, we ensure the global supply chain has access to the Flash memory it needs to keep our world moving forward. Job Description We are looking for technically sound and highly skilled High-speed SERDES IO PHY Layout designer with 12-15 years of experience. Apart from Serdes PHY Layout, the ideal candidate should have a strong background in analog/IO design principles, hands-on experience with layout tools, and a passion for solving challenging technical problems. Key Responsibilities: Develop and optimize Serdes PHY, analog and mixed-signal IC layouts, ensuring high performance and manufacturability. Collaborate with design engineers to understand design requirements and translate them into precise layouts. Strong experience in debugging DRC, ERC, LVS, EMIR and PERC issues independently. Work closely with the physical design team to integrate custom blocks into the overall chip design. Identify and resolve layout-related issues, providing creative solutions to meet design specifications. Conduct design reviews and provide technical feedback to improve layout practices and methodologies. Stay up-to-date with industry trends, tools, and technologies to continuously enhance layout processes. Qualifications 12-15 years of experience in Serdes Phy, Analog and Mixed-signal IC layout design. Proficiency in layout tools such as Cadence, Synopsys, or Mentor Graphics. Hands-on experience with custom layout design for various Serdes Phy, Analog and IO circuits is required, including expertise in Bandgap references, LDOs, Clocking circuits, GPIOs, DDR IOs. Familiarity with custom digital layout (i.e. high speed logic paths). Knowledge of signal integrity issues (i.e. clock/data routes, differential routing, shielding). Strong understanding of analog/IO design principles, including circuit performance and parasitic effects. Aware of layout techniques to mitigate ESD, latch-up issues. Holds advanced knowledge of CMOS and FinFET technologies and their impact on design and performance issues in deep sub-micron process nodes, specifically 5nm and below. Experience with layout concepts that incorporate reliability considerations, including techniques for managing electromigration (EM), IR drop, and self-heating. Experience with layout optimization for power, performance, and area (PPA) metrics. Excellent problem-solving skills and attention to detail. Effective communication and teamwork abilities. Preferred Skills: Knowledge of scripting languages (e.g., Skill,TCL and SVRF) for automation tasks. Qualifications Bachelor’s or Master’s degree in Electronics or Electrical Engineering Additional Information Sandisk thrives on the power and potential of diversity. As a global company, we believe the most effective way to embrace the diversity of our customers and communities is to mirror it from within. We believe the fusion of various perspectives results in the best outcomes for our employees, our company, our customers, and the world around us. We are committed to an inclusive environment where every individual can thrive through a sense of belonging, respect and contribution. Sandisk is committed to offering opportunities to applicants with disabilities and ensuring all candidates can successfully navigate our careers website and our hiring process. Please contact us at jobs.accommodations@sandisk.com to advise us of your accommodation request. In your email, please include a description of the specific accommodation you are requesting as well as the job title and requisition number of the position for which you are applying. Show more Show less

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. Job Description To develop & integrate foundry rule decks & technology files to support PDKs by using foundry provided process design kits as a starting point. PDK QA, verification and release methodology for decks and specialized setups including track patterns to aid in layout. Responsible for physical verification methodology, including installation, development, qualification, automation, and support – To develop scripts to automate LVS, DRC, RM,IR and Parasitic Extraction flows. And to support layout teams in verification flow issues. Ensuring QA of the integrated PDK’s with the custom design environment Add sub scripts to improve efficiency on QA process with adequate coverage. General tool usage support – real-time support of all tools, creating bug workarounds and filing CCRs with R&D Responsible for rule deck development - to implement process design rules into physical verification rules decks and QC for the rule decks. Responsible for interfacing with the design teams and foundry team to develop and verify our PDKs. Develop, own and maintain an automation frame work for efficiency improvement perspective for the design environment. Position Requirements Bachelor’s Degree in Electrical/Electronic Engineering or equivalent . 4-7 years of Work experience in PDK development and CAD enablement. Expertise in Cadence Python, SKILL, Perl programming languages. Knowledge of deep sub-micron CMOS processes, device physics and layout design. Experience with Cadence custom IC Virtuoso platform to create layout test structures, to validate verification rules and to troubleshoot errors. Experience in developing PDK device library components and definitions including SKILL parameterized cells (Pcell), symbols, CDF, callbacks, simulation/netlisting. Experience with physical verification tools for DRC, LVS and parasitic extraction, Cadence PVS, Assura is a plus. Working knowledge of revision control software (Git, sos, Subversion, Synchronicity, etc) Understanding on Pcell creation and enhancements to pcell parameters, device call backs etc is a plus Excellent technical problem solving skills. Excellent communication and presentation skills. We’re doing work that matters. Help us solve what others can’t. Show more Show less

Drafting, review and negotiation of contracts Confidential, Joint Venture, Consortium, Service provider agreements. Sound knowledge in FIDIC Contracts, NHAI Contracts, NPCIL Contracts, CPWD Contracts. Experience in operations with good understanding of infrastructure works Identification and monitoring of Project risks and opportunities in a timely manner. Drafting of Contractual communications/project correspondences. Ensuring timely notices for various issues arising at site pertaining to Extension of time, variations, settlement of disputes. Handling of Delay and Disruption claims. Must have knowledge in Indian Arbitration Act 1996(Amended on 2015 & 2019) and Indian Contract Act 1872. Experience in Dispute resolution processes such as DAB, DRC, Conciliation, Mediation, Amicable settlement (Preferred) Knowledge in project scheduling, EoT / Delay analysis and programming software like primavera and MSP. Show more Show less

Introduction Physical design team is responsible for designing high performance microprocessor blocks for IBM Power and z mainframe servers. Your Role And Responsibilities Responsible for high performance microprocessor blocks RTL to GDSII implementation Perform block level synthesis, floor-planning, placement and routing. Close the design to meet timing, power budget and area. Implement ECO's to address functional bugs and timing violations. Team player, with good problem solving and communication skills. Preferred Education Master's Degree Required Technical And Professional Expertise 5-8 years industry experience in physical design methodology. Good knowledge and hands on experience in physical design methodology which include logic synthesis,placement, clock tree synthesis, routing . Should be knowledgeable in physical verification ( LVS,DRC.. etc), Noise analysis, Power analysis and electro migration . Team player with good problem solving skills, communication skills and leadership skills. Preferred Technical And Professional Experience Automation skills in PYTHON, PERL ,SKILL and/or TCL Show more Show less

Job Description M.E./M.Tech in Electronics/Electrical Engineering with minimum of 10 years of strong, hands on Physical Design experience. Must have handled Netlist to GDS II at Top level or Hierarchical top level for at least 5 tape outs. Must have lead physical design team with hands on exposure in most of the following depending up on senior level or lead level role. Should have experience in 28nm & below technologies (preferably 20nm & below). Top level die size estimation, floor-planning, power estimation, power planning. IO Planning and package compatibility sign off. ESD analysis on IO ring and sign off. Netlist and constraint sign in checks and validation. Design implementation environment setup. Static and Dynamic power analysis at the top level. Netlist to GDS II implementation at chip level Hierarchical chip planning, block planning, block level constraint development, hierarchical clock tree implementation, block integration and chip finishing. Multimode multi corner optimization and closure at top level. Clock tree synthesis and advanced clock tree implementation at full chip level. Top level timing closure with sign off STA in MMMC with cross-talk and OCV. Top level ECO implementation strategy development for netlist, RTL and timing level changes Methodology development, customization as per the specific design need. Good hands-on knowledge in reference flows, excellent debugging skills. Scripting experience in Perl/TCL. Flow customization and fine tuning for Power, Performance, Area. Technical leadership and ability to mentor and make the team deliver. Strong inter-personal skills and ability to work with multiple teams. In depth exposure in Implementation in any of the following platforms. FC/ICC/Innovus; Tool exposure in Sign Off DRC/LVS : Calibre Timing sign off : Primetime PNA : Apache -Redhawk Job Type: Full-time Experience: Physical Design: 10-15 years Should have worked as technical lead for at least 2 projects. Requirement M.E./M.Tech in Electronics/Electrical Engineering with minimum of 10 years of strong, hands on Physical Design experience. Must have handled Netlist to GDS II at Top level or Hierarchical top level for at least 5 tape outs. Must have lead physical design team with hands on exposure in most of the following depending up on senior level or lead level role. Should have experience in 28nm & below technologies (preferably 20nm & below). Top level die size estimation, floor-planning, power estimation, power planning. IO Planning and package compatibility sign off. ESD analysis on IO ring and sign off. Netlist and constraint sign in checks and validation. Design implementation environment setup. Static and Dynamic power analysis at the top level. Netlist to GDS II implementation at chip level Hierarchical chip planning, block planning, block level constraint development, hierarchical clock tree implementation, block integration and chip finishing. Multimode multi corner optimization and closure at top level. Clock tree synthesis and advanced clock tree implementation at full chip level. Top level timing closure with sign off STA in MMMC with cross-talk and OCV. Top level ECO implementation strategy development for netlist, RTL and timing level changes Methodology development, customization as per the specific design need. Good hands-on knowledge in reference flows, excellent debugging skills. Scripting experience in Perl/TCL. Flow customization and fine tuning for Power, Performance, Area. Technical leadership and ability to mentor and make the team deliver. Strong inter-personal skills and ability to work with multiple teams. In depth exposure in Implementation in any of the following platforms. FC/ICC/Innovus; Tool exposure in Sign Off DRC/LVS : Calibre Timing sign off : Primetime PNA : Apache -Redhawk Job Type: Full-time Experience: Physical Design: 10-15 years Should have worked as technical lead for at least 2 projects. Show more Show less

At Juniper, we believe the network is the single greatest vehicle for knowledge, understanding, and human advancement the world has ever known. To achieve real outcomes, we know that experience is the most important requirement for networking teams and the people they serve. Delivering an experience-first, AI-Native Network pivots on the creativity and commitment of our people. It requires a consistent and committed practice, something we call the Juniper Way. Job Description At Juniper, we believe the network is the single greatest vehicle for knowledge, understanding, and human advancement the world has ever known. To achieve real outcomes, we know that experience is the most important requirement for networking teams and the people they serve. Delivering an experience-first, AI-Native Network pivots on the creativity and commitment of our people. It requires a consistent and committed practice, something we call the Juniper Way. Physical Design Engineer Experience: 4+ Years Job Specification Work with internal Design teams and Methodology teams to successfully Lead/implement Physical Designs of multiple blocks of Complex ASICs . The position requires good understanding of the physical design flow from RTL to GDS & several chips tapeout experience. The successful candidate should possess in-depth knowledge & experience in physical synthesis, design planning, floor planning, place & route, static timing analysis and design closure & physical verification Responsibilities Will be responsible for all aspects of Physical Design for Fullchip/Blocks covering Floorplanning, Placement, Budgeting, Clock Tree planning & analysis, Scan re-ordering, Clock tree synthesis, Placement optimizations, Routing, Timing and SI analysis/closure, ECO tasks (both timing and functional), EM/IR, DRC, LVS, ERC analysis & fixes, Low Power solution development & implementation. Prefer sound knowledge in EDA tools such as DC, ICC2, Cadence Innovus, STAR-RC, PT-SI, Verplex, Quartz, Calibre, internal tools & flow, etc. Work closely with the methodology team to solve the implementation challenges & provide inputs to improve the Physical design flow. Experienced in design automation. Understanding of Timing constraints, SI prevention, Power reduction. Must have prior experience with Synopsys/Cadence/Mentor place and route tools. Must have completed design in 16nm and or 7nm.. Proficient in Unix/TCL/Perl. Good communication and presentation skills. Requires good interpersonal skills and problem-solving ability. Minimum Qualifications 4+ years experience in ASIC physical design Experience with block implementation, extraction, timing and or full-chip designs Strong communication skills Strong hands-on TCL/Perl development skills Preferred Qualifications Experience as a full-chip floorplanning, routing, or timing lead for a large silicon project Track record of taping out complex chips on advanced process nodes About Juniper Networks Juniper Networks challenges the inherent complexity that comes with networking and security in the multicloud era. We do this with products, solutions and services that transform the way people connect, work and live. We simplify the process of transitioning to a secure and automated multicloud environment to enable secure, AI-driven networks that connect the world. Additional information can be found at Juniper Networks (www.juniper.net) or connect with Juniper on Twitter, LinkedIn and Facebook. WHERE WILL YOU DO YOUR BEST WORK? Wherever you are in the world, whether it's downtown Sunnyvale or London, Westford or Bengaluru, Juniper is a place that was founded on disruptive thinking - where colleague innovation is not only valued, but expected. We believe that the great task of delivering a new network for the next decade is delivered through the creativity and commitment of our people. The Juniper Way is the commitment to all our colleagues that the culture and company inspire their best work-their life's work. At Juniper we believe this is more than a job - it's an opportunity to help change the world. At Juniper Networks, we are committed to elevating talent by creating a trust-based environment where we can all thrive together. If you think you have what it takes, but do not necessarily check every single box, please consider applying. We’d love to speak with you. Additional Information for United States jobs: ELIGIBILITY TO WORK AND E-VERIFY In compliance with federal law, all persons hired will be required to verify identity and eligibility to work in the United States and to complete the required employment eligibility verification form upon hire. Juniper Networks participates in the E-Verify program. E-Verify is an Internet-based system operated by the Department of Homeland Security (DHS) in partnership with the Social Security Administration (SSA) that allows participating employers to electronically verify the employment eligibility of new hires and the validity of their Social Security Numbers. Information for applicants about E-Verify / E-Verify Información en español: This Company Participates in E-Verify / Este Empleador Participa en E-Verify Immigrant and Employee Rights Section (IER) - The Right to Work / El Derecho a Trabajar E-Verify® is a registered trademark of the U.S. Department of Homeland Security. Juniper is an Equal Opportunity workplace. We do not discriminate in employment decisions on the basis of race, color, religion, gender (including pregnancy), national origin, political affiliation, sexual orientation, gender identity or expression, marital status, disability, genetic information, age, veteran status, or any other applicable legally protected characteristic. All employment decisions are made on the basis of individual qualifications, merit, and business need. Show more Show less

Lead design of analog/mixed-signal ICs (ADC/DAC, PLL, LDO/DCDC, IO Drivers). Oversee verification, layout compliance, cross-functional collaboration, and product support. Utilize EDA tools for design, simulation, and debugging. Required Candidate profile Experienced analog/mixed-signal IC designer (8+ yrs), adept in variation-aware design, verification, debugging, and product support. Strong in cross-functional collaboration. Masters in VLSI or ECE

Drafting, review and negotiation of contracts Confidential, Joint Venture, Consortium, Service provider agreements. Sound knowledge in FIDIC Contracts, NHAI Contracts, NPCIL Contracts, CPWD Contracts. Experience in operations with good understanding of infrastructure works Identification and monitoring of Project risks and opportunities in a timely manner. Drafting of Contractual communications/project correspondences. Ensuring timely notices for various issues arising at site pertaining to Extension of time, variations, settlement of disputes. Handling of Delay and Disruption claims. Must have knowledge in Indian Arbitration Act 1996(Amended on 2015 & 2019) and Indian Contract Act 1872. Experience in Dispute resolution processes such as DAB, DRC, Conciliation, Mediation, Amicable settlement (Preferred) Knowledge in project scheduling, EoT / Delay analysis and programming software like primavera and MSP. Show more Show less

About Nxtwave: NxtWave is founded by Rahul Attuluri (Ex-Amazon, IIIT Hyderabad), Sashank Reddy (IIT Bombay), and Anupam Pedarla (IIT Kharagpur). In February 2023, NxtWave raised ₹275 crore led by Greater Pacific Capital, a leading international private equity firm . The startup is also backed by Orios Ventures, Better Capital, and marquee angels, including founders of some of India’s unicorns. NxtWave is one of India’s fastest-growing Ed-Tech startups , revolutionizing the 21st-century job market by transforming youth into highly skilled tech professionals irrespective of their educational background with its CCBP 4.0 programs. As an official partner for NSDC under the Ministry of Skill Development & Entrepreneurship, Government of India, and recognized by NASSCOM, Ministry of Commerce and Industry, Government of India, and Startup India, NxtWave has earned a reputation for excellence. The startup has received accolades such as ‘The Greatest Brand in Education’ in a research-based listing by URS Media, a leading international media house. NxtWave has also been honored with the "Startup Spotlight Award 2023" by T-Hub on its 8th Foundation Day. Recently, NxtWave’s founders, Anupam Pedarla and Sashank Gujjula, were honored in the 2024 Forbes India 30 Under 30 for their exceptional contribution to transforming the tech education landscape in India. The edtech brand eliminates the entry barrier to learning tech skills by offering vernacular content and interactive learning. Learning in one’s mother tongue helps achieve higher comprehension, deeper attention, longer retention, and greater outcomes. Presently, NxtWave has paid subscribers from 647+ districts across India. In just 2.5 years, CCBP 4.0 learners have been hired by 1700+ companies , including Google, Amazon, Nvidia, Goldman Sachs, Oracle, Deloitte, and more. Know more about NxtWave: https://www.ccbp.in Our LinkedIn page: Link Next wave of opportunities with 1700+ companies - Link 33M funding news - Link Youtube Channel - Link Impact Stores on LinkedIn - Link Read more about us in the news - Economic Times | CNBC | Yourstory | VCCircle About the Role We are seeking a meticulous and technically proficient Sound Engineer to join our in-house video production team. In this role, you will take ownership of the audio production pipeline , from on-set recording to post-production mixing and mastering. You’ll play a crucial role in ensuring our video content —whether educational masterclasses, brand films, testimonials, or explainers—delivers pristine, immersive audio that complements our high-caliber visuals. Your expertise will directly impact the viewer experience , ensuring clarity , consistency , and professional broadcast quality sound across all our productions. Key Responsibilities On-Set Audio Recording Plan and execute location sound recording , ensuring clean dialogue capture , minimal ambient noise, and optimal mic placement for various video formats. Operate and manage professional audio recording equipment , including shotgun microphones , lavalier systems , audio recorders , boom poles , and wireless audio kits . Conduct sound checks , monitor levels in real time, and troubleshoot issues on set to ensure uncompromised audio capture . Implement best practices for soundproofing and ambient control , particularly in studio environments. Audio Post-Production Perform audio editing , clean-up , mixing , and mastering for all types of video content. Reduce noise, hums, and unwanted frequencies using industry-standard software like Adobe Audition , Pro Tools , or DaVinci Resolve Fairlight . Synchronize audio with video footage, ensuring lip sync accuracy and audio continuity . Design and incorporate sound effects , room tone , and background scores , collaborating with composers or sourcing royalty-free libraries when required. Sound Quality & Consistency Maintain a consistent audio signature and brand sound identity across all videos. Ensure voice clarity , balanced tone , and correct loudness levels , optimized for various platforms (YouTube, LMS, social media, etc.). Implement Loudness Standards (LUFS), Dynamic Range Control (DRC) , and EQ balancing appropriate for the content type. Equipment Management & Workflow Optimization Manage, maintain, and upgrade audio equipment inventory , including microphones, audio interfaces, mixers, and monitoring systems. Recommend and integrate new technologies or tools that enhance recording quality or workflow efficiency. Document and refine audio production workflows , ensuring smooth handoffs between recording, post, and delivery teams. What We’re Looking For Experience : 2+ years as a Sound Engineer , Location Sound Recordist , or Audio Post-Production Specialist in professional video production environments. Technical Proficiency : Mastery of audio recording tools (Zoom F series, Sound Devices MixPre, Rode, Sennheiser, Shure, or equivalent professional microphones). Strong command over DAWs (Adobe Audition, Pro Tools, Fairlight, Logic Pro). Familiarity with audio plugins for noise reduction , de-reverb , EQ , compression , and limiting . Attention to Detail : Acute sensitivity to audio imperfections , pacing , volume consistency , and tonal balance . Problem Solving : Ability to troubleshoot live sound issues swiftly and effectively, ensuring minimal downtime on shoot days. Collaborative Spirit : Comfort working in close coordination with cinematographers , directors , and editors , with a proactive approach to creative problem-solving . Nice to Have Experience with 5.1 Surround and immersive audio formats . Knowledge of Foley recording , ADR , and voiceover session direction . Familiarity with audio for animation and motion graphics projects. Understanding of broadcast standards and delivery formats for OTT, YouTube, and LMS platforms. Why Join Us? At NxtWave , we believe sound is not just an accessory—it’s a driving force behind emotional impact and engagement. As a Sound Engineer , you will have the opportunity to shape the sonic identity of our content, ensuring that every word, every note, and every silence contributes to an exceptional learning and brand experience . You’ll be part of a creative, future-forward team , working on projects that redefine education through cinematic storytelling . Show more Show less

Company: Qualcomm India Private Limited Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: Qualcomm GPU team is actively seeking candidates for several physical design engineering positions. Graphics HW team in Bangalore is part of a worldwide team responsible for developing and delivering GPU solutions which are setting the benchmark in mobile computing industry.Team is involved in Architecture, Design, Verification, implementation and Productization of GPU IP COREs that go into Qualcomm Snapdragon SOC Products used in Smartphone, Compute, Automotive, AR/VR and other low power devices. Qualcomm has strong portfolio of GPU COREs and engineers get an opportunity to work with world class engineering team that leads industry through innovation and disciplined execution. As a Graphics physical design engineer, you will innovate, develop, and implement GPU cores using state-of-the-art tools and technologies. You will be part of a team responsible for the complete Physical Design Flow and deliveries of complex, high-speed, low power GPU COREs. Tasks also involve the development and enablement of low power implementation methods, customized P&R to achieve area reduction and performance goals. Additional responsibilities in this role involves good understanding of functional, test (DFT) mode constraints for place and route, floorplanning, power planning, IR drop analysis, placement, multi-mode & multi-corner (MMMC) clock tree synthesis, routing, timing optimization and closure, RC extraction, signal integrity, cross talk noise and delay analysis, debugging timing violations for multi-mode and multi-corner designs, implementing timing fixes, rolling in functional ECOs, debugging and fixing violations and formal verification. The individual also should have deep knowledge on scripting and software languages including PERL/TCL, Linux/Unix shell and C. This individual will design, verify and delivers complex Physical Design solutions from netlist and timing constraints to the final product. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. Minimum Qualifications Bachelor's/Master’s degree in Electrical/Electronic Engineering from reputed institution 12+ years of experience in Physical Design/Implementation Minimum Requirements: Physical Implementation activities for high performance GPU Core, which includes Floor-planning, Place and Route, CTS, Formal verification, Physical Verification (DRC/LVS), PDN, Timing Closure and power optimization. Should have good exposure to PD implementation of PPA critical Cores and making right PPA trade-off decisions. Strong expertise in timing convergence of high frequency data-path intensive Cores and advanced STA concepts Well versed with the Block level PnR convergence with Synopsys ICC2/ Cadence Innovus and timing convergence in PTSI/Tempus in latest technology nodes Good understanding of clocking architecture. Should be able work in close collaboration with design, DFT and PNR teams and resolve issues wrt constraints validation, verification, STA, Physical design, etc. Well versed with Tcl/Perl Scripting Experience of working as part of a larger team and working towards project milestones and deadlines; Handle technical deliverables with a small team of engineers. Strong problem-solving skills and good communication skills. Applicants : Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries). Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law. To all Staffing and Recruiting Agencies : Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications. If you would like more information about this role, please contact Qualcomm Careers. 3071473 Show more Show less

SAP DRC Consultant (Document & Reporting Compliance) India – Remote Long-term Contract Job Description: Looking for a senior SAP Consultant (10+ years) with strong experience in DRC, statutory reporting, and S/4HANA for a global ECC to S/4 project. Key Skills: SAP SD or FICO, S/4HANA DRC, VAT/GST, European tax reporting Debugging, testing, and documentation Strong financial process understanding Please email resumes to hr@sapdeck.com Show more Show less

Job TitleAI/ML Engineer - Time Series Forecasting & Clustering LocationBangalore Experience2+ Years Job TypeFull-Time Mandatory Skills: AI/ML Engineer with Time Series Forecasting & Clustering experience Responsibilities in Brief: Time Series Forecasting Build models to predict trends from time series data. Clustering Develop algorithms to group and analyze data segments. Data Insights Analyze data to enhance model performance. Team Collaboration Work with teams to integrate models into products. Stay Updated Apply the latest AI techniques to improve solutions. Qualifications: Education Bachelor s/Master s in Computer Science or related field. Experience Hands-on experience with time series forecasting and clustering. Skills Proficient in Python, R, and relevant ML tools Perks & Benefits: Health and WellnessHealthcare policy covering your family and parents. FoodEnjoy scrumptious buffet lunch at the office every day. Professional DevelopmentLearn and propel your career. We provide workshops, funded online courses and other learning opportunities based on individual needs. Rewards and RecognitionsRecognition and rewards programs in place to celebrate your achievements and contributions. Why join Relanto Health & FamilyComprehensive benefits for you and your loved ones, ensuring well-being. Growth MindsetContinuous learning opportunities to stay ahead in your field. Dynamic & InclusiveVibrant culture fostering collaboration, creativity, and belonging. Career LadderInternal promotions and clear path for advancement. Recognition & RewardsCelebrate your achievements and contributions. Work-Life HarmonyFlexible arrangements to balance your commitments. To find out more about us, head over to our Website and LinkedIn

Company Description ComTek Solutions is a global technology services and outsourcing provider specializing in SAP implementations, managed services, and staff augmentation. With headquarters in Virginia, USA, and offshore delivery centers in Hyderabad and Vizag, INDIA, ComTek focuses on IT industry best practices and a simple approach to enterprise applications. The company offers core services in SAP S/4 HANA Conversions & Migrations, SAP Ariba, SAP GRC, SAP SuccessFactors, and SAP Cloud Support. Role Description This is a contract remote role for a SAP DRC Consultant at ComTek Solutions. The SAP DRC Consultant will be responsible for implementing, configuring, and supporting SAP DRC solutions to ensure compliance with local and international regulations related to e-invoicing, e-reporting, and statutory compliance. Primary responsibilities include: - Implement and configure SAP Data Retention and Compliance (DRC) solutions. Analyze data retention policies and ensure compliance with regulations. Develop and maintain documentation for data management processes. Collaborate with stakeholders to identify data retention requirements. Monitor and report on data compliance status and issues. Provide training and support to users on DRC tools and practices. Show more Show less

Company Qualcomm India Private Limited Job Area Engineering Group, Engineering Group > Hardware Engineering General Summary As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. IPPD: Physical design engineer Physical Implementation activities for high performance Cores for 16/14/7/5nm or lower technologies, which includes all or some of the below. Floor-planning, Place and Route, CTS, Formal verification, Physical Verification (DRC/LVS), Low Power verification, PDN, Timing Closure and / or power optimization Exposure to PD implementation of PPA critical cores. Exposure to timing convergence of high frequency data-path intensive Cores and advanced STA concepts. Able to handle Block level PnR convergence with Synopsys ICC2/ Cadence Innovus and timing convergence in PTSI/Tempus in latest technology nodes. Understanding of clocking architecture. Tcl/Python/Perl Scripting aware for small automation Strong problem-solving skills , good communication skills and good team player Collaborate with design, DFT and PNR teams and support issue resolutions wrt constraints validation, verification, STA, Physical design, etc. Applicants : Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries). Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law. To all Staffing and Recruiting Agencies : Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications. If you would like more information about this role, please contact Qualcomm Careers. 3073060 Show more Show less

Selected Intern's Day-to-day Responsibilities Include Circuit Schematic Creation: Assist in creating and editing circuit schematics using Electronic Design Automation (EDA) tools like Altium Designer, Eagle, or KiCad. Simulation: Perform circuit simulations using software Spice to check the behavior of the design before physical implementation. Breadboarding and Prototyping Building Prototypes: Assemble circuits on breadboards Testing and Troubleshooting: Conduct basic testing of the circuits, troubleshooting and identifying issues such as incorrect connections or faulty components. Measurement and Data Collection: Use tools like multimeters, oscilloscopes, and signal generators to measure voltage, current, frequency, and other parameters. PCB Layout: Assist in designing the layout for printed circuit boards (PCBs) using CAD software. Component Placement: Help in placing components on the PCB based on the schematic, ensuring the design follows best practices for routing, grounding, and signal integrity. Design Rule Checks: Run design rule checks (DRC) to ensure that the PCB design follows manufacturing standards. Documenting Designs: Record detailed notes and diagrams for the design process, including schematics, component values, and testing results. Reporting: Prepare and present progress reports on ongoing design projects to the team or mentor. About Company: Toyart is a STEAM kit manufacturer company. Our business focuses on producing educational kits designed to teach science, technology, engineering, arts, and mathematics (STEAM) concepts in an engaging, hands-on manner. These kits are targeted toward students of various age groups, from elementary to high school, and sometimes even adults, to help them gain practical skills and foster creativity. The primary goal of the company is to make learning fun and interactive while enhancing critical thinking, problem-solving, and teamwork abilities. Show more Show less

Project Role : Application Lead Project Role Description : Lead the effort to design, build and configure applications, acting as the primary point of contact. Must have skills : SAP Integration with Vertex O Series/Sabrix, SAP FI CO Finance, Tax regimes, including Sales & Use, VAT, GST, HST, Solid Experience in Corporate Taxation Good to have skills : No Function Specialty Minimum 5 year(s) of experience is required Educational Qualification : 15 years full time education Summary :As an Application Lead, you will lead the effort to design, build, and configure applications, acting as the primary point of contact. Your day will involve overseeing project progress, coordinating with teams, and ensuring successful application development. We are seeking a Senior Tax Technology Specialist to join our team. This role requires a seasoned professional with extensive experience in tax engines, indirect tax management (particularly Vertex O Series), and a strong foundation in SAP systems. The ideal candidate will manage complex tax project across the Sales and Use Tax, helping to streamline tax processes and maintain global compliance. Roles & Responsibilities: Implementing new requirements and maintaining the Vertex O Series system, focusing on the global indirect tax solution Configuring and managing Vertex tax rules, rates, and jurisdictions to ensure precise and compliant tax calculations for all transactions - Supporting mapping updates to tax matrices and conducting end-to-end testing to ensure no regression impacts across jurisdictions (US and OUS) Collaborating with IT and finance teams to align tax systems with business needs and compliance requirements Developing and maintaining detailed documentation, including SOPs and user guides, for Vertex-related processes Professional & Technical Skills: Must To Have Skills:Proficiency in SAP Integration with Vertex O Series/Sabrix, SAP FI CO Finance Strong understanding of SAP FI CO Finance Must Have Skills:Experience in SAP Integration with Vertex O Series/Sabrix along with SAP FI CO Finance Extensive experience with Vertex O Series and familiarity with SAP tax-related solutions Strong knowledge of tax regimes, including Sales & Use, VAT, GST, HST, and Corporate Tax Excellent analytical skills and keen attention to detail Good To Have Skills:Experience in BRIM/FICA modules and DRC is beneficial but not mandatory Good To Have Skills:Experience in SAP ABAP development, SAP PI/PO, and SAP SD/MM modules. Additional Information: The candidate should have a minimum of 8+ years of experience in SAP Integration with Vertex O Series/Sabrix. This position is based at our Bengaluru office. A 15 years full-time education is required. Qualifications 15 years full time education