725 Drc Jobs - Page 4

Drishti Offset is looking for Graphic Design Professional to join our dynamic team and embark on a rewarding career journey A Graphic Designer is a professional who creates visual concepts and designs for various mediums to communicate messages or ideas effectively They combine artistic skills, creativity, and technical proficiency to develop visually appealing designs Here are some key responsibilities of a Graphic Designer:Concept Development: Graphic Designers collaborate with clients or creative teams to understand their requirements and develop design concepts They brainstorm ideas, research visual trends, and create design mockups or sketches that align with the project objectives Visual Design: Graphic Designers use various design elements, such as color, typography, images, and layout, to create visually engaging designs They design graphics for print materials, digital platforms, websites, social media, logos, packaging, and other marketing or promotional materials Branding and Identity: Graphic Designers play a crucial role in developing and maintaining brand identity They create brand guidelines, including logo design, color palettes, typography, and visual style guides, to ensure consistency across all brand materials Layout and Composition: Graphic Designers determine the arrangement and placement of design elements within a layout They consider factors such as balance, hierarchy, proportion, and visual flow to create visually appealing and user-friendly designs Digital Design: In the digital space, Graphic Designers create designs optimized for various digital platforms, such as websites, mobile applications, social media platforms, and email campaigns They ensure the designs are responsive, user-friendly, and visually appealing across different devices and screen sizes Image Editing and Manipulation: Graphic Designers are skilled in image editing and manipulation using software such as Adobe Photoshop They retouch and enhance images, adjust colors, remove backgrounds, and resize images to fit design requirements

SENIOR PHYSICAL DESIGN ENGINEER SmartSoC is looking for smart and enterprising Physical Designer Engineers to come to join us and get an opportunity to do some cutting-edge work and also work in a great environment where work is Always Fun and Exciting. This role will involve Physical design at the block and chip level of complex designs in the latest technologies. Desired Skills and Experience- 3 – 10 years relevant experience Excellent hands-on P&R skills with expert knowledge in ICC/Innovus Expert knowledge in all aspects of PD from Synthesis to GDSII, Strong background of Floor planning, Placement, CTS, Routing, P&R, Extraction, IR Drop Analysis, Timing and Signal Integrity closure Experience at taping out multiple chips, strong experience at top level at latest technology nodes Job Category VLSI (Silicon engineering) Job Location IndiaBangalore IndiaChennai IndiaHyderabad IndiaNoida Malaysia Singapore

SR. DFT ENGINEER SmartSoC is looking for expert DFT engineers for the development, support, maintenance, Implementation, and Testing of complex components of an ASIC/SOC/FPGA/Board. Desired Skills and Experience- 3 – 10year’s experience in DFT Good experience/concept on all aspects of DFT i.e. SCAN/ATPG, MBIST, Boundary Scan. DFT logic integration and verification. Experience in debugging low coverage and DRC fixes Gate Level ATPG simulation with and without timing. Pattern generation, verification, and delivery to ATE team. Post silicon debug and support on failing patterns. Good experience with tools from Mentor/Synopsis/Cadence. LBIST experience is plus. DFT mode STA and timing closure support. Familiarity with Verilog and RTL simulation Job Category VLSI (Silicon engineering) Job Location FinlandOulu IndiaBangalore IndiaChennai IndiaHyderabad IndiaNoida Malaysia S. KoreaSeoul Singapore SwedenStockholm USADelaware USATexas

Analog Layout Engineer Experience3 to 5 Years QualificationB.E / B. Tech / M.E / M. Tech ESSENTIAL DUTIES AND RESPONSIBILITIES: Candidate should have a strong knowledge on devices and process/fabrication technology. Should have work experience in 7nm, 10nm, 14nm, 16nm etc Good understating of Deep Submicron issues and layout techniques. Expertise on matching, parasitic reduction, ESD, DFM etc. Proficiency in use of below EDA tools for full custom layout and post-layout verification DRC/LVS/DFM etc. Cadence Virtuoso Layout editor (L/XL/GXL) Verification toolsAssura/PVS/Calibre/ Hercules Preferred Skills: Scripting Knowledge of perl/shell/skill are highly preferred Job Category VLSI (Silicon engineering) Job Location FinlandOulu IndiaBangalore IndiaChennai IndiaHyderabad IndiaNoida Malaysia S. KoreaSeoul Singapore SwedenStockholm USADelaware USATexas

Lead Analog Layout Engineer Experience8 to 10 Years QualificationB.E / B. Tech / M.E / M. Tech Essential Duties & Responsibilities: Candidate should have a strong knowledge on devices and process/fabrication technology. Should have work experience in 7nm, 10nm, 14nm, 16nm etc Good understating of Deep Submicron issues and layout techniques. Expertise on matching, parasitic reduction, ESD, DFM etc. Proficiency in use of below EDA tools for full custom layout and post-layout verification DRC/LVS/DFM etc. Cadence Virtuoso Layout editor (L/XL/GXL) Verification toolsAssura/PVS/Calibre/ Hercules Ability to handle a team Preferred Skills: Scripting Knowledge of perl/shell/skill are highly preferred Job Category VLSI (Silicon engineering) Job Location FinlandOulu IndiaBangalore IndiaChennai IndiaHyderabad IndiaNoida Malaysia S. KoreaSeoul Singapore SwedenStockholm USADelaware USATexas

Physical Design Engineer Experience 4-10 yrs Job Overview: Strong background of ASIC Physical DesignFloor planning, P&R, Extraction, IR Drop Analysis, Static Timing and Signal Integrity.. Hands-on experience on technology nodes like 5nm,7nm, 14nm, 10nm. Good knowledge of EDA tools from Synopsys, Cadence and Mentor Hands-on experience in floor planning, placement optimizations, CTS and routing. Hands-on experience in cadence or Synopsys tool (Encounter, ICC, PT/PTSI, TEMPUS, DC, RC, VOLTAS) Job Category VLSI (Silicon engineering) Job Location IndiaBangalore IndiaChennai IndiaHyderabad IndiaNoida

Title: Principal Engineer, QSP About GlobalFoundries GlobalFoundries is a leading full-service semiconductor foundry providing a unique combination of design, development, and fabrication services to some of the world’s most inspired technology companies. With a global manufacturing footprint spanning three continents, GlobalFoundries makes possible the technologies and systems that transform industries and give customers the power to shape their markets. For more information, visit www.gf.com. Introduction This position is for a QSP Engineer who will act as a point-of-contact for all QSP related topics. The successful candidate needs to be self-driven with a strong solution-oriented approach. Your Job Qualification and signoff IP libraries from FIP, NVM Develop and maintain QSP flows and tool automation. Drive and own initiatives towards timely resolution of issues related to IP Ownership of release and point of contact with QMS team for the IP related issues Work with cross-geo, cross-vertical teams to understand requirements and communicate resolution Work with vendors like Cadence, Synopsys, siemens for resolutions related to tools Required Qualifications : Design Engineer with knowledge of EDA tools and flows – Crosscheck, Schematic, Layout (Virtuoso),FE views, BE views. Requires a Bachelor of Engineering (B.E.) or equivalent degree in a related field from an accredited university. B.E./B.Tech + minimum of 7-8 years of relevant experience M.E./M.Tech +minimum 4-6 years of relevant experience 3+ years of experience in IPQA teams Language Fluency – Fluent in English Language – written & verbal. Must have proficient knowledge of and experience with Unix environment Must have hands-on experience on crosscheck tool Should be fluent with Cadence EDA tools for schematic and physical layout, design rule checking (DRC), layout versus schematic checking (LVS, schematic and layout extraction, methodology checking) Must have good technical verbal and written communication skills and ability to work with cross functional teams is necessary Be able to collaborate with PMO and technical design leads on multiple concurrent projects. Should have excellent problem-solving skills, written & oral communication, teaming & interpersonal skills Perform all activities in a safe and responsible manner and support all Environmental, Health, Safety & Security requirements, and programs Familiarity with standard engineering practices like Version Control systems, Configuration Management and Regression process Preferred Qualifications: Knowledge of scripting languages like Python/Perl Experience with PowerBI, Excel, Powerpoint and other office productivity tools GlobalFoundries is an equal opportunity employer, cultivating a diverse and inclusive workforce. We believe having a multicultural workplace enhances productivity, efficiency and innovation whilst our employees feel truly respected, valued and heard. As an affirmative employer, all qualified applicants are considered for employment regardless of age, ethnicity, marital status, citizenship, race, religion, political affiliation, gender, sexual orientation and medical and/or physical abilities. All offers of employment with GlobalFoundries are conditioned upon the successful completion of background checks, medical screenings as applicable and subject to the respective local laws and regulations. Information about our benefits you can find here: https://gf.com/about-us/careers/opportunities-asia

Apply at: https://docs.google.com/forms/d/e/1FAIpQLScRVbgJC66kbdy8qjpqci9JSZqmWeWza0xU_AGSxZLA-BsYqA/viewform?usp=sharing&ouid=118008152822125500826 Role Responsibilities: Design multi-layer PCBs (4-8 layers) with high-speed digital interfaces and mixed-signal circuits Create schematic designs and PCB layouts for industrial IoT devices and sensors Perform signal integrity analysis, power integrity analysis, and EMI/EMC optimization Collaborate with hardware engineers on component placement and routing strategies Conduct design rule checks (DRC) and design for manufacturability (DFM) reviews Support prototype bring-up and debug PCB-related issues Maintain component libraries and design documentation Work with manufacturing partners for PCB fabrication and assembly Required Qualifications: 2-4 years of PCB design experience in industrial or consumer electronics Expert proficiency in Altium Designer, KiCad, or similar PCB design tools Knowledge of high-speed digital design principles and signal integrity concepts Experience with power supply design, analog circuits, and mixed-signal layouts Understanding of PCB manufacturing processes and design constraints Familiarity with component sourcing and supply chain considerations Bachelor's degree in Electrical Engineering, Electronics, or related field Preferred Qualifications: Experience with RF circuit design and antenna integration Knowledge of EMI/EMC design principles and testing Familiarity with industrial communication protocols (CAN, RS485, Ethernet) Experience with flex-rigid PCB design Understanding of thermal management in PCB design What We Offer: Competitive compensation package Work on cutting-edge industrial IoT and loss prevention technology Collaborate with experienced hardware and firmware teams Professional development and skill enhancement opportunities Exposure to diverse PCB design challenges across multiple industries Position Details: Location: Noida (In-office) Experience: 2-4 years Joining: Immediate Growth opportunities in hardware design and leadership roles Job Type: Full-time Pay: Up to ₹1,200,000.00 per year Work Location: In person

Hi Folks, Experience : 5+ Yrs Location: Noida Minimum 5 years of experience in Physical Verification * Hands on debugging skills in different physical verification checks like LVS,DRC,ERC,PERC, Antenna, ESD and DFM using Calibre, ICV and Pegasus PV tools. * Knowledge of basic device physics and PV fixing using various PnR tools like Innovus/ICC2 is required. * Working experience in cutting edge technologies such as 5nm, 7nm and 16ff process nodes is desire

Location: Hybrid Job Type: Full-Time Posted Date: 6/30/2025 About The Role Job Overview: We are seeking a Senior Physical Design Engineer with strong expertise in Netlist-to-GDSII implementation and experience working on advanced submicron technology nodes. The role demands in-depth knowledge of industry-standard EDA tools and a solid grasp of timing closure and physical verification processes. Key Responsibilities:  Drive full Netlist-to-GDSII flow: floorplanning, placement, clock tree synthesis (CTS), routing, and sign-off.  Perform Static Timing Analysis (STA) and ensure timing closure across all design corners.  Execute power integrity and physical verification checks (LVS, DRC).  Collaborate closely with cross-functional teams (RTL, STA, packaging, and DFT).  Handle complex designs on 28nm and below technology nodes. Must-Have Skills  Strong hands-on experience with: o Synopsys/Cadence tools: Innovus, ICC2, Primetime, PT-PX, Calibre o Physical Design Methodologies: Floorplanning, Placement, CTS, Routing, STA  Proficiency in: o Timing constraints and closure o Tcl/Tk/Perl scripting o Submicron nodes (28nm and below) Good to Have  Familiarity with Fusion Compiler  Broader understanding of signal and power integrity  Experience in workflow automation and tool scripting If you are interested in this role, please mail your resume to hemanth@neualto.com or spoorthy@neualto.com.

Hi Everyone, If your interested, please share your resume to ayeesha.a.akhtar@accenture.com Must have skills : SAP Document and Reporting Compliance Experience – 7.5 Years to 12.0 Years Educational Qualification : 15 years of Education Technical Expertise: 1. Minimum 1 E2E implementation projects exp in S/4HANA Accounting and good Finance functional expertise with 7-9 years of functional experience. 2. Should have understanding of E2E Finance business processes, Business process analysis and study Gap Identification, Business Blueprint, Process Mapping, Configuration, Functional and Technical Specifications Document, Test Case Document, Training Presentation, Conf Guide and User Manual 3. Good understanding of Document & Reporting Compliance(DRC) and hands on experience in E2E implementation of DRC Statutory Reports /E-Invoicing. 4. Exposure to Localization or Country Specific Solutions-E-Invoicing/Taxation and well versed with taxation scenarios 5. Experience in DRC Report extensibility is an added advantage. 6. Testing the system and its extensions or modifications 7. Experience and knowledge in Taxes on Sales/Purchases; Withholding taxation, Month end process is must. 8. Knowledge on Integration with other 3rd party taxation tools / engines will be an advantage. 9. SAP S/4 HANA certified will be an added advantage. Key Responsibilities: 1. Deep business process functional expertise. Developing E2E business process, understanding the country specific statutory requirement, flow documentation based on discussion with business and requirement analysis. 2. Good team player and be able to lead a team to deliver activities efficiently and effectively. 3. Able to handle cross functional team’s communication / co-ordination. 4. Assist the Leads to solution prospective responses to Proposals in SAP DRC. Professional Attributes: 1. Good Finance business process understanding, Analytical and Problem-solving skills 2. Team Leading and good co-ordination skill with cross functional team in Onsite/Offshore delivery model with client facing experience. 3. Good Soft communication and presentation skills If your interested, please share your resume to ayeesha.a.akhtar@accenture.com Thanks.

Key Responsibilities: Design and develop standard cells for advanced CMOS technology nodes (e.g., 7nm, 5nm, 3nm). Optimize cells for PPA metrics in coordination with layout and circuit teams. Perform circuit-level simulations (e.g., SPICE) to ensure functionality and robustness. Drive layout implementation with an understanding of design rules, parasitics, and manufacturability. Run and debug various verification flows including DRC, LVS, ERC, and EM/IR checks. Perform characterization and validation of standard cells using industry-standard tools (e.g., Liberate, SiliconSmart, etc.). Interface with physical design, RTL, EDA, and process technology teams to ensure seamless integration. Contribute to automation scripts to improve cell development workflows (Python, TCL, Perl, etc.). Document design methodologies and maintain library QA and release processes. Required Skills & Experience: B.E./B.Tech or M.E./M.Tech in Electrical Engineering, Electronics, or a related discipline. 3 to 10 years of hands-on experience in standard cell circuit design and validation. Strong understanding of CMOS fundamentals and transistor-level design. Experience with industry EDA tools from Synopsys, Cadence, or Siemens. Knowledge of characterization methodologies and tools. Familiarity with technology file setup and design rule constraints. Proficiency in scripting (Python, TCL, Shell, etc.) for design automation.

Key Responsibilities: Define and implement DFT architecture for SoCs and IPs. Develop and integrate scan chains, ATPG, MBIST, LBIST, and boundary scan (JTAG). Work with RTL designers to insert DFT logic and resolve DRC violations. Generate and validate test patterns using tools such as TetraMAX , FastScan , DFT Advisor , etc. Analyze and improve fault coverage and test time reduction. Support silicon bring-up and post-silicon validation of test features. Debug and resolve DFT-related issues during synthesis, simulation, and verification. Collaborate with physical design and verification teams to ensure DFT compliance throughout the flow. Required Skills: 3–10 years of hands-on experience in DFT implementation. Strong knowledge of scan insertion, ATPG, MBIST, LBIST, and boundary scan. Experience with DFT tools: Synopsys DFT Compiler , TetraMAX , Mentor Tessent , FastScan , DFTMAX , etc. Proficient in scripting (TCL, Perl, Python, Shell) for automation. Familiar with RTL coding (Verilog/SystemVerilog) and synthesis flow. Good understanding of timing constraints, STA, and low-power design considerations in DFT. Experience in handling gate-level simulations and testbench development.

Key Responsibilities: Drive block-level and/or full-chip physical design from RTL to GDSII. Floorplanning, placement, clock tree synthesis (CTS), and routing. Work on static timing analysis (STA) and timing closure. Run and debug physical verification (LVS/DRC/ERC) and power integrity checks (IR Drop/EM). Collaborate with RTL, DFT, synthesis, verification, and packaging teams. Ownership of PPA (Power, Performance, Area) targets and meeting timing goals. Participate in multiple tape-outs and manage block-level signoff closure. Automate and optimize flows using Tcl, Perl, Python, or shell scripting. Keep up-to-date with the latest EDA tools and technology trends. Required Skills & Experience: B.E./B.Tech or M.E./M.Tech in Electronics, Electrical, or related field. 4–10 years of experience in physical design with successful tape-outs. Strong expertise in Synopsys/Cadence tools (ICC2, Fusion Compiler, Innovus, PrimeTime, etc.). Deep understanding of digital design concepts, timing, and power trade-offs. Hands-on experience in advanced technology nodes (16nm and below preferred). Experience with scripting languages (Tcl, Python, Perl, Shell). Familiarity with ECO flows, DFT insertion, and low-power design techniques (UPF/CPF). Knowledge of signal and power integrity issues (IR/EM) is a plus.

Overview: WHAT YOU DO AT AMD CHANGES EVERYTHING We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences – the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world’s most important challenges. We strive for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives. AMD together we advance_ Responsibilities: MTS SILICON DESIGN ENGINEER (AECG ASIC TFM Lead) THE ROLE: As a Silicon Design Engineer in the AMD AECG ASIC TFM (Tools Flows Methodology) team, you will work with design experts to come up with the best implementation methodologies/flows and work on development and support of the BE flows. THE PERSON: Engineer with good attitude who seeks new challenges and has good analytical and communication skills. Candidate needs to have the ability and desire to learn quickly and should be a good team player. KEY RESPONSIBILITIES: Define and drive key Beckend/Physical Design methodologies. Partner with AMD CAD Teams, Design team, physical design teams to ensure seamless end to end design flows. Work with existing development teams to define roadmaps for existing flows and assist in difficult technical debug. Work closely with design teams to gather requirements and develop strategies to tackle key technical problems. Work on Floor-plan, Physical Implementation of Power-plan, Synthesis, Placement, CTS, Timing Closure, Routing, Extraction, Physical Verification (DRC & LVS), Crosstalk Analysis, EM/IR Handling different PNR tools - Synopsys ICC2, ICC, Design Compiler, PrimeTime, StarRC, Mentor Graphics Calibre, Apache Redhawk PREFERRED EXPERIENCE: 8+ years of professional experience in physical design, preferably with high performance designs. Experience in automated synthesis and timing driven place and route of RTL blocks for high speed datapath and control logic applications. Experience in automated design flows for clock tree synthesis, clock and power gating techniques, scan stitching, design optimization for improved timing/power/area, and design cycle time reduction. Experience in floorplanning, establishing design methodology, IP integration, checks for logic equivalence, physical/timing/electrical quality, and final signoff for large IP delivery Strong experience with tools for logic synthesis, place and route, timing analysis, and design checks for physical and electrical quality, familiarity with tools for schematics, layout, and circuit/logic simulation Versatility with scripts to automate design flow. Strong communication skills, ability to multi-task across projects, and work with geographically spread out teams Excellent physical design and timing background. Strong analytical/problem solving skills and pronounced attention to details. ACADEMIC CREDENTIALS: Bachelors or Masters degree in computer engineering/Electrical Engineering #LI-SR4 Qualifications: Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. As a Non-Volatile Engineering (NVE) Product Engineer working in the Mask Design & Tapeout Solutions team at Micron Technology, Inc., you are part of a team committed to quality, efficient NAND Memory Design through Custom Layout Design and Tapeout Management. Layout & Mask Designer In our team, we support New Design Development and own the Design Revisions through the Product Lifecycle. As an expert Mask Design Engineer, you will apply DFM, Process Input and Fab Feedback while engaging in multi-functional teams. You will be committed to driving yield improvements, building new processes and tools and mitigating reliability fails through innovative Layout Design techniques. As an owner of the Design Library, you will build, verify and manage all Design Revisions. You will also mentor and train new Engineers and assist partner teams with Design Debug. Tapeout Solutions Our team also owns and supports the Tapeout Process of all Production Reticles for NAND Memory Designs. As such, you will craft and maintain Design Edit Documentation, contribute to Design Reviews and own Reticle Compatibility definitions for Fabs. In this role, you will work with various Engineering and Manufacturing groups to prioritize projects and coordinate resources to ensure critical schedules are met. Responsibilities Include Layout Mask Design Design, Implement and Drive Layout edits needed for development, yield improvement, quality and process enablement. Run (DFM) Flows and collaborate with Design & Technology Development and to craft and implement solutions. Design Library Management & Tapeout Build, Validate and Handle New Design Libraries and Final archives. Accountable for Final EDA checks (LVS, DRC, LVL) Generate Final Data and manage post-processing tapeout flows and Validate final mask data Lead Tapeout order paperwork and Coordinate with Partner Teams to ensure alignment of needs, expectations, priorities and resources to hit schedules. Who We Are We strive for a team culture where you are empowered to develop your skills and have a meaningful impact! We believe in enabling opportunity for you to explore interests that contribute to the team and your career. We prioritize having fun and care about and support each other! Who You Are You believe in driving continuous improvement. You are an Engineer who is passionate about learning new things as well as creating and innovating. You are tenacious and motivated by new challenges. You enjoy mentoring and training others. Your Skills: 8+ Years Experience in Layout Design / Design Library Management & Tapeout Solutions Self-motivated and driven with a Growth Mindset Excellent problem solving and analytical skills Strong multitasking, organizational and project management skills Knowledge of Semiconductor Processing including Photolithography Strong understanding of Semiconductor Physics and VLSI techniques Strong Communication skills in written and spoken English Exposure to EDA Tools About Micron Technology, Inc. We are an industry leader in innovative memory and storage solutions transforming how the world uses information to enrich life for all . With a relentless focus on our customers, technology leadership, and manufacturing and operational excellence, Micron delivers a rich portfolio of high-performance DRAM, NAND, and NOR memory and storage products through our Micron® and Crucial® brands. Every day, the innovations that our people create fuel the data economy, enabling advances in artificial intelligence and 5G applications that unleash opportunities — from the data center to the intelligent edge and across the client and mobile user experience. To learn more, please visit micron.com/careers All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, veteran or disability status. To request assistance with the application process and/or for reasonable accommodations, please contact hrsupport_india@micron.com Micron Prohibits the use of child labor and complies with all applicable laws, rules, regulations, and other international and industry labor standards. Micron does not charge candidates any recruitment fees or unlawfully collect any other payment from candidates as consideration for their employment with Micron.

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. For more than 45 years, Micron Technology, Inc. has redefined innovation with the world’s most advanced memory and semiconductor technologies. We’re an international team of visionaries and scientists, developing groundbreaking technologies that are transforming how the world uses information to enrich life. We are looking for Layout Design engineer at our Micron Technology’s HBM Team in Hyderabad, India. As a Layout Design engineer, you will be working for intensive applications such as artificial intelligence and high performance computing solution, High Bandwidth Memory. As a Layout Design Engineer you will be collaborating with peer teams crossing Micron global footprint, in a multiple projects-based environment. Role and Responsibilities Responsible for Design and development of critical analog, mixed-signal, custom digital block and full chip level integration support. Highly motivated with passion, detail oriented, systematic and methodical approach in IC layout design Perform layout verification like LVS/DRC/Antenna, quality check and documentation. Responsible for on-time delivery of block-level layouts with acceptable quality. Demonstrate leadership Skill in planning, area/time estimation, scheduling, delegation and execution to meet project schedule/milestones in multiple project environment. Guide junior team-members in their execution of Sub block-level layouts & review their work Contribute to effective project-management. Effectively communicating with Global engineering teams to assure the success of layout project. Qualification/Requirements 8 to 15 years' experience in analog/custom layout design in advanced CMOS process, in various technology nodes (Planar, FinFET ) Expertise in Cadence VLE/VXL and Mentor Graphic Calibre DRC/LVS is a must. Should have hands on experience in creating layout of critical blocks such as Temperature sensor, PLL, ADC, DAC, LDO, Bandgap, Ref Generators, Charge Pump, Current Mirrors, Comparator, Differential Amplifier etc., Good understanding of Analog Layout fundamentals (e.g., Matching, Electro-migration, Latch-up, coupling, crosstalk, IR-drop, active and passive parasitic devices etc.) Understanding layout effects on the circuit such as speed, capacitance, power and area etc., Ability to understand design constraints and implement high-quality layouts. Ability to understand design hierarchy and different architectures for Memory designs. Excellent command and problem-solving skills in physical verification of custom layout. Multiple Tape out support experience will be an added advantage. Experience in managing multiple layout projects, ensuring quality checks are taken care at all stages of layout development. Excellent verbal and written communication skills. Education BE or MTech in Electronic/VLSI Engineering All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, veteran or disability status. About Micron Technology, Inc. We are an industry leader in innovative memory and storage solutions transforming how the world uses information to enrich life for all . With a relentless focus on our customers, technology leadership, and manufacturing and operational excellence, Micron delivers a rich portfolio of high-performance DRAM, NAND, and NOR memory and storage products through our Micron® and Crucial® brands. Every day, the innovations that our people create fuel the data economy, enabling advances in artificial intelligence and 5G applications that unleash opportunities — from the data center to the intelligent edge and across the client and mobile user experience. To learn more, please visit micron.com/careers All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, veteran or disability status. To request assistance with the application process and/or for reasonable accommodations, please contact hrsupport_india@micron.com Micron Prohibits the use of child labor and complies with all applicable laws, rules, regulations, and other international and industry labor standards. Micron does not charge candidates any recruitment fees or unlawfully collect any other payment from candidates as consideration for their employment with Micron.

The Sr. Staff Physical Design Engineer position at Lattice Semiconductor in Pune, India offers a dynamic opportunity to join the HW design team focused on IP design and full chip integration. As part of a worldwide community of engineers and specialists, you will have the chance to contribute, learn, innovate, and grow within this fast-paced and ambitious organization. Key responsibilities for this role include implementing and leading the RTL to GDSII flow for complex designs, working on various aspects of physical design such as place & route, CTS, routing, floorplanning, powerplanning, timing, and physical signoff. The ideal candidate will have experience in physical design signoff checks, drive efficiency and quality in physical design flow and methodology, collaborate with internal and external teams, and possess scripting knowledge to enhance design efficiency. Additionally, the successful candidate will play a vital role in FPGA design efforts, drive physical design closure of key ASIC blocks & full chip, maintain design quality through quality checks and signoff, develop strong relationships with global teams, mentor colleagues, and may require occasional travel. Requirements for this role include a BS/MS/PhD in Electronics Engineering, Electrical Engineering, Computer Science or equivalent, along with 12+ years of experience in driving physical design activities for ASIC blocks and full chips. Candidates must have multiple tapeout experience and proficiency in industry-standard physical design tools. The ideal candidate should be an independent problem solver, capable of collaborating with diverse groups across different sites and time zones. Lattice Semiconductor values its employees as the cornerstone of its success and offers a comprehensive compensation and benefits program to attract and retain top talent in the industry. As an international developer of low-cost, low-power programmable design solutions, Lattice is committed to customer success and a culture of innovation and achievement. If you thrive in a results-oriented environment, seek individual success within a team-first organization, and are ready to contribute to a collaborative and innovative atmosphere, Lattice Semiconductor may be the perfect fit for you. Feel the energy at Lattice.,

As an experienced Analog/Custom Layout Designer, you will be responsible for designing and developing critical analog, mixed-signal, and custom digital layouts at both block and chip levels. Your expertise in using Cadence VLE/VXL and Mentor Graphics Calibre for layout and verification will be crucial in ensuring high-quality layout verification, including performing LVS/DRC/Antenna checks. You will be expected to deliver block-level layouts on time with optimal quality while also addressing complex physical verification challenges in custom layout design. Working in multiple project environments, you will play a key role in ensuring high-quality execution within project deadlines and guiding junior engineers by reviewing sub-block level layouts and critical elements. Collaboration is essential in this role, as you will need to work effectively with local engineering teams to contribute to project success. Your ability to contribute to project management and ensure a smooth workflow will be highly valued. To excel in this position, you should have at least 5 years of experience in analog/custom layout design in advanced CMOS processes, with expertise in TSMC 3nm, 5nm, and 7nm nodes. Strong problem-solving skills in physical verification (LVS/DRC/Antenna checks), the ability to mentor junior engineers, review complex layouts, and excellent communication and project management skills are essential. This is a full-time position with a day shift schedule, and the work location is in person.,

Role Responsibilities Exhibit expertise in the configuration of SAP S/4 HANA, specifically focusing on FI modules such as General Ledger Accounting and Taxation. Handle invoice-related processes including electronic documentation creation and subsequent reconciliation procedures. Manage data preparation and submission for electronic invoicing implementation. Administer reconciliation and statutory reporting of electronic invoicing processes, ensuring compliance with periodic reporting requirements. Perform corrections and manage compliance-related statutory reporting tasks efficiently. Demonstrate knowledge and practical application of sound workflow management techniques. Qualifications & Experience Hold a Bachelor’s or Master’s degree in relevant fields such as Software Engineering, Information Technology, Business Administration (MBA), Computer Applications (MCA), Chartered Accountancy (CA), or Cost and Works Accountancy (CWA). Possess hands-on expertise in SAP S/4 Hana project execution, with a focus on Document and Reporting Compliance (DRC). Successfully carried out at least one end-to-end implementation project within SAP DRC framework. Demonstrated proficiency in SAP taxation processes (direct and indirect), with an added advantage in tax system integrations. Execute SAP E-invoicing and handle country-specific reporting requirements effectively. Showcase advanced knowledge of document and reporting compliance management practices. Exhibit familiarity with Scrum methodologies and leverage practical experience to benefit project workflows. Skills: electronic invoicing,statutory reporting,workflow management,data replication,document and reporting compliance (drc),sap drc,sap s/4 hana,tax system integrations,general ledger accounting,scrum methodologies,reconciliation,sap,taxation

Role Responsibilities Exhibit expertise in the configuration of SAP S/4 HANA, specifically focusing on FI modules such as General Ledger Accounting and Taxation. Handle invoice-related processes including electronic documentation creation and subsequent reconciliation procedures. Manage data preparation and submission for electronic invoicing implementation. Administer reconciliation and statutory reporting of electronic invoicing processes, ensuring compliance with periodic reporting requirements. Perform corrections and manage compliance-related statutory reporting tasks efficiently. Demonstrate knowledge and practical application of sound workflow management techniques. Qualifications & Experience Hold a Bachelor’s or Master’s degree in relevant fields such as Software Engineering, Information Technology, Business Administration (MBA), Computer Applications (MCA), Chartered Accountancy (CA), or Cost and Works Accountancy (CWA). Possess hands-on expertise in SAP S/4 Hana project execution, with a focus on Document and Reporting Compliance (DRC). Successfully carried out at least one end-to-end implementation project within SAP DRC framework. Demonstrated proficiency in SAP taxation processes (direct and indirect), with an added advantage in tax system integrations. Execute SAP E-invoicing and handle country-specific reporting requirements effectively. Showcase advanced knowledge of document and reporting compliance management practices. Exhibit familiarity with Scrum methodologies and leverage practical experience to benefit project workflows. Skills: electronic invoicing,statutory reporting,workflow management,data replication,document and reporting compliance (drc),sap drc,sap s/4 hana,tax system integrations,general ledger accounting,scrum methodologies,reconciliation,sap,taxation

Role Responsibilities Exhibit expertise in the configuration of SAP S/4 HANA, specifically focusing on FI modules such as General Ledger Accounting and Taxation. Handle invoice-related processes including electronic documentation creation and subsequent reconciliation procedures. Manage data preparation and submission for electronic invoicing implementation. Administer reconciliation and statutory reporting of electronic invoicing processes, ensuring compliance with periodic reporting requirements. Perform corrections and manage compliance-related statutory reporting tasks efficiently. Demonstrate knowledge and practical application of sound workflow management techniques. Qualifications & Experience Hold a Bachelor’s or Master’s degree in relevant fields such as Software Engineering, Information Technology, Business Administration (MBA), Computer Applications (MCA), Chartered Accountancy (CA), or Cost and Works Accountancy (CWA). Possess hands-on expertise in SAP S/4 Hana project execution, with a focus on Document and Reporting Compliance (DRC). Successfully carried out at least one end-to-end implementation project within SAP DRC framework. Demonstrated proficiency in SAP taxation processes (direct and indirect), with an added advantage in tax system integrations. Execute SAP E-invoicing and handle country-specific reporting requirements effectively. Showcase advanced knowledge of document and reporting compliance management practices. Exhibit familiarity with Scrum methodologies and leverage practical experience to benefit project workflows. Skills: electronic invoicing,statutory reporting,workflow management,data replication,document and reporting compliance (drc),sap drc,sap s/4 hana,tax system integrations,general ledger accounting,scrum methodologies,reconciliation,sap,taxation

Role Responsibilities Exhibit expertise in the configuration of SAP S/4 HANA, specifically focusing on FI modules such as General Ledger Accounting and Taxation. Handle invoice-related processes including electronic documentation creation and subsequent reconciliation procedures. Manage data preparation and submission for electronic invoicing implementation. Administer reconciliation and statutory reporting of electronic invoicing processes, ensuring compliance with periodic reporting requirements. Perform corrections and manage compliance-related statutory reporting tasks efficiently. Demonstrate knowledge and practical application of sound workflow management techniques. Qualifications & Experience Hold a Bachelor’s or Master’s degree in relevant fields such as Software Engineering, Information Technology, Business Administration (MBA), Computer Applications (MCA), Chartered Accountancy (CA), or Cost and Works Accountancy (CWA). Possess hands-on expertise in SAP S/4 Hana project execution, with a focus on Document and Reporting Compliance (DRC). Successfully carried out at least one end-to-end implementation project within SAP DRC framework. Demonstrated proficiency in SAP taxation processes (direct and indirect), with an added advantage in tax system integrations. Execute SAP E-invoicing and handle country-specific reporting requirements effectively. Showcase advanced knowledge of document and reporting compliance management practices. Exhibit familiarity with Scrum methodologies and leverage practical experience to benefit project workflows. Skills: electronic invoicing,statutory reporting,workflow management,data replication,document and reporting compliance (drc),sap drc,sap s/4 hana,tax system integrations,general ledger accounting,scrum methodologies,reconciliation,sap,taxation

Role Responsibilities Exhibit expertise in the configuration of SAP S/4 HANA, specifically focusing on FI modules such as General Ledger Accounting and Taxation. Handle invoice-related processes including electronic documentation creation and subsequent reconciliation procedures. Manage data preparation and submission for electronic invoicing implementation. Administer reconciliation and statutory reporting of electronic invoicing processes, ensuring compliance with periodic reporting requirements. Perform corrections and manage compliance-related statutory reporting tasks efficiently. Demonstrate knowledge and practical application of sound workflow management techniques. Qualifications & Experience Hold a Bachelor’s or Master’s degree in relevant fields such as Software Engineering, Information Technology, Business Administration (MBA), Computer Applications (MCA), Chartered Accountancy (CA), or Cost and Works Accountancy (CWA). Possess hands-on expertise in SAP S/4 Hana project execution, with a focus on Document and Reporting Compliance (DRC). Successfully carried out at least one end-to-end implementation project within SAP DRC framework. Demonstrated proficiency in SAP taxation processes (direct and indirect), with an added advantage in tax system integrations. Execute SAP E-invoicing and handle country-specific reporting requirements effectively. Showcase advanced knowledge of document and reporting compliance management practices. Exhibit familiarity with Scrum methodologies and leverage practical experience to benefit project workflows. Skills: electronic invoicing,statutory reporting,workflow management,data replication,document and reporting compliance (drc),sap drc,sap s/4 hana,tax system integrations,general ledger accounting,scrum methodologies,reconciliation,sap,taxation

Role Responsibilities Exhibit expertise in the configuration of SAP S/4 HANA, specifically focusing on FI modules such as General Ledger Accounting and Taxation. Handle invoice-related processes including electronic documentation creation and subsequent reconciliation procedures. Manage data preparation and submission for electronic invoicing implementation. Administer reconciliation and statutory reporting of electronic invoicing processes, ensuring compliance with periodic reporting requirements. Perform corrections and manage compliance-related statutory reporting tasks efficiently. Demonstrate knowledge and practical application of sound workflow management techniques. Qualifications & Experience Hold a Bachelor’s or Master’s degree in relevant fields such as Software Engineering, Information Technology, Business Administration (MBA), Computer Applications (MCA), Chartered Accountancy (CA), or Cost and Works Accountancy (CWA). Possess hands-on expertise in SAP S/4 Hana project execution, with a focus on Document and Reporting Compliance (DRC). Successfully carried out at least one end-to-end implementation project within SAP DRC framework. Demonstrated proficiency in SAP taxation processes (direct and indirect), with an added advantage in tax system integrations. Execute SAP E-invoicing and handle country-specific reporting requirements effectively. Showcase advanced knowledge of document and reporting compliance management practices. Exhibit familiarity with Scrum methodologies and leverage practical experience to benefit project workflows. Skills: electronic invoicing,statutory reporting,workflow management,data replication,document and reporting compliance (drc),sap drc,sap s/4 hana,tax system integrations,general ledger accounting,scrum methodologies,reconciliation,sap,taxation