1750 Drc Jobs - Page 3

About The Role Project Role : Software Development Engineer Project Role Description : Analyze, design, code and test multiple components of application code across one or more clients. Perform maintenance, enhancements and/or development work. Must have skills : Static Timing Analysis (STA) Good to have skills : NA Minimum 12 year(s) of experience is required Educational Qualification : 15 years full time education Summary : Full Chip level Constraints development, validation, and timing closure Deep understanding of Finfet low technology node 7nm and below Expertise on IO budgeting, MMMC timing eco generation and convergence Expertise in Clock Tree analysis for deep submicron Hands-on expe...

Company Description Sandisk understands how people and businesses consume data and we relentlessly innovate to deliver solutions that enable today’s needs and tomorrow’s next big ideas. With a rich history of groundbreaking innovations in Flash and advanced memory technologies, our solutions have become the beating heart of the digital world we’re living in and that we have the power to shape. Sandisk meets people and businesses at the intersection of their aspirations and the moment, enabling them to keep moving and pushing possibility forward. We do this through the balance of our powerhouse manufacturing capabilities and our industry-leading portfolio of products that are recognized globa...

Required skills: He/She should be able to do top-level floor planning, PG Planning, partitioning,placement, scan-chain-reordering, clock tree synthesis, timing optimization, SI aware routing, timing analysis/closure and ECO tasks (timing and functional ECOs), SI closure, design rule checks (DRC), and Logical vs. Schematic (LVS) checks, Antenna checks. He/She should have worked on 65nm or lower node designs with adv low power techniques such as Voltage Islands, Power Gating and substrate-bias. Provide technical guidance, mentoring to physical design engrs. Interface with front-end ASIC teams to resolve issues. Low Power Design - Voltage Islands, Power Gating, Substrate-bias techniques. Timing...

The Opportunity We are looking for a detail-oriented and innovative Lithography Mask Designer with strong programming skills to support our semiconductor development processes. In this role, you will be responsible for the creation, optimization, and automation of lithography mask layouts, ensuring precision and efficiency in advanced manufacturing environments. How You’ll Make An Impact You will design and generate lithography masks for semiconductor devices using industry-standard tools (e.g. Cadence, KLayout, Calibre), big plus would be knowledge of DW2000. You will collaborate with process engineers and product designers to translate device requirements into mask layouts. You will develo...

Advance Hardware Engineer 7 + years Be an active member of electronics design team assisting project leader in requirements management, electronics circuit design, analysis, implementation & testing of aerospace electronics products / printed circuit cards. Electronics Component selection, analog & digital circuit design & schematic entry Circuit analysis for tolerance, power, thermal & worst-case analysis etc. Layout guidelines & interface with layout engineer for implementation. Board bring up & testing Environmental testing Process, quality & program compliance Support technical decision on design and implementation during product HW development Participate and sometimes lead critical hig...

by Khan Global Studies (KGS) in Competitive Exams EdTech UPSC 40 (views) Noida Full Time Job role insights Date posted October 30, 2025 Hiring location Noida Career level fresher or Experienced Qualification Bachelor Degree Gender Any Gender Show more Hide less Description Key Responsibilities: Eligibility Criteria: Khan Global Studies is hiring for a Content Writer (CSAT). Join KGS (Khan Global Studies) and be part of a dynamic team dedicated to creating high-quality UPSC content! Key Responsibilities Develop top-notch CSAT content covering reasoning, comprehension, numeracy, and decision-making. Create exam-oriented practice sets with accurate and detailed solutions aligned with UPS Prelim...

We are looking for a Digital/Memory Mask Design Engineer – someone who is excited to join a growing group of diverse individuals responsible for handling challenging high-speed digital memory circuit designs. NVIDIA has continuously reinvented itself. Our invention of the GPU sparked the growth of the PC gaming market, redefined modern computer graphics, and revolutionized parallel computing. Today, research in artificial intelligence is booming worldwide, which calls for highly scalable and massively parallel computation horsepower that NVIDIA GPUs excel. NVIDIA is a “learning machine” that constantly evolves by adapting to new opportunities that are hard to solve, that only we can address,...

We are looking for a Digital/Memory Mask Design Engineer – someone who is excited to join a growing group of diverse individuals responsible for handling challenging high-speed digital memory circuit designs. NVIDIA has continuously reinvented itself. Our invention of the GPU sparked the growth of the PC gaming market, redefined modern computer graphics, and revolutionized parallel computing. Today, research in artificial intelligence is booming worldwide, which calls for highly scalable and massively parallel computation horsepower that NVIDIA GPUs excel. NVIDIA is a “learning machine” that constantly evolves by adapting to new opportunities that are hard to solve, that only we can address,...

We are looking for a Digital/Memory Mask Design Engineer – someone who is excited to join a growing group of diverse individuals responsible for handling challenging high-speed digital memory circuit designs. NVIDIA has continuously reinvented itself. Our invention of the GPU sparked the growth of the PC gaming market, redefined modern computer graphics, and revolutionized parallel computing. Today, research in artificial intelligence is booming worldwide, which calls for highly scalable and massively parallel computation horsepower that NVIDIA GPUs excel. NVIDIA is a “learning machine” that constantly evolves by adapting to new opportunities that are hard to solve, that only we can address,...

We are looking for a Digital/Memory Mask Design Engineer – someone who is excited to join a growing group of diverse individuals responsible for handling challenging high-speed digital memory circuit designs. NVIDIA has continuously reinvented itself. Our invention of the GPU sparked the growth of the PC gaming market, redefined modern computer graphics, and revolutionized parallel computing. Today, research in artificial intelligence is booming worldwide, which calls for highly scalable and massively parallel computation horsepower that NVIDIA GPUs excel. NVIDIA is a “learning machine” that constantly evolves by adapting to new opportunities that are hard to solve, that only we can address,...

About The Role Role Purpose The purpose of this role is to perform the development of VLSI system by defining the various functionalities, architecture, layout and implementation for a client ? Do 1. Conduct verification of the module/ IP functionality and provide customer support a. Understand the architecture of the module or the IP and create verification environment and the development plan as per Universal Verification Methodology b. Create test bench development and test case coding of the one or multiple module c. Write the codes or check the code as required d. Execute the test cases and debug the test cases if required e. Conduct functional coverage analysis and document the test ca...

Role Purpose The purpose of this role is to perform the development of VLSI system by defining the various functionalities, architecture, layout and implementation for a client Do 1. Conduct verification of the module/ IP functionality and provide customer support a. Understand the architecture of the module or the IP and create verification environment and the development plan as per Universal Verification Methodology b. Create test bench development and test case coding of the one or multiple module c. Write the codes or check the code as required d. Execute the test cases and debug the test cases if required e. Conduct functional coverage analysis and document the test cases including fai...

Skills: VLE, Cadence Software, VLX, Calibre, DRC, LVS,. Layout Designer _ Hyderabad (5 to 8 Years. Description. Role and Responsibilities. Responsible for Design and development of critical analog, mixed-signal, custom digital block and full chip level integration support. Perform layout verification like LVS/DRC/Antenna, quality check and documentation. Responsible for on-time delivery of block-level layouts with acceptable quality. Demonstrate leadership Skill in planning, area/time estimation, scheduling, delegation and execution to meet project schedule/milestones in multiple project environment. Guide junior team-members in their execution of Sub block-level layouts & review their work....

Position Background And Responsibilities Morgan Stanley recruits quantitative research associates for the Risk Analytics Department. The ideal candidate will be actively involved in market risk modeling and statistical analysis of Morgan Stanley's portfolios for the Market Risk Department. The Market Risk Analytics group develops, maintains, and monitors the performance of market risk (VaR, Stressed VaR, IRC and CRM) and stress testing models for Morgan Stanley's portfolio of assets, as required by the regulatory framework and the Firm's risk management needs. Strong problem-solving abilities, solid writing, and oral presentation skills are desired. The candidate should be able to work in fa...

Physical Design Engineer Physical Design Engineer Experience 4-10 yrs Job Overview: Strong background of ASIC Physical DesignFloor planning, P&R, Extraction, IR Drop Analysis, Static Timing and Signal Integrity.. Hands-on experience on technology nodes like 5nm,7nm, 14nm, 10nm. Good knowledge of EDA tools from Synopsys, Cadence and Mentor Hands-on experience in floor planning, placement optimizations, CTS and routing. Hands-on experience in cadence or Synopsys tool (Encounter, ICC, PT/PTSI, TEMPUS, DC, RC, VOLTAS) Job Category VLSI (Silicon engineering) Job Location IndiaBangalore IndiaChennai IndiaHyderabad IndiaNoida

SR. DFT ENGINEER SR. DFT ENGINEER SmartSoC is looking for expert DFT engineers for the development, support, maintenance, Implementation, and Testing of complex components of an ASIC/SOC/FPGA/Board. Desired Skills and Experience- 3 – 10year’s experience in DFT Good experience/concept on all aspects of DFT i.e. SCAN/ATPG, MBIST, Boundary Scan. DFT logic integration and verification. Experience in debugging low coverage and DRC fixes Gate Level ATPG simulation with and without timing. Pattern generation, verification, and delivery to ATE team. Post silicon debug and support on failing patterns. Good experience with tools from Mentor/Synopsis/Cadence. LBIST experience is plus. DFT mode STA and ...

SENIOR PHYSICAL DESIGN ENGINEER SENIOR PHYSICAL DESIGN ENGINEER SmartSoC is looking for smart and enterprising Physical Designer Engineers to come to join us and get an opportunity to do some cutting-edge work and also work in a great environment where work is Always Fun and Exciting. This role will involve Physical design at the block and chip level of complex designs in the latest technologies. Desired Skills and Experience- 3 – 10 years relevant experience Excellent hands-on P&R skills with expert knowledge in ICC/Innovus Expert knowledge in all aspects of PD from Synthesis to GDSII, Strong background of Floor planning, Placement, CTS, Routing, P&R, Extraction, IR Drop Analysis, Timing an...

Lead Analog Layout Engineer Lead Analog Layout Engineer Experience8 to 10 Years QualificationB.E / B. Tech / M.E / M. Tech Essential Duties & Responsibilities: Candidate should have a strong knowledge on devices and process/fabrication technology. Should have work experience in 7nm, 10nm, 14nm, 16nm etc Good understating of Deep Submicron issues and layout techniques. Expertise on matching, parasitic reduction, ESD, DFM etc. Proficiency in use of below EDA tools for full custom layout and post-layout verification DRC/LVS/DFM etc. Cadence Virtuoso Layout editor (L/XL/GXL) Verification toolsAssura/PVS/Calibre/ Hercules Ability to handle a team Preferred Skills: Scripting Knowledge of perl/shel...

Analog Layout Engineer Analog Layout Engineer Experience3 to 5 Years QualificationB.E / B. Tech / M.E / M. Tech ESSENTIAL DUTIES AND RESPONSIBILITIES: Candidate should have a strong knowledge on devices and process/fabrication technology. Should have work experience in 7nm, 10nm, 14nm, 16nm etc Good understating of Deep Submicron issues and layout techniques. Expertise on matching, parasitic reduction, ESD, DFM etc. Proficiency in use of below EDA tools for full custom layout and post-layout verification DRC/LVS/DFM etc. Cadence Virtuoso Layout editor (L/XL/GXL) Verification toolsAssura/PVS/Calibre/ Hercules Preferred Skills: Scripting Knowledge of perl/shell/skill are highly preferred Job C...

Job Description Role Purpose The purpose of this role is to perform the development of VLSI system by defining the various functionalities, architecture, layout and implementation for a client Do 1.Conduct verification of the module/ IP functionality and provide customer support a.Understand the architecture of the module or the IP and create verification environment and the development plan as per Universal Verification Methodology b.Create test bench development and test case coding of the one or multiple module c.Write the codes or check the code as required d.Execute the test cases and debug the test cases if required e.Conduct functional coverage analysis and document the test cases inc...

Job Description Role Purpose The purpose of this role is to perform the development of VLSI system by defining the various functionalities, architecture, layout and implementation for a client Do 1.Conduct verification of the module/ IP functionality and provide customer support a.Understand the architecture of the module or the IP and create verification environment and the development plan as per Universal Verification Methodology b.Create test bench development and test case coding of the one or multiple module c.Write the codes or check the code as required d.Execute the test cases and debug the test cases if required e.Conduct functional coverage analysis and document the test cases inc...

Job Description Role Purpose The purpose of this role is to perform the development of VLSI system by defining the various functionalities, architecture, layout and implementation for a client Do 1.Conduct verification of the module/ IP functionality and provide customer support a.Understand the architecture of the module or the IP and create verification environment and the development plan as per Universal Verification Methodology b.Create test bench development and test case coding of the one or multiple module c.Write the codes or check the code as required d.Execute the test cases and debug the test cases if required e.Conduct functional coverage analysis and document the test cases inc...

Company Name: Atlanta Systems Pvt. Ltd. Website: www.atlantasys.com Head Office: Connaught Place, New Delhi About Us With over 30 years of legacy, Atlanta Systems Pvt. Ltd. is one of India’s leading manufacturers and solution providers in the IoT and electronics industry. We specialize in developing intelligent hardware systems, IoT devices, and smart technology solutions used across diverse sectors — from automotive and logistics to industrial automation and security. Our mission is to engineer innovation through reliable, scalable, and future-ready electronic products that redefine connectivity and performance. Position: PCB & Hardware Design Engineer – Power Electronics Location: Connaugh...

Job Title: Senior Analog Layout Engineer High-Speed Analog Chip (TSMC 5nm) Experience: 8+ Years Location: Remote / India (must support USA/Canada time zone) Travel: Willing to travel to the U.S. for project release (as required) Role Overview We are looking for a Senior Analog Layout Engineer to work on a high-speed analog chip development in advanced TSMC 5nm technology. The candidate will operate as an individual contributor, responsible for delivering complex high-speed analog and mixed-signal layout blocks with minimal supervision. This role demands deep technical expertise in chip-level integration, bump planning, and ESD implementation, along with a good understanding of circuit simula...

Physical Design Engineer Block-Level (PnR) Job Locations : Bangalore/Hyderabad/Noida/Ahmedabad Job Summary We are looking for a highly motivated Physical Design Engineer with a solid background in block-level place and route (PnR) to join our silicon implementation team. The ideal candidate will have at least 6 years of experience in block-level physical design with proven expertise in timing closure, DRC/LVS, and performance optimization. This role will involve working on advanced technology nodes and collaborating closely with RTL, DFT, STA, and power teams to ensure successful design with AMD flows is a significant plus. Required Qualifications 6+ years of hands-on experience in block-lev...