733 Drc Jobs - Page 26

B.Com / M.Com with 3 to 5 years of experience in Accounting in Pharma / Medical Field. Maintain & manage financial accounts, including balance sheets, income statements & cash flow statements. Knowledge of Accounting Software like SAP, Tally, Excel. Required Candidate profile Will oversee financial transactions, manage inventory, & ensure compliance with accounting standards. Company will provide Air Tickets + Visa + Accommodation + Food. Ready to work for min. 3 Years. Perks and benefits Negotiable - Depending Upon Candidate & Experience

Description Invent the future with us. Recognized by Fast Company’s 2023 100 Best Workplaces for Innovators List, Ampere is a semiconductor design company for a new era, leading the future of computing with an innovative approach to CPU design focused on high-performance, energy efficient, sustainable cloud computing. By providing a new level of predictable performance, efficiency, and sustainability Ampere is working with leading cloud suppliers and a growing partner ecosystem to deliver cloud instances, servers and embedded/edge products that can handle the compute demands of today and tomorrow. Join us at Ampere and work alongside a passionate and growing team — we’d love to have you apply. Come invent the future with us. About The Role Our Physical Design Implementation Engineer will work with multi-functional global teams to implement Partition/Block level Synthesis, Floorplan, Place and Route, Timing closure, IR/EM and DRC/LVS closure for our next generation highly complex 5nm/3nm/advanced-node Server class Processor products. PD work at Ampere is interesting, challenging, and will expand your professional breadth. We like to bring out the best in people, teach each other, and produce products that have value in the market. In this role, you will be at the forefront of our groundbreaking AI compute solution. Our products combine high-performance general-purpose CPUs with AI capabilities, offering a compelling combination of efficiency and market reach. This revolutionary product is poised to deliver superior performance while consuming significantly less power. What You’ll Achieve As a member of the PD Team, you will plan and implement a significant portion of the Chip Layout partnering with design and DFT engineering peers. You will create solutions to meet challenging frequency, power, area, clocking and design partition goals. You’ll get to work with custom and tool-driven CTS and physical design integration methodologies. About You B.Tech in Electronics Engineering or Computer Engineering with 3-5 years of semiconductor experience, or M.Tech with 2-4 years of experience. Good knowledge of EDA tools from Synopsys or Cadence or Mentor required. In particular experience with PTSI, Innovus, Calibre, StarRC, and Conformal LEC is essential. Good knowledge of VLSI process and device characteristics, to make optimal trade-off between performance and power. Good understanding of static timing analysis (STA), EM/IR and sign-off flows. Expertise in physical design of high frequency chips with emphasis on successful timing closure. Good understanding of physical design verification. Experience in implementation and design closure with advanced process nodes like 5nm, 3nm etc. Strong Hands-on Experience With Floor planning, place & route, power and clock distribution, pin placement and timing analysis. Timing convergence using high speed design techniques with signal integrity & EM/IR. Good scripting skills (perl, python, tcl). Self-driven individual and an excellent team player experienced in working with remote teams. Must have good communication skills and the ability and desire to work as a team. What We’ll Offer At Ampere we believe in taking care of our employees and providing a competitive total rewards package that includes base pay, bonus (i.e., variable pay tied to internal company goals), long-term incentive, and comprehensive benefits. Benefits Highlights Include Premium medical, dental, vision insurance, parental benefits including creche reimbursement, as well as a retirement plan, so that you can feel secure in your health, financial future and child care during work. Generous paid time off policy so that you can embrace a healthy work-life balance Fully catered lunch in our office along with a variety of healthy snacks, energizing coffee or tea, and refreshing drinks to keep you fueled and focused throughout the day. And there is much more than compensation and benefits. At Ampere, we foster an inclusive culture that empowers our employees to do more and grow more. We are passionate about inventing industry leading cloud-native designs that contribute to a more sustainable future. We are excited to share more about our career opportunities with you through the interview process. Ampere is an inclusive and equal opportunity employer and welcomes applicants from all backgrounds. All qualified applicants will receive consideration for employment without regard to race, color, national origin, citizenship, religion, age, veteran and/or military status, sex, sexual orientation, gender, gender identity, gender expression, physical or mental disability, or any other basis protected by federal, state or local law. Show more Show less

Introduction Physical design team is responsible for designing high performance microprocessor blocks for IBM Power and z mainframe servers. Your role and responsibilities . Responsible for high performance microprocessor blocks RTL to GDSII implementation . Perform block level synthesis, floor-planning, placement and routing. . Close the design to meet timing, power budget and area. . Implement ECOs to address functional bugs and timing violations. . Team player, with good problem solving and communication skills. Required education Bachelors Degree Preferred education Masters Degree Required technical and professional expertise 5-8 years industry experience in physical design methodology. Good knowledge andhands on experience in physical design methodology which include logic synthesis,placement, clock tree synthesis, routing . Should be knowledgeable in physical verification ( LVS,DRC.. etc), Noise analysis, Power analysis and electro migration . Team player with good problem solving skills, communication skills and leadership skills. Preferred technical and professional experience Automation skills in PYTHON, PERL ,SKILL and/or TCL

Company Qualcomm India Private Limited Job Area Engineering Group, Engineering Group > Hardware Engineering General Summary As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. Qualcomm Noida CPU team is hiring for developing high performance and power optimized custom CPU cores. Individuals to Handle hardening complex HMs from RTL to GDS [ Synthesis, PNR, Timing ]. We are excited to add folks with us for the most cutting-edge work. Here, individuals would have the opportunity to work with some of the most talented and passionate engineers in the world to create designs that push the envelope on performance, energy efficiency and scalability. We offer a fun, creative and flexible work environment, with a shared vision to build products to change the world. Desired Experience 5+ years experience in physical verification post BTECH / MTECH. Expertise in DRC, LVS, PERC, ERC, SOFTCHECK, DFM etc. Efficient fixing of DRCs in INNOVUS OR FC. Completely aware about CALIBRE , VIRTUSO Good scripting skills and automation. Applicants : Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries). Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law. To all Staffing and Recruiting Agencies : Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications. If you would like more information about this role, please contact Qualcomm Careers. 3076185 Show more Show less

Position Overview Job Title: Group Strategic Analytics – Quantitative Strategist - Market Risk Strats - Associate Location: Mumbai, India Role Description The Strategic Production and Analytics of Risk function within Group Strategic Analytics is principally responsible for daily analysis and control of various market risk metrics onboarded to bank’s strategic platforms. The role involves analysis of various market risk metrics including VaR / SVaR, Economic Capital, Market Risk CCAR, Capital charges under Standardised Approach, IMA Approach (Default Risk Charge and Risk Theoretical PnL) and Credit Valuation Adjustment (CVA) under FRTB regulations. You will work with Market Risk Managers, FO Quants, Risk Methodology experts to enable accurate risk measurement and help set up processes for BAU implementation. This role also involves performing controls and checks to ensure completeness and accuracy of risk metric. The role requires application of qualitative and quantitative techniques to analyse the data and a deep understanding of Market Risk Regulation. Group Strategic Analytics Analytics and technology are seen as central to all the main units of the bank, including Investment Bank, Corporate Bank and to Risk and Control functions. The Strategic Analytics team combines expertise in quantitative analytics, modelling, pricing and risk management with deep understanding of system architecture and programming. The primary output is a scalable and flexible Front Office pricing and risk management system with consistent interface to both the Middle Office and Back Office. The consistency in analytics and the technology platform ensures that no arbitrage can exist between various parts of the Bank as well as rational allocation of constrained resources, including risk budget, balance sheet, funding, and capital. Our People Our people are outstanding individuals with agile minds, from a diverse range of backgrounds and cultures. They generate fresh ideas and innovative solutions which set us apart from our competitors and add value to our clients. What We’ll Offer You As part of our flexible scheme, here are just some of the benefits that you’ll enjoy Best in class leave policy Gender neutral parental leaves 100% reimbursement under childcare assistance benefit (gender neutral) Sponsorship for Industry relevant certifications and education Employee Assistance Program for you and your family members Comprehensive Hospitalization Insurance for you and your dependents Accident and Term life Insurance Complementary Health screening for 35 yrs. and above Your Key Responsibilities Run all production process and controls to check completeness, accuracy and timeliness for Market risk metrics like VaR/SVaR, Economic Capital, FRTB CVA, FRTB SA and FRTB IMA (DRC and RTPL) numbers. Finalize the market risk metric in scope and explain drivers of moves including support with complex analysis, evaluation and decision making. Identify and remediate exceptions that are raised during metric calculations – both at individual Asset Class level and at DB Group level Provide analytical support to Risk Managers and FO Strats to facilitate risk management / improve risk management models / drive business decisions. Contribute to methodological enhancements, including quantitative impact analysis. Applying experience and subject matter expertise to perform Run-the-bank tasks such as market risk capital charge impact analysis for methodology, continuous improvement of processes and controls. Liaising with Market Risk Managers, FO Quants, Change teams and Methodology to perform deep dives on data challenges in new market risk models/methodology changes/RNIV and implementation of new regulations Prepare for model governance and Regulatory review process Help specify requirements and test functionalities for seamless implementation of new workflow/data/process enhancements - coordinating with Strats, FO and Risk Technology Your Skills And Experience A strong, relevant background and 5 years of experience working in an international Bank or comparable experience Good product knowledge of derivatives and pricing in at least one asset class – Equity, Credit, Rates, FX, Commodities or in Counterparty Credit risk. Market risk, Middle office, Valuations or Product control background with relevant subject matter expertise in one of the three disciplines Understanding of FRTB regulations, or experience in other Market Risk Regulatory areas MFE/MBA in Finance or relevant experience with Engineering, Finance or quantitative/statistics background Knowledge of languages such as R / Python / SQL. Excellent communication skills and attention to detail Strong analytical, problem solving and critical thinking skills with ability to cope well under pressure and tight timelines A track record of working in a CTB (Projects) and RTB (Production) environment simultaneously Certification such as FRM or CFA or CQF is preferred How We’ll Support You Training and development to help you excel in your career Coaching and support from experts in your team A culture of continuous learning to aid progression A range of flexible benefits that you can tailor to suit your needs About Us And Our Teams Please visit our company website for further information: https://www.db.com/company/company.htm We strive for a culture in which we are empowered to excel together every day. This includes acting responsibly, thinking commercially, taking initiative and working collaboratively. Together we share and celebrate the successes of our people. Together we are Deutsche Bank Group. We welcome applications from all people and promote a positive, fair and inclusive work environment. Show more Show less

Alternate Job Titles: ASIC Physical Design Engineer We Are: At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation. You Are: You are a highly motivated and experienced Physical Design Engineer with a passion for implementing and performing signoff verifications of digital blocks using ASIC design flow (Gate2GDSII). You thrive in dynamic environments and have a knack for problem-solving and innovation. Your expertise in digital block implementation, from gate netlist to GDSII, is complemented by your hands-on experience with state-of-the-art ASIC flows. You understand the intricacies of design initialization, power planning, floor planning/macro placement, scan-chain reordering, CTS, route, and chip finishing steps. You have a solid foundation in physical implementation, signoff verifications (DRC, LVS, Antenna), and reliability verifications (EMIR, ESD). Your ownership of writing MCMM and UPF for block designs showcases your leadership and technical prowess. You are adept at providing handoff data to other signoff closure like STA, formality, layout, and reliability verification. With a minimum of 5 years of relevant experience in the physical design domain and a B.E/B.Tech/M.Tech in ECE/EE, you are ready to take on new challenges and contribute to groundbreaking projects. What You’ll Be Doing: Implementing digital blocks using state-of-the-art gate to GDSII ASIC flows. Performing physical implementation of blocks from gate netlist to GDSII. Conducting signoff verifications, including layout verifications (DRC, LVS, Antenna) and reliability verifications (EMIR, ESD). Writing MCMM and UPF for block designs. Providing handoff data for other signoff closure processes like STA, formality, layout, and reliability verification. Collaborating with cross-functional teams to ensure the successful integration and testing of physical designs. The Impact You Will Have: Enhancing the quality and reliability of our digital block implementations. Driving innovation in physical design methodologies and processes. Enabling the successful deployment of high-performance silicon chips. Contributing to the development of cutting-edge technology that powers next-generation applications. Supporting the continuous improvement of our ASIC design flow and tools. Ensuring the seamless integration of physical designs into larger systems and platforms. What You’ll Need: In-depth understanding of the ASIC physical design flow steps from gate netlist. Experience in testchip implementation and testing exposure is a plus. Exposure to Synopsys toolset (such as FC/ICC2, Primetime, Formality, ICV) is highly desirable. Experience with FinFET designs is desirable. Experience in working on IO integration with wire-bond or flip-chip design is a big plus. Who You Are: A problem solver with strong analytical skills. Detail-oriented with a focus on quality and reliability. Effective communicator and collaborator. Innovative thinker with a passion for technology. Self-motivated and able to work independently. The Team You’ll Be A Part Of: Join a dynamic team of experts focused on pushing the boundaries of physical design and implementation. Our team is dedicated to continuous innovation and excellence, working collaboratively to solve complex challenges and deliver cutting-edge solutions. You'll be part of a supportive and inclusive environment where your contributions are valued and your professional growth is nurtured. Rewards and Benefits: We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process. Show more Show less

1. Hands on work on custom layout for analog blocks like High Speed SerDes and General purpose IO designs with Cadence Virtuoso on latest technologies like 5nm and below and also take leadership roles in delivery of IPs 2. Work on Floor planning, power design, signal routing strategy, EMIR awareness andparasitic optimisations 3. Understand and apply analog Layout techniques to ensure the design meets performance with minimum possible area and good yield. 4. Participate in building and enhancing layout flow for faster, higher quality design process. 5. Checking physical verifications like DRC/LVS/ERC/ANT/DFM and other IBM internal checks 6. Collaborate with Circuit Designers to solve challenging problems 7. Writing /PYTHON scripts to automate repetitive tasks 8. Work with Place and Route engineer to integrate custom macros into top level. 9. Able to perform design reviews across global team 10. Work closely with required global teams to ensure the success of the whole product. 11. Leadership in delivery of macros we plan to own from India Job requirements: 1. Experience in doing layouts for analog blocks like SerDes, ADCs, DACs, LDOs, PLLs, BGAP & amplifiers etc. 2. Experience in designing layouts for high-speed circuits is a plus. 3. Layout experience in the following technology nodes3nm, 5nm and 7nm FinFET. 4. Good team worker with multi-discipline, multi-cultural and multi-site environments 5. Strong fundamental knowledge in semiconductor device physics, layout principles, IC reliability and failure mechanisms 6. Good problem-solving skills are essential where problems are analysed upfront, identifying gaps, and providing optimum solutions7. Knowledge in Skill/perl/tcl/Python scripting is a plus. Required education Bachelor's Degree Preferred education Master's Degree Required technical and professional expertise The Analog layout design engineer with experience in next generation Ultra high speed serial IO link (HSS) interface for Cognitive, ML,DL, and data center applications. The engineer needs to have knowledge in the design and development full custom analog layouts for ultra high speed 32G/50G/112G IO link interfaces. Preferred technical and professional experience Experience in 7 and 14 nm analog layout design. Working on Cutting edge technology and HSS domain . Quick learner, deep layout design knowledge, problem solving skills and good communication skills with cross teams across the Geos.

The engineer should be well versed in Verilog/VHDL RTL coding, experienced in using Mentor DfT tools and Cadence tools. The engineer needs to have hands-on experience in scan insertion, JTAG, ATPG DRC and coverage analysis, Simulation debug with timing/SDF. Candidate with LBIST and Mixed Signal Radar IC experience is highly desirable Must be proactive, collaborative and detail-oriented capable of exercising independent judgment The engineer with experience on debug and root cause the problem in simulation failures Self-motivation, flexibility, with strong interpersonal skills. Effective communication skills, oral and written skills.

About the job ​Role: ​PCB CAM Engineer. Company: ​S​epic Technologies Pvt Ltd Location: Bengaluru Experience: ​1-​3 years Education: BE in electrical engineering, Electronics, or a related field (or equivalent experience). JOB OVERVIEW ​S​epic Technologies is seeking an experienced PCB CAM Engineer to join our ​D​esign team. The PCB CAM Engineer will be responsible for converting PCB designs into manufacturing-ready files, ensuring that all design requirements are met to resolve any design or production issues. The ideal candidate will have a strong understanding of PCB manufacturing processes. KEY RESPONSIBILITIES ​• Generate CAM files (Gerber, ODB++, and NC) for manufacturing processes. ​• DFM: Perform DFM checks to ensure the PCB design is optimized for manufacturing and meets production standards. Process Optimization: Continuously analyze and improve CAM​ processes, reducing errors, enhancing efficiency, and improving overall production timelines. Documentation: Create and maintain documentation of all CAM processes, as well as manufacturing guidelines and standards. Quality Control: Ensure that the final manufacturing files are accurate, high-quality, and meet all customer specifications. ​• Software Proficiency: ​Cam350, GC prevue or any equivalent tools. REQUIRED SKILLS ​1-​3 years of hands-on experience in PCB CAM. ​• Ability to read and interpret engineering drawings and PCB Gerber files ​• Knowledge of DRC guidelines and best practices. ​• Strong problem-solving skills and the ability to handle complex ​• Excellent communication skills and the ability to work in a collaborative team environment. Job Type: Full-time Pay: ₹200,000.00 - ₹500,000.00 per year Benefits: Health insurance Schedule: Day shift Fixed shift Monday to Friday Morning shift Weekend availability Ability to commute/relocate: Chandra Lay Out, Bengaluru, Karnataka: Reliably commute or planning to relocate before starting work (Preferred) Experience: PCB CAM: 1 year (Required) Willingness to travel: 50% (Preferred) Work Location: In person Application Deadline: 30/06/2025 Expected Start Date: 01/07/2025

SKS Enterpprises is looking for Manager/ Sr Manager - Placement to join our dynamic team and embark on a rewarding career journey Career Counseling: Provide guidance and career counseling to students or job seekers, helping them identify their skills, interests, and career goals Job Placement: Facilitate job placements by matching candidates with suitable job openings based on their qualifications and preferences Employer Engagement: Build and maintain relationships with employers, businesses, and organizations to understand their hiring needs and requirements Job Postings and Recruitment: Post job vacancies and coordinate recruitment processes, including conducting interviews and coordinating selection procedures Resume and Interview Preparation: Assist candidates in preparing resumes, cover letters, and interview techniques to enhance their chances of securing a job Internship and Training Opportunities: Identify and promote internship and training opportunities for students and job seekers to gain practical experience Networking Events: Organize job fairs, networking events, and industry-specific workshops to connect candidates with potential employers

Responsibilities DFT Engineer Bangalore, India 6+ years experience in DFT In depth knowledge and hands on experience in scan insertion, ATPG, coverage analysis, Transition delay test coverage analysis Analyze design and propose best compression technique Debug and resolve the DRC issues Work with front end team to provide the solutions and make sure DFT DRCs are fixed Generating high quality manufacturing ATPG test patterns for (SAF) stuck-at, transition fault (TDF), Path Delay fault (PDF) models and through the use of on-chip test compression techniques Working experience in Synopsis TetraMax/DFTMax and Cadence Encounter Test is required In depth knowledge and hands on experience in MBIST insertion and Memory test validation Expertise in Mentor tools is plus Bachelors Degree in Electrical, Electronics or Computer Engineering Show more Show less

locationsIndia, Bangalore time typeFull time posted onPosted 18 Days Ago job requisition idJR0271803 Job Details: About The Role : Develops the logic design, register transfer level (RTL) coding, and simulation for graphics IPs (including graphics, compute, display, and media) required to generate cell libraries, functional units, and the GPU IP block for integration in full chip designs. Participates in the definition of architecture and microarchitecture features of the block being designed. Applies various strategies, tools, and methods to write RTL and optimize logic to qualify the design to meet power, performance, area, and timing goals as well as design integrity for physical implementation. Reviews the verification plan and implementation to ensure design features are verified correctly across verification hierarchies, drives unit level verification, and resolves and implements corrective measures for failing RTL tests to ensure correctness of features. Supports SoC customers to ensure high quality integration of the GPU block. Qualifications: Minimum qualifications are required to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates. Minimum Qualifications: B.Tech/M.Tech +6 Years of relevant industry experience. Having achieved multiple tape-outs reaching production with first pass silicon. Ability to drive and improve digital design methodology to achieve high quality first silicon. Hands on experience with FPGA emulation, silicon bring-up, characterization and debug. Have experience working in GPU/CPU domain. Able to work with multi-functional teams within Intel and external vendors across geographical boundaries to resolve architectural and implementation challenges with a focus on schedule. Strong verbal and written communication skills. Good understanding of verilog and system verilog, synthesizable RTL. Knowledgeable in modern design techniques and energy-efficient/low power logic design and power analysis. Requirements listed would be obtained through a combination of industry relevant job experience, internship experiences and or schoolwork/classes/research. Job Type: Experienced Hire Shift: Shift 1 (India) Primary Location: India, Bangalore Additional Locations: Business group: The Client Computing Group (CCG) is responsible for driving business strategy and product development for Intel's PC products and platforms, spanning form factors such as notebooks, desktops, 2 in 1s, all in ones. Working with our partners across the industry, we intend to deliver purposeful computing experiences that unlock people's potential - allowing each person use our products to focus, create and connect in ways that matter most to them. As the largest business unit at Intel, CCG is investing more heavily in the PC, ramping its capabilities even more aggressively, and designing the PC experience even more deliberately, including delivering a predictable cadence of leadership products. As a result, we are able to fuel innovation across Intel, providing an important source of IP and scale, as well as help the company deliver on its purpose of enriching the lives of every person on earth. Posting Statement: All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance. Position of Trust N/A Work Model for this Role This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. *

We are seeking a skilled SoC (System on Chip) Frontend Design Engineer to join our integrated circuit (IC) design team. The ideal candidate will be working on RTL design, digital logic design, synthesis, linting, timing analysis, and verification for FPGA/ASIC projects. This role requires deep knowledge of VHDL/Verilog, verification methodologies, testbench development, and debugging. The candidate will work closely with cross-functional teams to deliver high-quality, efficient SoC designs. You have: Bachelors Degree in Electrical, Computer Engineering, or a related field (Masters preferred).3+ years of experience in RTL design, digital logic design, and synthesis. Proficiency in VHDL/Verilog for RTL design. Strong knowledge of digital logic design, synthesis, and timing analysis. Experience with linting tools and methodologies. Familiarity with verification methodologies (UVM, System Verilog). Experience in testbench development, simulation, and functional coverage. Strong debugging skills to identify and resolve design issues. Proven track record of successful FPGA/ASIC design projects. Required ToolsSynopsys Design Compiler or Cadence Genus, Mentor Graphics QuestaSim, Spyglass VC It would be nice if you also had: Experience with advanced verification methodologies and tools. Familiarity with high-level synthesis (HLS) tools. Knowledge of scripting languages such as Python, Tcl, or Perl for automation. Develop RTL designs using VHDL/Verilog for FPGA/ASIC projects. Perform digital logic design, synthesis, and timing analysis. Conduct linting and static analysis to ensure code quality. Develop and implement verification methodologies (UVM, System Verilog). Create and maintain testbenches for simulation and functional coverage. Perform simulations and debugging to ensure design correctness. Participate in design reviews and provide feedback to improve design quality.

Company Qualcomm India Private Limited Job Area Engineering Group, Engineering Group > Hardware Engineering General Summary As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. Experience : 7 to 10 years Physical design of block level with full understanding of PnR cycle. Good understanding of Physical design fundamentals Good hands-on experience on industry standard pnr tools like ICC2/Innovus Good understanding on signoff tool like Prime time , Redhawk and calibre Should be able to guide junior engineers in resolving technical issues. Tools : ICC/Innovus, PT, StarRC, Redhawk, Calibre DRC/LVS Scripting: TCL, Perl Applicants : Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries). Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law. To all Staffing and Recruiting Agencies : Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications. If you would like more information about this role, please contact Qualcomm Careers. 3072524 Show more Show less

Develops block, macro, or chip level layouts and floorplans according to project requirements, specifications, and design schematics. Applies understanding of design manuals, established processes, layout elements, and basic electronic principles to create accurate designs that meet project needs. Conducts analyses, tests, and verifies designs using different tools and techniques to identify and troubleshoot issues, and stays abreast of new verification methods. Works with multiple internal and external stakeholders to align on projects, provide updates, and resolve issues. Minimum Qualifications: Bachelor's degree in Electrical Engineering, Computer Science, Mathematics, Electronic Engineering, or related field and 2+ years of experience designing custom layouts in relevant domain (e.g., analog, mixed signal, RF, digital design), or related work experience. OR Associate's degree in Computer Science, Mathematics, Electrical Engineering or related field and 4+ years of experience designing custom layouts in relevant domain (e.g., analog, mixed signal, RF, digital design), or related work experience. OR High School diploma or equivalent and 6+ years of experience designing custom layouts in relevant domain (e.g., analog, mixed signal, RF, digital design), or related work experience. 2+ years of experience using layout design and verification tools (e.g., cadence, LVS, rmap). Solid experience of 3 to 6 years in developing high speed IO/ESD/Analog layout design. Expertise in working on FinFet layouts in lower nodes, preference to TSMCN 7nm and below. Expertise in using the best and latest features of Cadence VXL and Calibre DRC/LVS. Basic understanding of IO/ESD designs. Knowledge on Basic SKILL/PERL. Capable of working independently and with team and getting work done with contract work force. The ability to work & communicate effectively with global engineering teams.

Location Karnataka Bengaluru Experience Range 8 - 12 Years Job Description PD: Technical Skills: Should be able to handle Full chip PnR (timing/congestion/CTS issues), understanding of IO ring, package support, multi voltage design Deep understanding of the concepts related to synthesis, place & route, CTS, timing convergence, IR/EM checks and signoff DRC/LVS closure Responsible for independent planning and execution of all aspects of physical design including floor planning, place and route, Clock Tree Synthesis, Clock Distribution, extraction, Timing closure, Power and Signal Integrity Analysis, Physical Verification, DFM Must have participated in all stages of the design (floor planning, placement, CTS, routing, physical verification, IREM) Well versed with the timing closure (STA), timing closure methodologies Good Understanding of DRC, LVS,ERC and PERC rule files for lower tech node layout verification Experience in lower tech node (<7nm) Good automation skills in PERL, TCL and EDA tool-specific scripting Able to take complete ownership for Block/sub-system for complete execution cycle Out of box thinking to meet tighter PPA requirements Qualification: BE/BTECH/MTECH in EE/ECE with proven experience in ASIC Physical Design Detailed knowledge of EDA tools and flows, Fusion compiler based RTL2GDS flow is desired Experience – 11+

Applied Materials is the leader in materials engineering solutions to produce virtually every new chip and advanced display in the world. Our expertise in modifying materials at atomic levels and on an industrial scale enables customers to transform possibilities into reality. Our innovations make possible™ the technology shaping the future. To achieve this, we employ some of the best, brightest, and most talented people in the world who work together as part of a winning team. Key Responsibilities Expertise in PDK enablement and library validation/automation. Hands-on experience with LVS/Parasitic extraction/standard cell characterization flows and methodologies Design/System level experience with DTCO and PPA analysis Hands-on expertise in TCL, Python, make and shell scripting Broad understanding of system design (product architecture, packaging, SRAM, DRAM, etc.) is a plus Strong understanding of the RTL2GDS concepts and methodology and experience with Synopsys/Cadence physical design tools (Fusion Compiler/Innovus) Knowledge of standard cell architecture and design tradeoffs with respect to PPA Proactively identify and act on new trends or developments in future technology nodes Ability to implement solutions and troubleshoot complex problems with limited or no supervision in area of expertise Creative thinking and ability to look ahead and anticipating future technology innovations/issues Ability to collaborate with internal stakeholders, customers and vendors Collaborate/participate in discussions to solve interdisciplinary technical issues in a cross-functional team environment Mandatory - PDK, DRC, LVS, Python, Physical Design Functional Knowledge Demonstrates depth and/or breadth of expertise in own specialized discipline or field Business Expertise Interprets internal/external business challenges and recommends best practices to improve products, processes or services Leadership May lead functional teams or projects with moderate resource requirements, risk, and/or complexity Problem Solving Leads others to solve complex problems; uses sophisticated analytical thought to exercise judgment and identify innovative solutions Impact Impacts the achievement of customer, operational, project or service objectives; work is guided by functional policies Interpersonal Skills Communicates difficult concepts and negotiates with others to adopt a different point of view Qualifications Education: Master's Degree Skills Certifications: Languages: Years of Experience: 7 - 10 Years Work Experience: Additional Information Shift: Day (India) Travel: Yes, 10% of the Time Relocation Eligible: Yes Applied Materials is an Equal Opportunity Employer committed to diversity in the workplace. All qualified applicants will receive consideration for employment without regard to race, color, national origin, citizenship, ancestry, religion, creed, sex, sexual orientation, gender identity, age, disability, veteran or military status, or any other basis prohibited by law. Show more Show less

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. Job Title: Lead Product Validation Engineer Location: Bangalore Cadence is a pivotal leader in electronic design, building upon more than 30 years of computational software expertise. The company applies its underlying Intelligent System Design strategy to deliver software, hardware and IP that turn design concepts into reality. Cadence customers are the world’s most innovative companies, delivering extraordinary electronic products from chips to boards to systems for the most dynamic market applications including consumer, hyperscale computing, 5G communications, automotive, aerospace industrial and health. The Cadence Advantage The opportunity to work on cutting-edge technology in an environment that encourages you to be creative, innovative, and to make an impact. Cadence’s employee-friendly policies focus on the physical and mental well-being of employees, career development, providing opportunities for learning, and celebrating success in recognition of specific needs of the employees. The unique “One Cadence – One Team” culture promotes collaboration within and across teams to ensure customer success Multiple avenues of learning and development available for employees to explore as per their specific requirement and interests You get to work with a diverse team of passionate, dedicated, and talented individuals who go above and beyond for our customers, our communities, and each other—every day. Job Summary As PV engineer, this person will be responsible for product validation [quality engineering] owning validation from test plan creation, test automation to bug tracking, follow-up and closing summary. The ideal candidate is expected to have understanding of semiconductor verification flow. Job Responsibilities Focus on quality of physical validation tool Pegasus by analyzing on existing functionality/regressions for customer deliverables and report failures in bug tracking system. Maintain regression tests with regular test cycles and integrate customer test cases as part of regression suites. Working closely with PE and R&D to develop test plan of new features and methodology for testing coverage improvement. Experience And Technical Skills Required 4+ to 7 years' experience in developing and supporting physical verification activities. Have 3+ years of experience in VLSI back-end domain Be expert in layout and physical verification concepts (DRC/FILL/LVS/PERC) Have solid working experience with UNIX and skilled in shell/perl/tcl/python scripting language Good communication, strong solving skill and working as a team player Strong knowledge of Cadence Virtuoso is a big plus Qualifications BE/BTech/ME/MS/MTech in Electrical/Electronics Behavioral Skills Required Must possess strong written, verbal and presentation skills Ability to establish a close working relationship with both customer peers and management Explore what’s possible to get the job done, including creative use of unconventional solutions Work effectively across functions and geographies Push to raise the bar while always operating with integrity We’re doing work that matters. Help us solve what others can’t. Show more Show less

Job Overview This opening is for a memory layout designer in our PHYSICAL IP – MEMORY group in Noida. We work on innovative memory architectures in pioneering technology nodes to enable the best Arm Systems in all the markets. This position is a rare opportunity for you as a memory layout professional to work with our successful layout and circuits team. You will be working on floor planning, metal planning, efficient layout techniques to extract the best PPA in groundbreaking process technologies. Responsibilities Implementation of quality full-custom layouts of high-performance arrays and memory blocks from supplied schematics from planning stages through final layout verification and review, in accordance with strict guidelines for performance and manufacturability. Interpretation and implementation of all physical design rules in the most advanced manufacturing processes used by Arm. Custom layout and verification of complex memory cells. Physical design verification (DRC/LVS/DFM) resource for all types of circuit and test layouts using calibre verification tools. Electro-migration and IR checks for reliability and integrity. Required Skills and Experience The ideal candidate is expected to have 2+ years relevant layout design experience with a Bachelor/Masters or equivalent education. Ability to understand, plan and organize work using complex schematics of hierarchically structured circuits. Understanding of layout techniques for optimization of power, speed, and area for data path, bitcell arrays, word line drivers, control blocks, and other complex memory circuits. Ability to quickly interpret and repair complicated LVS and DRC problems using innovative verification software. Must have experience with Cadence Virtuoso layout systems. Organized and exhibits attention to detail “Nice To Have” Skills and Experience Understanding of layout techniques for design-for-manufacture in advanced (7nm/5nm/3nm/2nm) processes. Ability to identify possible design tradeoffs with circuit design leads, based upon assumptions, inherent knowledge, and design analysis. Programming experience Tcl, Perl, shell, Skill, Scheme. In Return By joining our team, you will be at the heart of Arm roadmap investments and product, exposing you to the steps that it takes to turn strategic objectives into reality. This position offers numerous opportunities for interaction with various stakeholders and senior leaders. This role provides excellent exposure for professional development! Accommodations at Arm At Arm, we want to build extraordinary teams. If you need an adjustment or an accommodation during the recruitment process, please email accommodations@arm.com . To note, by sending us the requested information, you consent to its use by Arm to arrange for appropriate accommodations. All accommodation or adjustment requests will be treated with confidentiality, and information concerning these requests will only be disclosed as necessary to provide the accommodation. Although this is not an exhaustive list, examples of support include breaks between interviews, having documents read aloud, or office accessibility. Please email us about anything we can do to accommodate you during the recruitment process. Hybrid Working at Arm Arm’s approach to hybrid working is designed to create a working environment that supports both high performance and personal wellbeing. We believe in bringing people together face to face to enable us to work at pace, whilst recognizing the value of flexibility. Within that framework, we empower groups/teams to determine their own hybrid working patterns, depending on the work and the team’s needs. Details of what this means for each role will be shared upon application. In some cases, the flexibility we can offer is limited by local legal, regulatory, tax, or other considerations, and where this is the case, we will collaborate with you to find the best solution. Please talk to us to find out more about what this could look like for you. Equal Opportunities at Arm Arm is an equal opportunity employer, committed to providing an environment of mutual respect where equal opportunities are available to all applicants and colleagues. We are a diverse organization of dedicated and innovative individuals, and don’t discriminate on the basis of race, color, religion, sex, sexual orientation, gender identity, national origin, disability, or status as a protected veteran. Show more Show less

The Opportunity We're looking for the Wavemakers of tomorrow. Alphawave Semi enables tomorrow’s future by accelerating the critical data communication at the heart of our digital world – from seamless video streaming to AI to the metaverse and much more. Our technology powers product innovation in the most data-demanding industries today, including data centers, networking, storage, artificial intelligence, 5G wireless infrastructure, and autonomous vehicles. Customers partner with us for mission-critical data communication, our innovative technologies, and our proven track record. Together, we enable the next generation of digital technology. What You'll Do : Responsible for PDK evaluation, setup, customization, and flows definition Drive and implement specific Custom Design Automation flows such as Schematic entry, Layout design - color aware and DPT/MPT Parasitic Extraction for transistor level flow Device Modeling and Simulation environment in Synopsys' Custom Compiler PrimeSim XA circuit simulators Knowledge and hands-on experience in physical verification – DRC, LVS, and DFM checks Knowledge of Electrical verification like EMIR, ERC, PERC Knowledge of Analog cell characterization Knowledge of Reliability Verification Drive Interfacing between Digital and Analog/Mixed signal methodologies. . Develop Custom flows automation, rule deck customizations, improve productivity and efficiency. Train, Deployment and support of Automation flows to Design teams Debug flow issues and testcases from Design teams for Simulation, LVS, DRC, EMIR, post layout simulation. Assist Tape outs, final chip finishing runs, interface across foundry/customer for rulesets You will be reporting to Manager IP Modelling Team. What You'll Need: Must have a minimum Bachelor's degree in Electronic Engineering or a related program Must have 2 to 5 years of work experience in a CAD Automation engineer role. Experience with different Technology nodes (7nm, 5nm, 4nm, 3nm, etc) Experience with the different foundries (TSMC, SAMSUNG, etc) and design techniques. Good to have: Good knowledge of Analog/Mixed-signal Design and Development in Synopsys/Cadence Design environment. Good knowledge of EDA Tools and Methodologies in Analog/Mixed Signal Design and Development. Experience with standards and formats like Spice, CDL, LEF, DEF, Verilog, SPEF, GDS, OA, LIB, etc. Good knowledge of scripting skills – TCL, Python, C-Shell scripts, PERL, etc. Good knowledge of Data management aspects using Git/ SVN/ICManage / Cliosoft / Perforce / Methodics / etc. Good knowledge of 14nm/10nm/7nm/5nm/4nm/3nm finfet technologies Good knowledge of Deep Submicron Issues/technologies ( Understanding of Job submission and monitoring is a plus Understanding of tool License features and license administration is a plus ''We have a flexible work environment to support and help employees thrive in personal and professional capacities” As part of our commitment to the well-being and satisfaction of our employees, we have designed a comprehensive benefits package that includes: Competitive Compensation Package Restricted Stock Units (RSUs) Provisions to pursue advanced education from Premium Institute, eLearning content providers Medical Insurance and a cohort of Wellness Benefits Educational Assistance Advance Loan Assistance Office lunch & Snacks Facility Equal Employment Opportunity Statement Alphawave Semi is an equal opportunity employer, welcoming all applicants regardless of age, gender, race, disability, or other protected characteristics. We value diversity and provide accommodations during the recruitment process. Show more Show less

Role Description Additional Comments:Physical Design Engineer Experience- 4 to 10 years Engineers is expected to be very good in Basic Fundamentals of C-MOS technology Expected to have a very good understanding of the PD Flow for flat and hierarchal designs Able to handle RTL/Netlist to GDSII independently at block level/SS/SoC and should have done multiple tape outs with low power implementation (Experience on floor planning, Partitioning, integration at Subsystem/Chip will be add advantage) Should have hands-on experience of working on Lower technology nodes like 3nm, 5nm, 7nm, 10nm, 14nm, 16nm, 28nm etc. Hands-on experience in floor planning, placement optimizations, CTS and routing. Hands-on experience in block/top level signoff STA, physical verification (DRC/LVS/ERC/antenna) checks and other reliability checks(IR/EM/Xtalk) Should have expertise on industry standard EDA tools from Synopsys , Cadence and Mentor ( ICC2, Fusion-Compiler, Design Compiler, Primetime, PTSI, IC Validator, Innovus, Genus, Tempus, Encounter, Nanoroute, Calibre, StarRC and Redhawk, voltage storm Exposure in DMSA flow for ECO generation and implementation. Good knowledge of VLSI process and scripting in TCL, perl . Skills Physical design,PNR,PD Flow Show more Show less

About The Job Our Team: Within Digital Risk & Compliance, we are looking for a Digital Risk & Compliance Expert – Controls Assurance. We are the Digital Risk & Compliance team. Our mission is to drive Digital Risk & Compliance to protect patient safety and Sanofi growth. One of our key drivers is to demonstrate risk & compliance health across critical digital solutions and/or third parties by providing proactive operating effectiveness insights of Digital controls through real-time monitoring and assurance. Where real-time monitoring is not yet available, we are conducting assessment & testing campaigns to check effectiveness of controls mitigating Digital risks (i.e.: Product Quality & Patient safety, Financial, Cyber risks…) What You’ll Be Doing The “Digital Risk & Compliance Expert– Controls Assurance” will be responsible to drive the execution of assessment and testing campaigns: GxP Periodic Reviews & Third Party Assessments. The DRC team is composed of around 60 team members. Your impact would go way beyond this team: our aim is, by ensuring Risk & Compliance @the speed of the business, to support the Digital transformation with a OneSanofi objective to halve the time from discovery to therapy. This role provides an opportunity to work in an international environment, into a dynamic team, fully empowered to propose and implement innovative ideas. This role will also provide the Digital Risk & Compliance Expert with hands-on experience on collaborating with diverse business teams and vendors. Main Responsibilities GxP Periodic Reviews Conduct activities related to the execution of GxP Periodic Reviews with a high level of expertise and critical thinking mindset Support the operational elements of the GxP Periodic Reviews process Identify compliance risks and areas of improvement Evaluate the adequacy of designed controls with a continuous improvement mindset Lead the improvement of the GxP Periodic Reviews process with a continuous improvement mindset, exploring synergies with other controls assurance functions (Third Party Audit), and enable transformation and automation Ensure proper and timely reporting of GxP Periodic Reviews plan progress via the maintenance of dedicated KPIs Escalate execution issues and alerts as needed Third Party Risk Assessments Support the execution of third party quality assessments and audits (typically remotely) Identify compliance risks and areas of improvement and evaluate the adequacy of designed controls, drawing conclusions and presenting findings to Third Party Audit team The position is based in the above mentioned location with the opportunity to collaborate with internal and external stakeholders located all around the globe. About You If you are passionate about Digital/IT and Quality, if you want to make a difference in how we work, you should come and join a dynamic team with great values! Based on prior experience of the selected applicant, upskilling opportunities will be provided. Education & Experience Bachelor’s degree in a scientific, engineering or Digital/IT discipline 4+ years of experience in Audit / Quality Assurance / inspection experience in regulated GxP computerized systems environments 4+ years of experience in Quality Management, Computerized Systems compliance (GxP, Sarbannes Oxley, Data Privacy, Cyber), or Information Technology contributing to regulated projects or system lifecycle activities 2+ years of experience working in the Life Sciences industry Soft skills: Stakeholder management Adaptability to a changing and highly dynamic work environment Strong critical-thinking and problem-solving skills Demonstrated leadership skills and ability to effectively influence and make decisions, in a global setting Excellent written and oral communication in English Strong interpersonal skills to effectively communicate and build effective relationships with a variety of stakeholders Pragmatic and results-driven Excellent organizational and communication skills Rigor and assertiveness with the ability to present in an impactful way High level of proactivity and autonomy with ability to alert Technical skills: Audit / Quality Assurance / inspection experience Understanding of relevant life sciences IT risk domains and controls (e.g., Data Privacy, Security) Advanced knowledge of quality management & compliance, industry standards, Sarbannes Oxley and GXP regulations applicable to computerized systems Recognized thought leader on development and maintenance of integrated controls framework Hands on knowledge of IT lifecycle approaches (including Agile practices); experience in systems validation and required controls to mitigate risks to compliance Languages: English is mandatory Sanofi Behaviors and Skills This position is required to demonstrate behaviors such as Stretch, Put the interest of the organization, Act in the interest of our patients and customers and Take Action. During the interview we will also be asking for examples of skills such as Strategic Thinking, Result Orientation, , Relationship and Influence. null Show more Show less

Role Purpose The purpose of this role is to perform the development of VLSI system by defining the various functionalities, architecture, layout and implementation for a client Do 1. Conduct verification of the module/ IP functionality and provide customer support a. Understand the architecture of the module or the IP and create verification environment and the development plan as per Universal Verification Methodology b. Create test bench development and test case coding of the one or multiple module c. Write the codes or check the code as required d. Execute the test cases and debug the test cases if required e. Conduct functional coverage analysis and document the test cases including failures and debugging procedures on SharePoint/ JIRA or any other platform as directed f. Test the entire IP functionality under regression testing and complete the documentation to publish to client g. Troubleshoot, debug and upgrade existing systems on time & with minimum latency and maximum efficiency h. Write scripts for the IP i. Comply with project plans and industry standards 2. Ensure reporting & documentation for the client a. Ensure weekly, monthly status reports for the clients as per requirements b. Maintain documents and create a repository of all design changes, recommendations etc c. Maintain time-sheets for the clients d. Providing written knowledge transfer/ history of the project Deliver No. Performance Parameter Measure 1. Verification Timeliness Quality of Code/ Number of defects Customer responsiveness Project documentation (scripts, test cases etc) 2. Self-development Skill test for next level clearance on Trend Nxt Mandatory Skills: VLSI Physical Place and Route. Experience1-3 Years.

Role Purpose The purpose of this role is to perform the development of VLSI system by defining the various functionalities, architecture, layout and implementation for a client Do 1. Conduct verification of the module/ IP functionality and provide customer support a. Understand the architecture of the module or the IP and create verification environment and the development plan as per Universal Verification Methodology b. Create test bench development and test case coding of the one or multiple module c. Write the codes or check the code as required d. Execute the test cases and debug the test cases if required e. Conduct functional coverage analysis and document the test cases including failures and debugging procedures on SharePoint/ JIRA or any other platform as directed f. Test the entire IP functionality under regression testing and complete the documentation to publish to client g. Troubleshoot, debug and upgrade existing systems on time & with minimum latency and maximum efficiency h. Write scripts for the IP i. Comply with project plans and industry standards 2. Ensure reporting & documentation for the client a. Ensure weekly, monthly status reports for the clients as per requirements b. Maintain documents and create a repository of all design changes, recommendations etc c. Maintain time-sheets for the clients d. Providing written knowledge transfer/ history of the project Deliver No. Performance Parameter Measure 1. Verification Timeliness Quality of Code/ Number of defects Customer responsiveness Project documentation (scripts, test cases etc) 2. Self-development Skill test for next level clearance on Trend Nxt Mandatory Skills: VLSI Physical Design Planning. Experience3-5 Years.

Role Purpose The purpose of this role is to perform the development of VLSI system by defining the various functionalities, architecture, layout and implementation for a client Do 1. Conduct verification of the module/ IP functionality and provide customer support a. Understand the architecture of the module or the IP and create verification environment and the development plan as per Universal Verification Methodology b. Create test bench development and test case coding of the one or multiple module c. Write the codes or check the code as required d. Execute the test cases and debug the test cases if required e. Conduct functional coverage analysis and document the test cases including failures and debugging procedures on SharePoint/ JIRA or any other platform as directed f. Test the entire IP functionality under regression testing and complete the documentation to publish to client g. Troubleshoot, debug and upgrade existing systems on time & with minimum latency and maximum efficiency h. Write scripts for the IP i. Comply with project plans and industry standards 2. Ensure reporting & documentation for the client a. Ensure weekly, monthly status reports for the clients as per requirements b. Maintain documents and create a repository of all design changes, recommendations etc c. Maintain time-sheets for the clients d. Providing written knowledge transfer/ history of the project Deliver No. Performance Parameter Measure 1. Verification Timeliness Quality of Code/ Number of defects Customer responsiveness Project documentation (scripts, test cases etc) 2. Self-development Skill test for next level clearance on Trend Nxt Mandatory Skills: Semiconductor Integration. Experience3-5 Years.