733 Drc Jobs - Page 23

Full Chip Physical Design Engineer Job Summary: We are seeking a highly motivated and skilled engineer to join our SoC implementation team. You will be responsible for the physical design of complex ASICs and SoCs, working on full-chip floorplanning, integration, and signoff activities to meet aggressive PPA (Power, Performance, Area) goals. Key Responsibilities: Drive full chip-level physical design flow from RTL to GDSII. Ownership of chip-level floorplanning, partitioning, and integration. Collaborate with RTL, synthesis, DFT, and STA teams to resolve cross-functional issues. Implement place & route flows including timing closure, IR/EM, and congestion optimization. Perform physical verification (LVS/DRC/ERC) and work with foundries to fix violations. Manage static timing analysis (STA) at top level and work closely with timing owners for signoff. Handle power planning and power domain implementation (UPF/CPF-based). Contribute to methodology improvements and automation. Required Qualifications: Bachelor's or Master’s degree in Electrical/Electronics/Computer Engineering or related field. 3–6 years of experience in physical design with at least one full chip tapeout. Hands-on expertise with industry-standard tools such as Synopsys (ICC2, Fusion Compiler, PrimeTime), Cadence (Innovus), and Mentor (Calibre). Strong knowledge of physical design concepts: floorplanning, CTS, routing, timing closure, IR drop, EM, DRC/LVS. Proficiency in scripting languages like Tcl, Perl, Python, or Shell. Familiarity with hierarchical design and ECO flows. Experience: 3 to 6 Years. Location: Bangalore / Hyderabad . Notice Period: Less than 30 days Show more Show less

Contracts manager as per the JD given below for Agra Metro AGCC07. B.E. Civil Engineering PG in Construction/Contracts Management – preferred Sound knowledge in FIDIC red book Sound knowledge in project scheduling, EoT / Delay analysis and programming software like primavera and MSP. Experience in operations with good understanding of infrastructure works (Metros) Identification and monitoring of Project risks and opportunities in a timely manner. Drafting & Vetting of Contractual communications/project correspondences. Ensuring timely notices for various issues arising at site pertaining to Extension of time, variations, settlement of disputes. Handling of Delay and Disruption claims. Experience in Dispute resolution processes such as DAB, DRC, Conciliation, Mediation, Amicable settlement. Show more Show less

Role Description Physical Design Engineer Exp:4 to 7 Handled Netlist to GDS II at block level for multiple tape outs. Hands-on experience on technology nodes like 28nm, 20nm, 14nm, 10nm Good knowledge of EDA tools from Synopsys , Cadence and Mentor, particularly experience with ICC, PTSI, Encounter, Nanoroute, Calibre, StarRC Hands-on experience in floor planning, placement optimizations, CTS and routing. Hands-on experience in block/top level signoff STA, physical verification (DRC/LVS/ERC/antenna) checks and other reliability checks(IR/EM/Xtalk) Exposure in physical implementation of timing/functional ECO’s Good knowledge of VLSI process and device characteristics TCL, perl scripting. Skills Physical Design,DRC,LVS,ERC,antenna Show more Show less

Company Description Sandisk understands how people and businesses consume data and we relentlessly innovate to deliver solutions that enable today’s needs and tomorrow’s next big ideas. With a rich history of groundbreaking innovations in Flash and advanced memory technologies, our solutions have become the beating heart of the digital world we’re living in and that we have the power to shape. Sandisk meets people and businesses at the intersection of their aspirations and the moment, enabling them to keep moving and pushing possibility forward. We do this through the balance of our powerhouse manufacturing capabilities and our industry-leading portfolio of products that are recognized globally for innovation, performance and quality. Sandisk has two facilities recognized by the World Economic Forum as part of the Global Lighthouse Network for advanced 4IR innovations. These facilities were also recognized as Sustainability Lighthouses for breakthroughs in efficient operations. With our global reach, we ensure the global supply chain has access to the Flash memory it needs to keep our world moving forward. Job Description We are looking for technically sound and highly skilled High-speed SERDES IO PHY Layout designer with 12-15 years of experience. Apart from Serdes PHY Layout, the ideal candidate should have a strong background in analog/IO design principles, hands-on experience with layout tools, and a passion for solving challenging technical problems. Key Responsibilities: Develop and optimize Serdes PHY, analog and mixed-signal IC layouts, ensuring high performance and manufacturability. Collaborate with design engineers to understand design requirements and translate them into precise layouts. Strong experience in debugging DRC, ERC, LVS, EMIR and PERC issues independently. Work closely with the physical design team to integrate custom blocks into the overall chip design. Identify and resolve layout-related issues, providing creative solutions to meet design specifications. Conduct design reviews and provide technical feedback to improve layout practices and methodologies. Stay up-to-date with industry trends, tools, and technologies to continuously enhance layout processes. Qualifications 12-15 years of experience in Serdes Phy, Analog and Mixed-signal IC layout design. Proficiency in layout tools such as Cadence, Synopsys, or Mentor Graphics. Hands-on experience with custom layout design for various Serdes Phy, Analog and IO circuits is required, including expertise in Bandgap references, LDOs, Clocking circuits, GPIOs, DDR IOs. Familiarity with custom digital layout (i.e. high speed logic paths). Knowledge of signal integrity issues (i.e. clock/data routes, differential routing, shielding). Strong understanding of analog/IO design principles, including circuit performance and parasitic effects. Aware of layout techniques to mitigate ESD, latch-up issues. Holds advanced knowledge of CMOS and FinFET technologies and their impact on design and performance issues in deep sub-micron process nodes, specifically 5nm and below. Experience with layout concepts that incorporate reliability considerations, including techniques for managing electromigration (EM), IR drop, and self-heating. Experience with layout optimization for power, performance, and area (PPA) metrics. Excellent problem-solving skills and attention to detail. Effective communication and teamwork abilities. Preferred Skills: Knowledge of scripting languages (e.g., Skill,TCL and SVRF) for automation tasks. Qualifications Bachelor’s or Master’s degree in Electronics or Electrical Engineering Additional Information Sandisk thrives on the power and potential of diversity. As a global company, we believe the most effective way to embrace the diversity of our customers and communities is to mirror it from within. We believe the fusion of various perspectives results in the best outcomes for our employees, our company, our customers, and the world around us. We are committed to an inclusive environment where every individual can thrive through a sense of belonging, respect and contribution. Sandisk is committed to offering opportunities to applicants with disabilities and ensuring all candidates can successfully navigate our careers website and our hiring process. Please contact us at jobs.accommodations@sandisk.com to advise us of your accommodation request. In your email, please include a description of the specific accommodation you are requesting as well as the job title and requisition number of the position for which you are applying. Show more Show less

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. Job Description To develop & integrate foundry rule decks & technology files to support PDKs by using foundry provided process design kits as a starting point. PDK QA, verification and release methodology for decks and specialized setups including track patterns to aid in layout. Responsible for physical verification methodology, including installation, development, qualification, automation, and support – To develop scripts to automate LVS, DRC, RM,IR and Parasitic Extraction flows. And to support layout teams in verification flow issues. Ensuring QA of the integrated PDK’s with the custom design environment Add sub scripts to improve efficiency on QA process with adequate coverage. General tool usage support – real-time support of all tools, creating bug workarounds and filing CCRs with R&D Responsible for rule deck development - to implement process design rules into physical verification rules decks and QC for the rule decks. Responsible for interfacing with the design teams and foundry team to develop and verify our PDKs. Develop, own and maintain an automation frame work for efficiency improvement perspective for the design environment. Position Requirements Bachelor’s Degree in Electrical/Electronic Engineering or equivalent . 4-7 years of Work experience in PDK development and CAD enablement. Expertise in Cadence Python, SKILL, Perl programming languages. Knowledge of deep sub-micron CMOS processes, device physics and layout design. Experience with Cadence custom IC Virtuoso platform to create layout test structures, to validate verification rules and to troubleshoot errors. Experience in developing PDK device library components and definitions including SKILL parameterized cells (Pcell), symbols, CDF, callbacks, simulation/netlisting. Experience with physical verification tools for DRC, LVS and parasitic extraction, Cadence PVS, Assura is a plus. Working knowledge of revision control software (Git, sos, Subversion, Synchronicity, etc) Understanding on Pcell creation and enhancements to pcell parameters, device call backs etc is a plus Excellent technical problem solving skills. Excellent communication and presentation skills. We’re doing work that matters. Help us solve what others can’t. Show more Show less

Drafting, review and negotiation of contracts Confidential, Joint Venture, Consortium, Service provider agreements. Sound knowledge in FIDIC Contracts, NHAI Contracts, NPCIL Contracts, CPWD Contracts. Experience in operations with good understanding of infrastructure works Identification and monitoring of Project risks and opportunities in a timely manner. Drafting of Contractual communications/project correspondences. Ensuring timely notices for various issues arising at site pertaining to Extension of time, variations, settlement of disputes. Handling of Delay and Disruption claims. Must have knowledge in Indian Arbitration Act 1996(Amended on 2015 & 2019) and Indian Contract Act 1872. Experience in Dispute resolution processes such as DAB, DRC, Conciliation, Mediation, Amicable settlement (Preferred) Knowledge in project scheduling, EoT / Delay analysis and programming software like primavera and MSP. Show more Show less

Introduction Physical design team is responsible for designing high performance microprocessor blocks for IBM Power and z mainframe servers. Your Role And Responsibilities Responsible for high performance microprocessor blocks RTL to GDSII implementation Perform block level synthesis, floor-planning, placement and routing. Close the design to meet timing, power budget and area. Implement ECO's to address functional bugs and timing violations. Team player, with good problem solving and communication skills. Preferred Education Master's Degree Required Technical And Professional Expertise 5-8 years industry experience in physical design methodology. Good knowledge and hands on experience in physical design methodology which include logic synthesis,placement, clock tree synthesis, routing . Should be knowledgeable in physical verification ( LVS,DRC.. etc), Noise analysis, Power analysis and electro migration . Team player with good problem solving skills, communication skills and leadership skills. Preferred Technical And Professional Experience Automation skills in PYTHON, PERL ,SKILL and/or TCL Show more Show less

Job Description M.E./M.Tech in Electronics/Electrical Engineering with minimum of 10 years of strong, hands on Physical Design experience. Must have handled Netlist to GDS II at Top level or Hierarchical top level for at least 5 tape outs. Must have lead physical design team with hands on exposure in most of the following depending up on senior level or lead level role. Should have experience in 28nm & below technologies (preferably 20nm & below). Top level die size estimation, floor-planning, power estimation, power planning. IO Planning and package compatibility sign off. ESD analysis on IO ring and sign off. Netlist and constraint sign in checks and validation. Design implementation environment setup. Static and Dynamic power analysis at the top level. Netlist to GDS II implementation at chip level Hierarchical chip planning, block planning, block level constraint development, hierarchical clock tree implementation, block integration and chip finishing. Multimode multi corner optimization and closure at top level. Clock tree synthesis and advanced clock tree implementation at full chip level. Top level timing closure with sign off STA in MMMC with cross-talk and OCV. Top level ECO implementation strategy development for netlist, RTL and timing level changes Methodology development, customization as per the specific design need. Good hands-on knowledge in reference flows, excellent debugging skills. Scripting experience in Perl/TCL. Flow customization and fine tuning for Power, Performance, Area. Technical leadership and ability to mentor and make the team deliver. Strong inter-personal skills and ability to work with multiple teams. In depth exposure in Implementation in any of the following platforms. FC/ICC/Innovus; Tool exposure in Sign Off DRC/LVS : Calibre Timing sign off : Primetime PNA : Apache -Redhawk Job Type: Full-time Experience: Physical Design: 10-15 years Should have worked as technical lead for at least 2 projects. Requirement M.E./M.Tech in Electronics/Electrical Engineering with minimum of 10 years of strong, hands on Physical Design experience. Must have handled Netlist to GDS II at Top level or Hierarchical top level for at least 5 tape outs. Must have lead physical design team with hands on exposure in most of the following depending up on senior level or lead level role. Should have experience in 28nm & below technologies (preferably 20nm & below). Top level die size estimation, floor-planning, power estimation, power planning. IO Planning and package compatibility sign off. ESD analysis on IO ring and sign off. Netlist and constraint sign in checks and validation. Design implementation environment setup. Static and Dynamic power analysis at the top level. Netlist to GDS II implementation at chip level Hierarchical chip planning, block planning, block level constraint development, hierarchical clock tree implementation, block integration and chip finishing. Multimode multi corner optimization and closure at top level. Clock tree synthesis and advanced clock tree implementation at full chip level. Top level timing closure with sign off STA in MMMC with cross-talk and OCV. Top level ECO implementation strategy development for netlist, RTL and timing level changes Methodology development, customization as per the specific design need. Good hands-on knowledge in reference flows, excellent debugging skills. Scripting experience in Perl/TCL. Flow customization and fine tuning for Power, Performance, Area. Technical leadership and ability to mentor and make the team deliver. Strong inter-personal skills and ability to work with multiple teams. In depth exposure in Implementation in any of the following platforms. FC/ICC/Innovus; Tool exposure in Sign Off DRC/LVS : Calibre Timing sign off : Primetime PNA : Apache -Redhawk Job Type: Full-time Experience: Physical Design: 10-15 years Should have worked as technical lead for at least 2 projects. Show more Show less

At Juniper, we believe the network is the single greatest vehicle for knowledge, understanding, and human advancement the world has ever known. To achieve real outcomes, we know that experience is the most important requirement for networking teams and the people they serve. Delivering an experience-first, AI-Native Network pivots on the creativity and commitment of our people. It requires a consistent and committed practice, something we call the Juniper Way. Job Description At Juniper, we believe the network is the single greatest vehicle for knowledge, understanding, and human advancement the world has ever known. To achieve real outcomes, we know that experience is the most important requirement for networking teams and the people they serve. Delivering an experience-first, AI-Native Network pivots on the creativity and commitment of our people. It requires a consistent and committed practice, something we call the Juniper Way. Physical Design Engineer Experience: 4+ Years Job Specification Work with internal Design teams and Methodology teams to successfully Lead/implement Physical Designs of multiple blocks of Complex ASICs . The position requires good understanding of the physical design flow from RTL to GDS & several chips tapeout experience. The successful candidate should possess in-depth knowledge & experience in physical synthesis, design planning, floor planning, place & route, static timing analysis and design closure & physical verification Responsibilities Will be responsible for all aspects of Physical Design for Fullchip/Blocks covering Floorplanning, Placement, Budgeting, Clock Tree planning & analysis, Scan re-ordering, Clock tree synthesis, Placement optimizations, Routing, Timing and SI analysis/closure, ECO tasks (both timing and functional), EM/IR, DRC, LVS, ERC analysis & fixes, Low Power solution development & implementation. Prefer sound knowledge in EDA tools such as DC, ICC2, Cadence Innovus, STAR-RC, PT-SI, Verplex, Quartz, Calibre, internal tools & flow, etc. Work closely with the methodology team to solve the implementation challenges & provide inputs to improve the Physical design flow. Experienced in design automation. Understanding of Timing constraints, SI prevention, Power reduction. Must have prior experience with Synopsys/Cadence/Mentor place and route tools. Must have completed design in 16nm and or 7nm.. Proficient in Unix/TCL/Perl. Good communication and presentation skills. Requires good interpersonal skills and problem-solving ability. Minimum Qualifications 4+ years experience in ASIC physical design Experience with block implementation, extraction, timing and or full-chip designs Strong communication skills Strong hands-on TCL/Perl development skills Preferred Qualifications Experience as a full-chip floorplanning, routing, or timing lead for a large silicon project Track record of taping out complex chips on advanced process nodes About Juniper Networks Juniper Networks challenges the inherent complexity that comes with networking and security in the multicloud era. We do this with products, solutions and services that transform the way people connect, work and live. We simplify the process of transitioning to a secure and automated multicloud environment to enable secure, AI-driven networks that connect the world. Additional information can be found at Juniper Networks (www.juniper.net) or connect with Juniper on Twitter, LinkedIn and Facebook. WHERE WILL YOU DO YOUR BEST WORK? Wherever you are in the world, whether it's downtown Sunnyvale or London, Westford or Bengaluru, Juniper is a place that was founded on disruptive thinking - where colleague innovation is not only valued, but expected. We believe that the great task of delivering a new network for the next decade is delivered through the creativity and commitment of our people. The Juniper Way is the commitment to all our colleagues that the culture and company inspire their best work-their life's work. At Juniper we believe this is more than a job - it's an opportunity to help change the world. At Juniper Networks, we are committed to elevating talent by creating a trust-based environment where we can all thrive together. If you think you have what it takes, but do not necessarily check every single box, please consider applying. We’d love to speak with you. Additional Information for United States jobs: ELIGIBILITY TO WORK AND E-VERIFY In compliance with federal law, all persons hired will be required to verify identity and eligibility to work in the United States and to complete the required employment eligibility verification form upon hire. Juniper Networks participates in the E-Verify program. E-Verify is an Internet-based system operated by the Department of Homeland Security (DHS) in partnership with the Social Security Administration (SSA) that allows participating employers to electronically verify the employment eligibility of new hires and the validity of their Social Security Numbers. Information for applicants about E-Verify / E-Verify Información en español: This Company Participates in E-Verify / Este Empleador Participa en E-Verify Immigrant and Employee Rights Section (IER) - The Right to Work / El Derecho a Trabajar E-Verify® is a registered trademark of the U.S. Department of Homeland Security. Juniper is an Equal Opportunity workplace. We do not discriminate in employment decisions on the basis of race, color, religion, gender (including pregnancy), national origin, political affiliation, sexual orientation, gender identity or expression, marital status, disability, genetic information, age, veteran status, or any other applicable legally protected characteristic. All employment decisions are made on the basis of individual qualifications, merit, and business need. Show more Show less

Lead design of analog/mixed-signal ICs (ADC/DAC, PLL, LDO/DCDC, IO Drivers). Oversee verification, layout compliance, cross-functional collaboration, and product support. Utilize EDA tools for design, simulation, and debugging. Required Candidate profile Experienced analog/mixed-signal IC designer (8+ yrs), adept in variation-aware design, verification, debugging, and product support. Strong in cross-functional collaboration. Masters in VLSI or ECE

About Nxtwave: NxtWave is founded by Rahul Attuluri (Ex-Amazon, IIIT Hyderabad), Sashank Reddy (IIT Bombay), and Anupam Pedarla (IIT Kharagpur). In February 2023, NxtWave raised ₹275 crore led by Greater Pacific Capital, a leading international private equity firm . The startup is also backed by Orios Ventures, Better Capital, and marquee angels, including founders of some of India’s unicorns. NxtWave is one of India’s fastest-growing Ed-Tech startups , revolutionizing the 21st-century job market by transforming youth into highly skilled tech professionals irrespective of their educational background with its CCBP 4.0 programs. As an official partner for NSDC under the Ministry of Skill Development & Entrepreneurship, Government of India, and recognized by NASSCOM, Ministry of Commerce and Industry, Government of India, and Startup India, NxtWave has earned a reputation for excellence. The startup has received accolades such as ‘The Greatest Brand in Education’ in a research-based listing by URS Media, a leading international media house. NxtWave has also been honored with the "Startup Spotlight Award 2023" by T-Hub on its 8th Foundation Day. Recently, NxtWave’s founders, Anupam Pedarla and Sashank Gujjula, were honored in the 2024 Forbes India 30 Under 30 for their exceptional contribution to transforming the tech education landscape in India. The edtech brand eliminates the entry barrier to learning tech skills by offering vernacular content and interactive learning. Learning in one’s mother tongue helps achieve higher comprehension, deeper attention, longer retention, and greater outcomes. Presently, NxtWave has paid subscribers from 647+ districts across India. In just 2.5 years, CCBP 4.0 learners have been hired by 1700+ companies , including Google, Amazon, Nvidia, Goldman Sachs, Oracle, Deloitte, and more. Know more about NxtWave: https://www.ccbp.in Our LinkedIn page: Link Next wave of opportunities with 1700+ companies - Link 33M funding news - Link Youtube Channel - Link Impact Stores on LinkedIn - Link Read more about us in the news - Economic Times | CNBC | Yourstory | VCCircle About the Role We are seeking a meticulous and technically proficient Sound Engineer to join our in-house video production team. In this role, you will take ownership of the audio production pipeline , from on-set recording to post-production mixing and mastering. You’ll play a crucial role in ensuring our video content —whether educational masterclasses, brand films, testimonials, or explainers—delivers pristine, immersive audio that complements our high-caliber visuals. Your expertise will directly impact the viewer experience , ensuring clarity , consistency , and professional broadcast quality sound across all our productions. Key Responsibilities On-Set Audio Recording Plan and execute location sound recording , ensuring clean dialogue capture , minimal ambient noise, and optimal mic placement for various video formats. Operate and manage professional audio recording equipment , including shotgun microphones , lavalier systems , audio recorders , boom poles , and wireless audio kits . Conduct sound checks , monitor levels in real time, and troubleshoot issues on set to ensure uncompromised audio capture . Implement best practices for soundproofing and ambient control , particularly in studio environments. Audio Post-Production Perform audio editing , clean-up , mixing , and mastering for all types of video content. Reduce noise, hums, and unwanted frequencies using industry-standard software like Adobe Audition , Pro Tools , or DaVinci Resolve Fairlight . Synchronize audio with video footage, ensuring lip sync accuracy and audio continuity . Design and incorporate sound effects , room tone , and background scores , collaborating with composers or sourcing royalty-free libraries when required. Sound Quality & Consistency Maintain a consistent audio signature and brand sound identity across all videos. Ensure voice clarity , balanced tone , and correct loudness levels , optimized for various platforms (YouTube, LMS, social media, etc.). Implement Loudness Standards (LUFS), Dynamic Range Control (DRC) , and EQ balancing appropriate for the content type. Equipment Management & Workflow Optimization Manage, maintain, and upgrade audio equipment inventory , including microphones, audio interfaces, mixers, and monitoring systems. Recommend and integrate new technologies or tools that enhance recording quality or workflow efficiency. Document and refine audio production workflows , ensuring smooth handoffs between recording, post, and delivery teams. What We’re Looking For Experience : 2+ years as a Sound Engineer , Location Sound Recordist , or Audio Post-Production Specialist in professional video production environments. Technical Proficiency : Mastery of audio recording tools (Zoom F series, Sound Devices MixPre, Rode, Sennheiser, Shure, or equivalent professional microphones). Strong command over DAWs (Adobe Audition, Pro Tools, Fairlight, Logic Pro). Familiarity with audio plugins for noise reduction , de-reverb , EQ , compression , and limiting . Attention to Detail : Acute sensitivity to audio imperfections , pacing , volume consistency , and tonal balance . Problem Solving : Ability to troubleshoot live sound issues swiftly and effectively, ensuring minimal downtime on shoot days. Collaborative Spirit : Comfort working in close coordination with cinematographers , directors , and editors , with a proactive approach to creative problem-solving . Nice to Have Experience with 5.1 Surround and immersive audio formats . Knowledge of Foley recording , ADR , and voiceover session direction . Familiarity with audio for animation and motion graphics projects. Understanding of broadcast standards and delivery formats for OTT, YouTube, and LMS platforms. Why Join Us? At NxtWave , we believe sound is not just an accessory—it’s a driving force behind emotional impact and engagement. As a Sound Engineer , you will have the opportunity to shape the sonic identity of our content, ensuring that every word, every note, and every silence contributes to an exceptional learning and brand experience . You’ll be part of a creative, future-forward team , working on projects that redefine education through cinematic storytelling . Show more Show less

Company: Qualcomm India Private Limited Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: Qualcomm GPU team is actively seeking candidates for several physical design engineering positions. Graphics HW team in Bangalore is part of a worldwide team responsible for developing and delivering GPU solutions which are setting the benchmark in mobile computing industry.Team is involved in Architecture, Design, Verification, implementation and Productization of GPU IP COREs that go into Qualcomm Snapdragon SOC Products used in Smartphone, Compute, Automotive, AR/VR and other low power devices. Qualcomm has strong portfolio of GPU COREs and engineers get an opportunity to work with world class engineering team that leads industry through innovation and disciplined execution. As a Graphics physical design engineer, you will innovate, develop, and implement GPU cores using state-of-the-art tools and technologies. You will be part of a team responsible for the complete Physical Design Flow and deliveries of complex, high-speed, low power GPU COREs. Tasks also involve the development and enablement of low power implementation methods, customized P&R to achieve area reduction and performance goals. Additional responsibilities in this role involves good understanding of functional, test (DFT) mode constraints for place and route, floorplanning, power planning, IR drop analysis, placement, multi-mode & multi-corner (MMMC) clock tree synthesis, routing, timing optimization and closure, RC extraction, signal integrity, cross talk noise and delay analysis, debugging timing violations for multi-mode and multi-corner designs, implementing timing fixes, rolling in functional ECOs, debugging and fixing violations and formal verification. The individual also should have deep knowledge on scripting and software languages including PERL/TCL, Linux/Unix shell and C. This individual will design, verify and delivers complex Physical Design solutions from netlist and timing constraints to the final product. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. Minimum Qualifications Bachelor's/Master’s degree in Electrical/Electronic Engineering from reputed institution 12+ years of experience in Physical Design/Implementation Minimum Requirements: Physical Implementation activities for high performance GPU Core, which includes Floor-planning, Place and Route, CTS, Formal verification, Physical Verification (DRC/LVS), PDN, Timing Closure and power optimization. Should have good exposure to PD implementation of PPA critical Cores and making right PPA trade-off decisions. Strong expertise in timing convergence of high frequency data-path intensive Cores and advanced STA concepts Well versed with the Block level PnR convergence with Synopsys ICC2/ Cadence Innovus and timing convergence in PTSI/Tempus in latest technology nodes Good understanding of clocking architecture. Should be able work in close collaboration with design, DFT and PNR teams and resolve issues wrt constraints validation, verification, STA, Physical design, etc. Well versed with Tcl/Perl Scripting Experience of working as part of a larger team and working towards project milestones and deadlines; Handle technical deliverables with a small team of engineers. Strong problem-solving skills and good communication skills. Applicants : Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries). Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law. To all Staffing and Recruiting Agencies : Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications. If you would like more information about this role, please contact Qualcomm Careers. 3071473 Show more Show less

SAP DRC Consultant (Document & Reporting Compliance) India – Remote Long-term Contract Job Description: Looking for a senior SAP Consultant (10+ years) with strong experience in DRC, statutory reporting, and S/4HANA for a global ECC to S/4 project. Key Skills: SAP SD or FICO, S/4HANA DRC, VAT/GST, European tax reporting Debugging, testing, and documentation Strong financial process understanding Please email resumes to hr@sapdeck.com Show more Show less

Job TitleAI/ML Engineer - Time Series Forecasting & Clustering LocationBangalore Experience2+ Years Job TypeFull-Time Mandatory Skills: AI/ML Engineer with Time Series Forecasting & Clustering experience Responsibilities in Brief: Time Series Forecasting Build models to predict trends from time series data. Clustering Develop algorithms to group and analyze data segments. Data Insights Analyze data to enhance model performance. Team Collaboration Work with teams to integrate models into products. Stay Updated Apply the latest AI techniques to improve solutions. Qualifications: Education Bachelor s/Master s in Computer Science or related field. Experience Hands-on experience with time series forecasting and clustering. Skills Proficient in Python, R, and relevant ML tools Perks & Benefits: Health and WellnessHealthcare policy covering your family and parents. FoodEnjoy scrumptious buffet lunch at the office every day. Professional DevelopmentLearn and propel your career. We provide workshops, funded online courses and other learning opportunities based on individual needs. Rewards and RecognitionsRecognition and rewards programs in place to celebrate your achievements and contributions. Why join Relanto Health & FamilyComprehensive benefits for you and your loved ones, ensuring well-being. Growth MindsetContinuous learning opportunities to stay ahead in your field. Dynamic & InclusiveVibrant culture fostering collaboration, creativity, and belonging. Career LadderInternal promotions and clear path for advancement. Recognition & RewardsCelebrate your achievements and contributions. Work-Life HarmonyFlexible arrangements to balance your commitments. To find out more about us, head over to our Website and LinkedIn

Company Description ComTek Solutions is a global technology services and outsourcing provider specializing in SAP implementations, managed services, and staff augmentation. With headquarters in Virginia, USA, and offshore delivery centers in Hyderabad and Vizag, INDIA, ComTek focuses on IT industry best practices and a simple approach to enterprise applications. The company offers core services in SAP S/4 HANA Conversions & Migrations, SAP Ariba, SAP GRC, SAP SuccessFactors, and SAP Cloud Support. Role Description This is a contract remote role for a SAP DRC Consultant at ComTek Solutions. The SAP DRC Consultant will be responsible for implementing, configuring, and supporting SAP DRC solutions to ensure compliance with local and international regulations related to e-invoicing, e-reporting, and statutory compliance. Primary responsibilities include: - Implement and configure SAP Data Retention and Compliance (DRC) solutions. Analyze data retention policies and ensure compliance with regulations. Develop and maintain documentation for data management processes. Collaborate with stakeholders to identify data retention requirements. Monitor and report on data compliance status and issues. Provide training and support to users on DRC tools and practices. Show more Show less

Company Qualcomm India Private Limited Job Area Engineering Group, Engineering Group > Hardware Engineering General Summary As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. IPPD: Physical design engineer Physical Implementation activities for high performance Cores for 16/14/7/5nm or lower technologies, which includes all or some of the below. Floor-planning, Place and Route, CTS, Formal verification, Physical Verification (DRC/LVS), Low Power verification, PDN, Timing Closure and / or power optimization Exposure to PD implementation of PPA critical cores. Exposure to timing convergence of high frequency data-path intensive Cores and advanced STA concepts. Able to handle Block level PnR convergence with Synopsys ICC2/ Cadence Innovus and timing convergence in PTSI/Tempus in latest technology nodes. Understanding of clocking architecture. Tcl/Python/Perl Scripting aware for small automation Strong problem-solving skills , good communication skills and good team player Collaborate with design, DFT and PNR teams and support issue resolutions wrt constraints validation, verification, STA, Physical design, etc. Applicants : Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries). Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law. To all Staffing and Recruiting Agencies : Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications. If you would like more information about this role, please contact Qualcomm Careers. 3073060 Show more Show less

Selected Intern's Day-to-day Responsibilities Include Circuit Schematic Creation: Assist in creating and editing circuit schematics using Electronic Design Automation (EDA) tools like Altium Designer, Eagle, or KiCad. Simulation: Perform circuit simulations using software Spice to check the behavior of the design before physical implementation. Breadboarding and Prototyping Building Prototypes: Assemble circuits on breadboards Testing and Troubleshooting: Conduct basic testing of the circuits, troubleshooting and identifying issues such as incorrect connections or faulty components. Measurement and Data Collection: Use tools like multimeters, oscilloscopes, and signal generators to measure voltage, current, frequency, and other parameters. PCB Layout: Assist in designing the layout for printed circuit boards (PCBs) using CAD software. Component Placement: Help in placing components on the PCB based on the schematic, ensuring the design follows best practices for routing, grounding, and signal integrity. Design Rule Checks: Run design rule checks (DRC) to ensure that the PCB design follows manufacturing standards. Documenting Designs: Record detailed notes and diagrams for the design process, including schematics, component values, and testing results. Reporting: Prepare and present progress reports on ongoing design projects to the team or mentor. About Company: Toyart is a STEAM kit manufacturer company. Our business focuses on producing educational kits designed to teach science, technology, engineering, arts, and mathematics (STEAM) concepts in an engaging, hands-on manner. These kits are targeted toward students of various age groups, from elementary to high school, and sometimes even adults, to help them gain practical skills and foster creativity. The primary goal of the company is to make learning fun and interactive while enhancing critical thinking, problem-solving, and teamwork abilities. Show more Show less

Project Role : Application Lead Project Role Description : Lead the effort to design, build and configure applications, acting as the primary point of contact. Must have skills : SAP Integration with Vertex O Series/Sabrix, SAP FI CO Finance, Tax regimes, including Sales & Use, VAT, GST, HST, Solid Experience in Corporate Taxation Good to have skills : No Function Specialty Minimum 5 year(s) of experience is required Educational Qualification : 15 years full time education Summary :As an Application Lead, you will lead the effort to design, build, and configure applications, acting as the primary point of contact. Your day will involve overseeing project progress, coordinating with teams, and ensuring successful application development. We are seeking a Senior Tax Technology Specialist to join our team. This role requires a seasoned professional with extensive experience in tax engines, indirect tax management (particularly Vertex O Series), and a strong foundation in SAP systems. The ideal candidate will manage complex tax project across the Sales and Use Tax, helping to streamline tax processes and maintain global compliance. Roles & Responsibilities: Implementing new requirements and maintaining the Vertex O Series system, focusing on the global indirect tax solution Configuring and managing Vertex tax rules, rates, and jurisdictions to ensure precise and compliant tax calculations for all transactions - Supporting mapping updates to tax matrices and conducting end-to-end testing to ensure no regression impacts across jurisdictions (US and OUS) Collaborating with IT and finance teams to align tax systems with business needs and compliance requirements Developing and maintaining detailed documentation, including SOPs and user guides, for Vertex-related processes Professional & Technical Skills: Must To Have Skills:Proficiency in SAP Integration with Vertex O Series/Sabrix, SAP FI CO Finance Strong understanding of SAP FI CO Finance Must Have Skills:Experience in SAP Integration with Vertex O Series/Sabrix along with SAP FI CO Finance Extensive experience with Vertex O Series and familiarity with SAP tax-related solutions Strong knowledge of tax regimes, including Sales & Use, VAT, GST, HST, and Corporate Tax Excellent analytical skills and keen attention to detail Good To Have Skills:Experience in BRIM/FICA modules and DRC is beneficial but not mandatory Good To Have Skills:Experience in SAP ABAP development, SAP PI/PO, and SAP SD/MM modules. Additional Information: The candidate should have a minimum of 8+ years of experience in SAP Integration with Vertex O Series/Sabrix. This position is based at our Bengaluru office. A 15 years full-time education is required. Qualifications 15 years full time education

Skill required: Network Services - Cisco Routing and Switching Operations Designation: Business Advisory Associate Qualifications: Any Graduation Years of Experience: 1 to 3 years What would you do? "Helps transform back office and network operations, reduce time to market and grow revenue, by improving customer experience and capex efficiency, and reducing cost-to-serveLooking for a candidate who has expertise in Networking and has good knowledge on fundamentals of NetworkA solution that validates the ability to install, configure, operate, and troubleshoot medium-size route and switched networks." What are we looking for? " Agility for quick learning Ability to work well in a team Process-orientation Written and verbal communication Network fundamentals Understanding all the networking devicesRouters, switches, etc. IP connectivity, access, addressing, and services Network security fundamentals Installation, Configuration, Operation, Administration, and Troubleshooting Fundamental IPv4 & IPv6 Business Networks Excellent Communication Problem Solving Skills Flexibility Teamwork Experience and working knowledge on OSI Layer 1 (Physical) and 2 (Datalink) troubleshooting (WAN point to point connection) Experience and working knowledge with IP, WAN, OSI layer, TCP/IP models, IPv4/v6 addressing, subnetting and Ethernet. Layer 1 to Layer 3 fault isolation and troubleshooting with telco providers and onsite technicians. Experience working with internal groups (e.g., order entry, test & turn-up, sales), and third party client/vendors and LEC s (preferred). Familiarity with SDH, SONET, and Ethernet concepts Basic knowledge of cabling infrastructure such as patch panels, cross-connects and fiber types. Experience working with internal groups (e.g., order entry, test & turn-up, sales), and third party client/vendors and LEC s (preferred). Experience working with global carriers in North America, LATAM, APAC, and/or EMEA Experience working in a multi-vendor DWDM optical environment Good English written/verbal communication and customer engagement skills Strong focus on providing an outstanding user experience Must be detail-oriented, with strong organizational skills Able to work independently and also in a team environment" Roles and Responsibilities: " In this role you are required to solve routine problems, largely through precedent and referral to general guidelines Your expected interactions are within your own team and direct supervisor You will be provided detailed to moderate level of instruction on daily work tasks and detailed instruction on new assignments The decisions that you make would impact your own work You will be an individual contributor as a part of a team, with a predetermined, focused scope of work Please note that this role may require you to work in rotational shifts Provide 24/7/365 monitoring of ticket queue, phones, and IRC channel Manage network events such as: Fiber cuts/ Leased Wave outage - Notify dark fiber providers of outage and manage event to resolution, verify quality of remedial work by measuring power levels etc., and provide all stakeholders with periodic updates Link Down, Latency, Packet Loss, Network Traffic Issues and Routing and BGP issues - Familiarity Provide 24/7/365 monitoring of ticket queue, phones, and IRC channel Manage network events such as: Fiber cuts/ Leased Wave outage - Notify dark fiber providers of outage and manage event to resolution, verify quality of remedial work by measuring power levels etc., and provide all stakeholders with periodic updates Link Down, Latency, Packet Loss, Network Traffic Issues and Routing and BGP issues - Familiarity and understanding of router show commands and how to interpret the output Manage client s optical network, manage alarms and faults in a multi-vendor environment, and Tracking of all work in ticketing system network interconnects with internal and external network operators Track and maintain a repository of RFOs and vendor improvements/actions and be able to represent client during external calls with 3rd party providers Manage troubleshooting, confirming fix and restoring traffic from network incidents reported by internal teams and third-party teams, engaging field resources and inventory teams as necessary. Track, coordinate and manage hardware recalls / minor card or part replacement, RMA part delivery, initiate production change requests and work with onsite techs for faulty card/part replacement Read/Parse vendor notifications and translate to Clients Production Change Request (PCR s) Look up affected circuits to include them in change request Escalate any emergency change requests for immediate review and scheduling Navigate ambiguity with unclear notifications from vendors - escalating as necessary or referring notification to other internal client teams" Qualification Any Graduation

Drafting, review and negotiation of contracts Confidential, Joint Venture, Consortium, Service provider agreements. Sound knowledge in FIDIC Contracts, NHAI Contracts, NPCIL Contracts, CPWD Contracts. Experience in operations with good understanding of infrastructure works Identification and monitoring of Project risks and opportunities in a timely manner. Drafting of Contractual communications/project correspondences. Ensuring timely notices for various issues arising at site pertaining to Extension of time, variations, settlement of disputes. Handling of Delay and Disruption claims. Must have knowledge in Indian Arbitration Act 1996(Amended on 2015 & 2019) and Indian Contract Act 1872. Experience in Dispute resolution processes such as DAB, DRC, Conciliation, Mediation, Amicable settlement (Preferred) Knowledge in project scheduling, EoT / Delay analysis and programming software like primavera and MSP. Show more Show less

If you are looking for a challenging and exciting career in the world of technology, then look no further. Skyworks is an innovator of high performance analog semiconductors whose solutions are powering the wireless networking revolution. At Skyworks, you will find a fast-paced environment with a strong focus on global collaboration, minimal layers of management and the freedom to make meaningful contributions in a setting that encourages creativity and out-of-the-box thinking. Our work culture values diversity, social responsibility, open communication, mutual trust and respect. We are excited about the opportunity to work with you and glad you want to be part of a team of talented individuals who together can change the way the world communicates. Requisition ID: 74458 Job Description Architects, designs and verifies circuits, logic, systems, algorithms, etc. to meet product requirements Determine design approaches and parameters Develops innovative new designs for patenting or protecting as trade secret Demonstrates good judgment in solving a broad range of issues, based on an advanced understanding of industry practices and company policies and procedures Responsible for custom layout, including overseeing the work of layout designers Reports on design results through design reviews, in accordance with company quality requirements and resolves action items generated as a result of these reviews Attends design reviews to provide input and learn from other designers’ experiences Research design techniques through technical publications and seminars Supports marketing in product definition Having a wide-ranging experience uses professional concepts and company objectives to resolve complex issues in creative and effective way Determines methods and procedures on new assignments and may coordinate the activities of other personnel Job Requirements A technology-related master’s degree or equivalent training and 3 or more years of analog/mixed-signal design experience developing mixed-signal ICs Strong knowledge of engineering fundamentals Advanced knowledge of CMOS fabrication processes Advanced knowledge of MOS transistors and analog/digital circuit design Knowledge of complex AD/DC analysis (poles, zeros, compensation) Advanced signal analysis knowledge Basic understanding of CMOS and BCD parasitic junctions and the risks associated with them Strong parasitic analysis knowledge (capacitance, resistance, power grid) Advanced knowledge of circuit building blocks (e.g., OPAMP, gm-C filters, switch capacitors, ADC, DAC, state-machines, and bus interfaces) Advanced understanding of layout tradeoffs for performance and size Advanced design skills in system modeling Strong knowledge of UNIX, Matlab, and circuit simulation tools Proficiency in layout verification, DRC, LVS Additional skills (one or more of these are highly desirable): Working knowledge of device physics Working knowledge of digital design and design flows System knowledge (e.g., High Performance PLLs) Knowledge of scripting language (python, shell, skill) Advanced laboratory measurement skills (analog, digital) Knowledge of MS Office documentation, spreadsheet, presentation tools or equivalent tools Excellent written and verbal presentation skills Skyworks is an Equal Opportunity Employer. All qualified applicants will receive consideration for employment without regard to race, color, religion, age, sex, sexual orientation, gender identity, national origin, disability, protected veteran status, or any other characteristic protected by law. Show more Show less

Long Description Annual maintenance contract preparation and preventive maintenance of QC and IPQA instrument as per approved procedure. Breakdown handling of QC and IPQA instrument as per approved procedure. Upkeep the records of preventive maintenance and breakdown in SAP. Qualification of new instruments and SOP preparation. To participate in failure investigation related to malfunctions. To impart training to the analysts for instruments maintenance and troubleshooting. Co-ordination with vendor service engineer of service /breakdown related activities. To maintain GMP in QC laboratory, Real time documentation. Computer system validation of laboratory instruments. Execution and implementation of quality system in laboratory. Taking part in internal calibration, out-side calibration and reviewing calibration data. Taking part in instrument cleaning maintain & Maintenance of all laboratories indents. QAMS, Caliber-e-log related activities SAP Bill & invoice clearance PO & PR related activity software handling EDMS ,SAP, caliber E log, QAMS, LIMS. etc. Competencies Innovation & Creativity Result Orientation Collaboration Customer Centricity Developing Talent Stakeholder Management Strategic Agility Process Excellence Education Graduation in Mechanical Engineering Work Experience 7 to 8 Years of experience in Quality Control as Instrument Engineer

Aion Silicon is seeking an experienced Physical Design Engineers to join our growing team in UK/Barcelona/Morocco or Hyderabad . As part of a dynamic physical implementation design team, you will be responsible for block development and potentially full chip responsibility, taking designs from RTL to GDS. This is an exciting opportunity for an individual who is self-motivated, detail-oriented, and passionate about contributing to the development of high-quality, cutting-edge designs. Key Responsibilities: Independent Work: Contribute to physical design projects with minimal supervision, delivering high-quality results. Problem Solving: Address and resolve moderate complexity design challenges, applying sound judgment to interpret results and conduct quantitative analysis. Physical Design Ownership: Take responsibility for various aspects of the physical design flow, from RTL to GDS, ensuring timely and accurate delivery. Multi-Project Management: Handle multiple assignments from different customers or teams, ensuring that deadlines and quality standards are met. Collaboration: Work closely with more experienced team members to resolve design issues, applying expertise in physical design tools and techniques. Tool Expertise: Demonstrate proficiency in one or more tools such as Synthesis, PnR, Formal verification, Custom layout techniques, Analog simulation, or Chip finishing. Documentation and White Papers: Contribute to the development of technical white papers and presentations. Sales Support: Contribute to sales activities, including Statement of Work preparation. Time Management: Maintain accurate timekeeping and manage your workload effectively. Self-Discipline: Execute design tasks efficiently, adhering to best practices and maintaining a high standard of work. Key Relationships: Internal: Reports to: Engineering Manager/Principal Engineer Collaborates with: Engineers, Senior Engineers, Principal Engineers, Project Managers, Sales, Finance, and HR teams Supervises: Physical Design Team (2-3 engineers) External: Customers: Minimal technical engineer-to-engineer communication Suppliers: EDA Tool Vendors, Foundries, and Assembly Houses Qualifications: Essential: A degree, Master's, or PhD in a relevant subject. Typically, 5+ years of experience in physical design and implementation. Desirable: Master's or PhD in a related subject with 5+ years of practical experience. Skills & Experience: Essential: Good tapeout experience on multiple technologies (e.g., 5nm, 7nm, 12nm, 28nm). Experience with physical verification checks (e.g., DRC, LVS, ANTENNA, ERC). Solid understanding of synthesis, floorplanning, placement, CTS, routing, and STA concepts. Experience with physical design tools such as: PnR tools: Synopsys ICC, Cadence EDI, Mentor Olympus Synthesis tools: Synopsys DC, Cadence RC Formal verification tools: Formality, Formalpro Physical verification tools: Mentor Calibre, Synopsys IC Validator Demonstrated ability to solve problems independently and as part of a team. Strong scripting skills in Tcl, Perl, or Python. Strong capability in managing projects and delivering results on time. Desirable: Broad knowledge across multiple sub-functions within physical design. Proven ability to contribute to multi-disciplinary teams. Attributes: Essential: Excellent self-organisation and adaptability to changing priorities. Strong leadership skills with the ability to manage and guide a small team. Ability to work under pressure and manage multiple projects simultaneously. Excellent organisational and problem-solving skills. Self-motivated with the ability to work independently. Strong attention to detail and commitment to delivering high-quality results. Why Aion? At Aion, we are passionate about pushing the boundaries of digital design. As part of our new office in Barcelona, you’ll be joining an innovative and collaborative team, with opportunities to work on cutting-edge ASIC designs. This role offers significant responsibility and the opportunity to influence the direction of key projects. If you're a skilled Physical Design Engineer with a passion for technology and leadership, we’d love to hear from you! Show more Show less

Company: Qualcomm India Private Limited Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. IPPD: Physical design engineer Physical Implementation activities for high performance Cores for 16/14/7/5nm or lower technologies, which includes all or some of the below. Floor-planning, Place and Route, CTS, Formal verification, Physical Verification (DRC/LVS), Low Power verification, PDN, Timing Closure and / or power optimization Exposure to PD implementation of PPA critical cores. Exposure to timing convergence of high frequency data-path intensive Cores and advanced STA concepts. Able to handle Block level PnR convergence with Synopsys ICC2/ Cadence Innovus and timing convergence in PTSI/Tempus in latest technology nodes. Understanding of clocking architecture. Tcl/Python/Perl Scripting aware for small automation Strong problem-solving skills , good communication skills and good team player Collaborate with design, DFT and PNR teams and support issue resolutions wrt constraints validation, verification, STA, Physical design, etc. Applicants : Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries). Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law. To all Staffing and Recruiting Agencies : Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications. If you would like more information about this role, please contact Qualcomm Careers.

Company Qualcomm India Private Limited Job Area Engineering Group, Engineering Group > Hardware Engineering General Summary As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. Job Summary This position is open for 2-10 years’ experience candidate in Qualcomm CSI (Custom/SemiCustom implementation) team Candidate will be part of CSI team working on RTL- GDS HM implementations using custom flow and methodology for custom design . Qualcomm is one of the fastest growing semiconductor organization in India making high-end Chips with the most advanced technologies. To support its growing needs, we have strong CSI team for the design, development of various highspeed and low power IP’s being used in SoC. Individual has to work on RTL-GDS implementation. This will involve innovating new solutions in close collaboration with the other design teams. Job Responsibilities Job responsibilities include design and development of custom macro using Schematic design at block level (Ex RegArray, memory subsystem) Frontend verification and model generations CLP/PAGLS/LEC verifications at block level. Functional verification using spice/gatesim. Timing Signoff using PT, Candidate should be able to collaborate with different teams. Skillset/Experience 2-10 year of experience: Strong knowledge in transistor circuit design& block level logic design of Memory subsystem & Data path. STA for the design to close Set-up, Hold, MPW, Transition, etc Design verification using ESPCV & LEC, Simulation using Finesim & HSPICE. Front-end RTL Design (Verilog RTL design, System Verilog, Synopsys Design Compiler, Cadence RTL Compiler, LEC, PLDRC, Static Timing Analysis and PTPX) Physical Design using industry-standard RTL2GDS flow including Synopsys ICC2, Cadence Encounter. Scripting in Perl/Python/Shell/Tcl for productivity is a plus IP development (custom macro transistor level design, physical integration, collateral generation, flow development) and PPA quantification. Interface with Process Technology Team to understand the complex DRC and DFM requirements of the advanced technology nodes Work with cross functional teams (Architecture, Test/Verification , Product, CAD, Layout, Physical Design) to gather/define/implement specs Transistor level implementation of the block using CMOS/Domino/Cell-Based/Data path styles Implement power/clock gating techniques, Implement power/clock gating techniques, Implement industry standard as well as custom DFT techniques Implement clock distribution using custom/CTS techniques for low skew/latency/power, Implement block layout using custom/compiler techniques using custom/semi-custom/stdcell libraries Implement block level floor planning using custom and/or tiling techniques Applicants : Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries). Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law. To all Staffing and Recruiting Agencies : Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications. If you would like more information about this role, please contact Qualcomm Careers. 3075292 Show more Show less