728 Drc Jobs - Page 11

Job title: Data Scientist - Risk & Compliance Location: Hyderabad – RMZ spire About the job We are the Digital Risk & Compliance team (DRC). Our mission is to drive Digital Risk & Compliance to protect patient safety and Sanofi growth. One of our key drivers is to foster the Digital risk culture through automation, self-service predictive/prescriptive risk monitoring. We aim to provide Digital teams with accurate, real-time, and complete data in order that they be empowered for managing risk & compliance of their Digital Solution(s) To support this journey, we are looking for a Data Scientist Lead – Risk & Compliance who will be responsible for modelling complex business problems and discovering business insights using statistical, algorithmic, mining, and visualization techniques to drive the execution of the real-time monitoring strategy. Our Hubs are a crucial part of how we innovate, improving performance across every Sanofi department and providing a springboard for the amazing work we do. Build a career and you can be part of transforming our business while helping to change millions of lives. Ready? As Data Scientist Lead – Risk & Compliance within our Digital Risk & Compliance team, you’ll be instrumental to build and develop the organization’s data infrastructure and supports the senior leadership and Digital teams with insights, management reports, and analysis for decision-making processes. We are an innovative global healthcare company with one purpose: to chase the miracles of science to improve people’s lives. We’re also a company where you can flourish and grow your career, with countless opportunities to explore, make connections with people, and stretch the limits of what you thought was possible. Ready to get started? Main responsibilities: - Data management & Transformation incl. data acquisition, analytics development, insights generation for Digital/Business and senior leadership Process & Tools configuration incl. toolsets selection, data management process design and Key Risk Indicators (KRI) development Research and implement cutting-edge techniques and tools in machine learning/deep learning/artificial intelligence to make data analysis more efficient Work closely with DRC Data Monitoring lead (who is the DRC Data Monitoring Product Owner) to prioritize controls for automation, monitoring, and design KRIs Work with DRC Strategy & Governance and technology partners to automate data management, analytics, visualization and reporting processes. About you Experience : bachelor’s degree in a scientific, engineering or Digital/IT discipline 8+ Experience in data analytics / business intelligence, machine learning, statistical modelling / data mining, and data visualization, along with proficiency in data analysis tools and languages such as Python, R, SQL, and Tableau 4+ Experience working in the Life Sciences industry. Soft skills: Business partnering and consulting. Adaptability to a changing and highly dynamic work environment Strong critical thinking and problem-solving skills Demonstrated leadership skills and ability to effectively influence and make decisions, in a global setting. Technical skills: Data transformation (data preparation, analysis, visualization, engineering) Artificial Intelligence, Machine learning engineering Coding & development Compliance of computerized system (e.g. GxP, SOX) Dashboard / report development. Experience developing deployable code and deploying models in product-focused development under an agile environment Experience in production-ready software development You’re fully autonomous and hands-on in coding and developing Languages: Fluent in English. Why choose us? Bring the miracles of science to life alongside a supportive, future-focused team. Discover endless opportunities to grow your talent and drive your career, whether it’s through a promotion or lateral move, at home or internationally. Enjoy a thoughtful, well-crafted rewards package that recognizes your contribution and amplifies your impact. Take good care of yourself and your family, with a wide range of health and wellbeing benefits including high-quality healthcare, prevention and wellness programs and at least 14 weeks’ gender-neutral parental leave. “The Data Scientist Lead will be instrumental in our transformation strategy to empower Digital teams for the risk & compliance of their Digital products”

ARTELIA GROUP , headquartered in Paris, France, is an International multidisciplinary independent group offering a full range of engineering-related services in mobility, water, energy, building and industrial sectors, from technical expertise to complex project delivery, consulting, master planning & feasibility, design & engineering, construction & project management, asset & facility management, turnkey solutions. Artelia, having 9700+ employees and a turnover of € 934 million (2023). For more details visit www.arteliagroup.com About the Artelia Consulting Engineers Limited Artelia Consulting Engineers Limited (ACE) is based in Chennai, India and is subsidiary company of ARTELIA GROUP, focusing on Engineering, Project Advisory, Infrastructure Consulting and Sustainability Advisory services across sectors and geographies. ACE projects spread across India, neighbouring countries of India, GCC countries, and Africa. Today, ACE competes with leading players in the industry, and its assignments have grown, spreading across more than 25 Indian States and also in countries like Cameroon, Senegal, DRC, Madagascar, Mali, Rwanda, Tanzania, Liberia, Ghana, Malawi, Ethiopia, Nigeria, Namibia, South Africa, Zambia, Zimbabwe, Mozambique, Angola, Uganda, Kenya, Eswatini, Mauritius, Bangladesh, Nepal, Bhutan, Qatar, Oman and Saudi Arabia. ACE has positioned itself as Knowledge hub blended with a strong underlay of social inclusion, capacity building and smart, sustainable solutions. Urgent Requirement – Contract and Planning Manager Location – Vijayawada- Andhra Pradesh Experience – Overall Experience1O years. Should be a Graduate in Civil Engineering with minimum 5 years of experience in Contract Management activities for Infrastructure Projects. Qualification – Graduate in Civil Engineering Hiring – Immediate joining / within one month Job Description Undertake contract administration and management for all project-related contractors, vendors, and suppliers on behalf of the client. Monitor program schedules and plans for compliance with the contract and advise on the impact of any non-compliance. Develop a claims management process that includes evaluation of responsibility, impact and costs, and includes a dispute resolution process. Looking for an immediate joiner. Interested candidates kindly mention the position and share your resume to No calls (Only WhatsApp No:9840701512) Job Types: Full-time, Contractual / Temporary Contract length: 12 months Schedule: Day shift Work Location: In person Application Deadline: 07/07/2025 Expected Start Date: 10/07/2025

Description Invent the future with us. Recognized by Fast Company’s 2023 100 Best Workplaces for Innovators List, Ampere is a semiconductor design company for a new era, leading the future of computing with an innovative approach to CPU design focused on high-performance, energy efficient, sustainable cloud computing. By providing a new level of predictable performance, efficiency, and sustainability Ampere is working with leading cloud suppliers and a growing partner ecosystem to deliver cloud instances, servers and embedded/edge products that can handle the compute demands of today and tomorrow. Join us at Ampere and work alongside a passionate and growing team — we’d love to have you apply. Come invent the future with us. About The Role Ampere is seeking a highly skilled and experienced candidate with proven expertise in PHY hardening, particularly in DDR and SerDes, with a focus on digital implementation and convergence. We are looking for a self-motivated individual with a proven track record in hardening state-of-the-art PHYs and contributing to the development of cutting-edge expertise. What You’ll Achieve As a PHY Hardening Engineer, you will collaborate with architects, RTL designers, packaging and PCB design teams, and post-silicon validation groups. This is an exceptional opportunity to showcase your engineering skills in a dynamic, fast-paced environment that fosters innovation and operates at the forefront of technology. High-Speed Digital Design Develop high-speed digital layouts, including DDR and other high-speed interfaces. Expertise in floor planning, bump planning, routing, power grid design, clock design/distribution, and optimization for high-speed digital circuits. Optimize layouts to minimize signal integrity issues, reduce power consumption, and meet timing, power, and manufacturability requirements. Coordinate with PHY vendors for hardening activities and deliverables. Estimate effort and timelines for PHY hardening tasks and provide feedback on timing/PDV. Chip-Level Physical Design Perform chip-level tasks such as floor planning, partitioning, and power/clock distribution. Handle chip assembly and ensure seamless integration of multiple IP blocks into the top-level design. Proficiency in using EDA tools for chip-level physical verification (DRC, LVS, ERC). Collaborate with the packaging team to refine bump placement and package routing considerations. Signal and Power Integrity Familiarity with signal and power integrity concepts in high-performance memory systems. Expertise in managing high-speed signals to mitigate issues like crosstalk, reflection, and signal degradation. Perform thermal and power integrity analysis to ensure reliable designs. Knowledge of advanced packaging techniques and considerations, an added plus Design-for-Test (DFT) Basic understanding of DFT structures, including scan chains, MBIST, and loopback mechanisms. Contribute to DFT-based timing closure activities. About You Bachelor's degree & 8 years of related experience or Master's degree & 6 years of related experience Expertise in floor planning, bump planning, routing, power grid design, clock design/distribution, and optimization for high-speed digital circuits Experience developing high-speed digital layouts, including DDR and other high-speed interfaces Handling chip assembly and ensure seamless integration of multiple IP blocks into the top-level design Proficiency in using EDA tools for chip-level physical verification (DRC, LVS, ERC) Worked with architects and RTL teams to develop physical constraints and optimize their design Integrate PHYs, controllers, and memory stacks into the top-level design Expertise in managing high-speed signals to mitigate issues like crosstalk, reflection, and signal degradation Experience with advanced packaging technologies, such as 2.5D/3D integration, TSV, and interposer-based designs Handle micro-bump design to ensure proper alignment and minimize resistance Understand the SIPI impacts of bump placement Basic understanding of DFT structures, including scan chains, MBIST, and loopback mechanisms Strong communication and articulation skills are required to excel in this role What We’ll Offer At Ampere we believe in taking care of our employees and providing a competitive total rewards package that includes base pay, bonus (i.e., variable pay tied to internal company goals), long-term incentive, and comprehensive benefits. Benefits Highlights Include Premium medical, dental, vision insurance, parental benefits including creche reimbursement, as well as a retirement plan, so that you can feel secure in your health, financial future and child care during work. Generous paid time off policy so that you can embrace a healthy work-life balance Fully catered lunch in our office along with a variety of healthy snacks, energizing coffee or tea, and refreshing drinks to keep you fueled and focused throughout the day. And there is much more than compensation and benefits. At Ampere, we foster an inclusive culture that empowers our employees to do more and grow more. We are passionate about inventing industry leading cloud-native designs that contribute to a more sustainable future. We are excited to share more about our career opportunities with you through the interview process. Ampere is an inclusive and equal opportunity employer and welcomes applicants from all backgrounds. All qualified applicants will receive consideration for employment without regard to race, color, national origin, citizenship, religion, age, veteran and/or military status, sex, sexual orientation, gender, gender identity, gender expression, physical or mental disability, or any other basis protected by federal, state or local law.

We are seeking highly motivated and talented VLSI Engineers with 2-4 years of industry experience to join our intensive Campus Training Program. This program is designed to provide in-depth, hands-on training in various aspects of VLSI design, verification, and implementation, specifically tailored to align with our current projects and future technological advancements. Upon successful completion of the training, candidates will transition into key roles within our VLSI design teams. This is an excellent opportunity for engineers looking to deepen their expertise, specialize in cutting-edge VLSI methodologies, and contribute to the development of next-generation semiconductor products. Responsibilities during the Training Program: * Actively participate in structured training modules covering advanced VLSI concepts, methodologies, and tools. * Engage in hands-on lab sessions and practical exercises to apply learned concepts. * Collaborate with trainers and mentors on assigned projects and case studies. * Complete individual and group assignments, demonstrating understanding and proficiency in VLSI sub-domains. * Participate in technical discussions, design reviews, and knowledge-sharing sessions. * Learn and adhere to industry best practices, design flows, and quality standards. * Continuously seek to improve technical skills and knowledge through self-study and provided resources. * Document progress, learning outcomes, and project work thoroughly. Key Areas of Training (may include, but are not limited to): * Digital IC Design: Advanced RTL design, low-power design techniques, clock domain crossing (CDC). * Verification: Advanced UVM/SystemVerilog methodologies, functional coverage, formal verification. * Physical Design: Floorplanning, placement, routing, clock tree synthesis (CTS), static timing analysis (STA), power integrity (PI) analysis. * Design for Testability (DFT): Scan insertion, ATPG, boundary scan. * Analog/Mixed-Signal Design (if applicable): Device physics, circuit simulation, layout considerations. * Front-End Tools: Synthesis, Linting, STA. * Back-End Tools: Place and Route, DRC/LVS. * Scripting: Perl, Python, TCL for automation. * EDA Tools: Exposure to industry-standard EDA tools from Cadence, Synopsys, Mentor Graphics (specific tools will be taught based on company needs). Required Qualifications: * Bachelor's or Master's degree in Electronics and Communication Engineering (ECE), Electrical Engineering (EE), or a related field. * 2-4 years of professional experience in VLSI design, verification, or physical design. * Strong fundamental understanding of digital electronics, circuit theory, and semiconductor physics. * Proficiency in at least one hardware description language (HDL) such as Verilog or VHDL. * Familiarity with the VLSI design flow (front-end to back-end). * Experience with scripting languages (e.g., Python, Perl, TCL) is highly desirable. * Excellent problem-solving and analytical skills. * Strong communication and interpersonal skills. * Ability to learn quickly and adapt to new technologies and methodologies. * Self-motivated with a strong desire to build a long-term career in VLSI. Preferred Qualifications (Assets): * Prior experience with specific EDA tools (Cadence Virtuoso, Synopsys DC/ICC/VCS, Mentor Graphics Calibre, etc.). * Experience with UVM methodology for verification. * Understanding of low-power design techniques. * Familiarity with formal verification concepts. * Exposure to advanced technology nodes.

In this role, you are expected to Develop algorithms in C/C++ for circuit characterization tools critical to develop standard cell libraries. Develop applications using the latest Web technologies (javaScript,AngularJS,HTML) for tool-front end. Have excellent debugging skills Build knowledge of Library characterization Have strong interpersonal skills needed to coordinate deliverables and requirements from several areas within and outside of the organization. Required education Bachelor's Degree Preferred education Master's Degree Required technical and professional expertise 2-5 years years of soft ware programming experience Strong C/C++programming skills in a Unix/Linux environment are desired. VLSI knowledge, Knowledge in Standard Cell Power Modelling/ Power Domain. Great scripting skills – Perl / Python/Shell Proven problem-solving skills and the ability to work in a team environment are a must EDA tool development experience Preferred technical and professional experience Cadence, VLSI knowledge, VHDL/Verilog, computer architecture, Machine Learning/AI.

Lattice Overview There is energy here…energy you can feel crackling at any of our international locations. It’s an energy generated by enthusiasm for our work, for our teams, for our results, and for our customers. Lattice is a worldwide community of engineers, designers, and manufacturing operations specialists in partnership with world-class sales, marketing, and support teams, who are developing programmable logic solutions that are changing the industry. Our focus is on R&D, product innovation, and customer service, and to that focus, we bring total commitment and a keenly sharp competitive personality. Energy feeds on energy. If you flourish in a fast paced, results-oriented environment, if you want to achieve individual success within a “team first” organization, and if you believe you can contribute and succeed in a demanding yet collegial atmosphere, then Lattice may well be just what you’re looking for. Responsibilities & Skills There is energy here…energy you can feel crackling at any of our international locations. It’s an energy generated by enthusiasm for our work, for our teams, for our results, and for our customers. Lattice is a worldwide community of engineers, designers, and manufacturing operations specialists in partnership with world-class sales, marketing, and support teams, who are developing programmable logic solutions that are changing the industry. Our focus is on R&D, product innovation, and customer service, and to that focus, we bring total commitment and a keenly sharp competitive personality. Energy feeds on energy. If you flourish in a fast paced, results-oriented environment, if you want to achieve individual success within a “team first” organization, and if you believe you can contribute and succeed in a demanding yet collegial atmosphere, then Lattice may well be just what you’re looking for. Lattice Semiconductor is seeking a Sr. Staff Physical Design Engineer to join the HW design team focused on IP design and full chip integration. This position is an opportunity to be part of a dynamic team with ample opportunity to contribute, learn, innovate and grow. Role Specifics This is a full-time individual contributor position located in Pune, India. The qualified candidate will be implementing and lead RTL to GDSII flow for complex design. The qualified candidate will work and lead one or more aspects of physical design including place & route, CTS, routing, floorplanning, powerplanning, timing and physical signoff The qualified candidate is expected to have experience in physical design signoff checks, including timing closure, EM/RV and physical verification (DRC, LVS). The qualified candidate is expected to drive efficiency and quality of physical design flow and methodology and work together with internal EDA team and external tool vendors The qualified candidate is expected to have scripting knowledge or perl /python etc to improve design efficiency and methodology development. Collaborate with RTL, DFT , verification and full chip teams to ensure robust design implementation. The successful candidate will be open and willing to both (a) teach best-known-methods to an existing FPGA team and (b) learn from the team about the complications of highly programmable FPGA fabrics. This role carries the need to be both a strong educator and a open-minded student. Accountabilities Serve as a key contributor to FPGA design efforts. Drive physical design closure of key ASIC blocks & full chip and bring best-in-class methodologies to achieve best power, performance, and area. Ensuring design quality through all physical design quality checks and signoff. Develop strong relationships with worldwide teams. Mentor and develop strong partners and colleagues. Occasional travel as needed. Required Skills BS/MS/PhD Electronics Engineering, Electrical Engineering, Computer Science or equivalent. 12+ years of experience in driving physical design activities of ASIC blocks and full chip. Must have experience of multiple tapeouts Experience on working with industry standard physical design tools including Innovus, Genus, Tempus, voltus, calibre, conformal etc. Independent worker with demonstrated problem-solving abilities. Proven ability to work with multiple groups across different sites and time zones Lattice recognizes that employees are its greatest asset and the driving force behind success in a highly competitive, global industry. Lattice continually strives to provide a comprehensive compensation and benefits program to attract, retain, motivate, reward and celebrate the highest caliber employees in the industry. Lattice is an international, service-driven developer of innovative low cost, low power programmable design solutions. Our global workforce, some 800 strong, shares a total commitment to customer success and an unbending will to win. For more information about how our FPGA , CPLD and programmable power management devices help our customers unlock their innovation, visit www.latticesemi.com . You can also follow us via Twitter , Facebook , or RSS . At Lattice, we value the diversity of individuals, ideas, perspectives, insights and values, and what they bring to the workplace. Applications are welcome from all qualified candidates. Lattice Feel the energy.

Job Description Change the world. Love your job. Texas Instruments is seeking a Layout Engineer. In this role, you will develop and prepare multi-dimensional layouts and detailed drawings of the semiconductor devices from schematics and related geometry provided by design engineering. Work may be completed through use of CAD or other computerized equipment. You may also check dimensions, write specifications, and verify completed drawings, artwork or digitized plots. Additional job functions may involve checking design layouts and detailed drawings, referring to offline layout leveling charts for details on duties. A bachelor's degree in engineering is typically required. Strong Analog Layout fundamentals and basic Analog design knowledge. Layout Design for various analog circuits like: High Current POWER-FETS, Amplifiers, Comparators, Buffers, BG, Current Mirrors etc. Good floor planning and signal planning skills in Cadence Virtuoso XL Design area and parasitic efficient layouts. Experience in Assura LVS ,DRC verification is an advantage. Good exposure to layout XL utilities like Modgen, Wire assistant etc., Experience in BiCmos technologies is an advantage. Exposure to Digital Place and rout is an advantage. Ability to plan, track, multi-task, Prioritize work to complete the work efficiently . Scripting knowledge in Skill/Perl/Shell/Python is an advantage. Good communication, Team player skills to work with cross functional team and external stakeholders . Good technical documentation and presentations skills. Follow guidelines, processes and checklists for high-quality, on time completion of task. Qualifications Minimum requirements: Minimum education (ie bachelor's degree in electrical engineering) Minimum of 5 years of experience Preferred Qualifications Ability to establish strong relationships with key stakeholders critical to success, both internally and externally Strong verbal and written communication skills Ability to quickly ramp on new systems and processes Demonstrated strong interpersonal, analytical and problem-solving skills Ability to work in teams and collaborate effectively with people in different functions Ability to take the initiative and drive for results Strong time management skills that enable on-time project delivery About Us Why TI? Engineer your future. We empower our employees to truly own their career and development. Come collaborate with some of the smartest people in the world to shape the future of electronics. We're different by design. Diverse backgrounds and perspectives are what push innovation forward and what make TI stronger. We value each and every voice, and look forward to hearing yours. Meet the people of TI Benefits that benefit you. We offer competitive pay and benefits designed to help you and your family live your best life. Your well-being is important to us. About Texas Instruments Texas Instruments Incorporated (Nasdaq: TXN) is a global semiconductor company that designs, manufactures and sells analog and embedded processing chips for markets such as industrial, automotive, personal electronics, communications equipment and enterprise systems. At our core, we have a passion to create a better world by making electronics more affordable through semiconductors. This passion is alive today as each generation of innovation builds upon the last to make our technology more reliable, more affordable and lower power, making it possible for semiconductors to go into electronics everywhere. Learn more at TI.com . Texas Instruments is an equal opportunity employer and supports a diverse, inclusive work environment. If you are interested in this position, please apply to this requisition. About The Team TI does not make recruiting or hiring decisions based on citizenship, immigration status or national origin. However, if TI determines that information access or export control restrictions based upon applicable laws and regulations would prohibit you from working in this position without first obtaining an export license, TI expressly reserves the right not to seek such a license for you and either offer you a different position that does not require an export license or decline to move forward with your employment.

90/130/150nm and higher node with PMIC layout experience. Performs layout and takes corrective actions in such a way that the final result meets all requirements as stated in the Design document, section layout, including all remarks from review, the customer and back annotation. Performs layout in such a way that the final result meets all general layout guidelines and matches 1-to-1 with parameter devices and hierarchy used in simulations. Create floorplan Performs DRC and takes corrective actions if needed until DRC is error free Performs LVS and takes corrective actions if needed until result is successful Performs layout in such a way that final result meets the foundry layout rules. Provides extracted netlist for back annotation to DE as specified in the Design document, section layout. Translates sub block schematics to sub block layouts, taking care of the same hierarchical build-up and respecting the guidelines of the Block review document, section layout. Adds extra useful information to the Block review document, section layout.

About the Role — PCB Design Engineer Location: Gurugram Experience: 5–10 Years Qualification: B.Tech/B.E. in Electrical/Electronics/ECE or related discipline (Mandatory) Who We Are: At Boon , we’re building cutting-edge water tech solutions to make clean drinking water more sustainable, efficient, and accessible. As part of our Power Electronics team, you’ll help us develop high-performance hardware that powers next-generation water purification and distribution systems deployed globally. Role Overview: We’re looking for an experienced PCB Design Engineer with deep expertise in designing robust, high-reliability PCBs for power electronics applications. You’ll work extensively with Altium and other tools , apply EMI/EMC best practices, and handle thermal-critical layouts for power-dense systems. Key Responsibilities: Design complex, multi-layer PCBs for power electronics including DC-DC converters, inverters, SMPS, and motor drives. Develop and maintain schematic diagrams, PCB layouts, footprints, and libraries in Altium Designer. Optimize PCB layouts for signal integrity, power integrity, thermal performance, and high-current handling. Ensure compliance with EMI/EMC standards and integrate grounding, shielding, and filtering best practices. Perform DRC/ERC checks and support DFM/DFT processes for manufacturability and testability. Collaborate cross-functionally with electrical, mechanical, and firmware engineers throughout product development. Integrate 3D component models and conduct mechanical fit and clearance checks using Altium’s 3D design capabilities. Coordinate with PCB fabrication and assembly vendors for prototyping and production runs. Support prototype bring-up, debugging, and validation with the testing team. Manage documentation including Gerber files, BOMs, assembly drawings, and design revisions. What You’ll Need: Bachelor’s degree in Electronics/Electrical Engineering or a related field. 7–10 years of hands-on PCB design experience, ideally in power electronics. Advanced proficiency with Altium Designer (schematic, layout, 3D, library management). Strong understanding of EMI/EMC principles and practical implementation. Experience designing for high-voltage, high-current, and thermally demanding applications. Competency in 3D modeling and mechanical integration of PCB assemblies. Solid grasp of IPC standards and PCB manufacturing processes. Excellent analytical, problem-solving, and debugging skills. Strong communication and teamwork abilities. Join us at Boon and help shape innovative hardware that makes clean water more sustainable for millions.

Job Title: Physical Design Engineer Domain: Semiconductor | VLSI | Chip Design Experience: 7 to 15 Years Location: Bangalore / Hyderabad / Cochin / Pune Budget: ₹30 LPA to ₹75 LPA Work Mode: 5 Days Office Key Responsibilities End-to-end ownership of chip-level and block-level floor planning. Drive partitioning, placement, clock tree synthesis (CTS), and routing. Utilize tools like Cadence Innovus and Synopsys Fusion Compiler for implementation. Perform timing analysis, DRC/LVS closure, and physical verification. Collaborate with cross-functional teams including RTL, DFT, STA, and packaging teams. Key Skills Required Strong experience in chip-level and block-level physical design. Hands-on expertise with Innovus and/or Fusion Compiler. Solid understanding of timing, power, signal integrity, and physical verification. Exposure to advanced technology nodes (e.g., 7nm, 5nm) is a plus. Excellent problem-solving and debugging skills. Skills: block-level physical design,cadence innovus,semiconductor,vlsi design,problem-solving,synopsys fusion compiler,fusion compiler,power management,timing analysis,drc/lvs closure,physical verification,signal integrity,innovus,chip-level physical design,debugging,chip design,physical design

Job Title: Physical Design Engineer Domain: Semiconductor | VLSI | Chip Design Experience: 7 to 15 Years Location: Bangalore / Hyderabad / Cochin / Pune Budget: ₹30 LPA to ₹75 LPA Work Mode: 5 Days Office Key Responsibilities End-to-end ownership of chip-level and block-level floor planning. Drive partitioning, placement, clock tree synthesis (CTS), and routing. Utilize tools like Cadence Innovus and Synopsys Fusion Compiler for implementation. Perform timing analysis, DRC/LVS closure, and physical verification. Collaborate with cross-functional teams including RTL, DFT, STA, and packaging teams. Key Skills Required Strong experience in chip-level and block-level physical design. Hands-on expertise with Innovus and/or Fusion Compiler. Solid understanding of timing, power, signal integrity, and physical verification. Exposure to advanced technology nodes (e.g., 7nm, 5nm) is a plus. Excellent problem-solving and debugging skills. Skills: block-level physical design,cadence innovus,semiconductor,vlsi design,problem-solving,synopsys fusion compiler,fusion compiler,power management,timing analysis,drc/lvs closure,physical verification,signal integrity,innovus,chip-level physical design,debugging,chip design,physical design

Job Summary: We are seeking a technically strong SAP DRC (Document Reporting & Compliance) Expert with hands-on experience in SAP Public Cloud implementations. This role will focus on designing, configuring, and deploying SAP’s Document Compliance capabilities across multiple European countries, ensuring seamless integration with regulatory frameworks and Schneider’s global SAP rollout strategy. Key Responsibilities: · Lead the technical implementation of SAP Document Reporting Compliance (DRC) for electronic invoicing and statutory reporting across European countries on SAP S/4HANA Public Cloud. · Translate legal and regulatory requirements into scalable DRC technical configurations and architecture, ensuring high-performance, secure, and compliant document transmission. · Configure and extend SAP DRC using Integration Suite, SAP Business Technology Platform (BTP), Application Interface Framework (AIF), and other relevant middleware/tools. · Collaborate with SAP Global and internal solution architects to ensure alignment with Schneider’s global SAP templates and cloud design principles. · Partner with business and functional teams to assess local compliance needs and deliver tailored technical solutions without deviating from the global template. · Support end-to-end project lifecycle for DRC rollouts: blueprinting, prototyping, testing (SIT/UAT), cutover, go-live, and hyper care. · Monitor document flows and system logs, troubleshoot DRC-related issues, and implement performance improvements and bug fixes. · Maintain documentation of DRC configurations, interfaces, and exception handling scenarios in line with IT compliance policies. · Engage in proactive collaboration with SAP Product Support and external partners for issue resolution, legal updates, and roadmap alignment. Technical Skills & Experience: · 3+ years of hands-on experience with SAP DRC configuration and technical setup , including electronic invoicing frameworks in Europe (e.g., SdI, Chorus Pro, KSeF) and Overall 6+ Years of experience. · Strong technical knowledge of SAP S/4HANA Public Cloud architecture and SAP Integration Suite (Cloud Integration/CPI) or SAP BTP. · Proficient in data mapping, XML/UBL formats, API management, and outbound e-document frameworks. · Familiarity with SAP BTP, AIF, and IDoc/EDI processing in a cloud context. · Experience implementing DRC as part of global rollout projects in large enterprise environments. · Understanding of European legal requirements for e-invoicing, digital signatures, and real-time reporting.

floor planning, bump planning, routing, power grid design, clock design, optimization for high-speed digital circuits high-speed digital layouts, DDR and other high-speed interfaces EDA tools for chip-level physical verification (DRC, LVS, ERC) Accessible workspace Food allowance Health insurance Annual bonus Provident fund

Job Title: Physical Design Engineer Company: Wipro Domain: Semiconductor | VLSI | Chip Design Experience: 7 to 15 Years Location: Bangalore / Hyderabad / Cochin / Pune Budget: ₹30 LPA to ₹75 LPA Work Mode: 5 Days Office Key Responsibilities: End-to-end ownership of chip-level and block-level floor planning . Drive partitioning, placement, clock tree synthesis (CTS), and routing. Utilize tools like Cadence Innovus and Synopsys Fusion Compiler for implementation. Perform timing analysis , DRC/LVS closure , and physical verification. Collaborate with cross-functional teams including RTL, DFT, STA, and packaging teams. Key Skills Required: Strong experience in chip-level and block-level physical design . Hands-on expertise with Innovus and/or Fusion Compiler . Solid understanding of timing, power, signal integrity, and physical verification. Exposure to advanced technology nodes (e.g., 7nm, 5nm) is a plus. Excellent problem-solving and debugging skills. Interview Process: L1 Technical Round – Virtual L2 Final Round – Virtual Job Types: Full-time, Permanent Pay: ₹3,000,000.00 - ₹7,500,000.00 per year Schedule: Monday to Friday Ability to commute/relocate: Pune, Maharashtra: Reliably commute or planning to relocate before starting work (Preferred) Application Question(s): End-to-end ownership of chip-level and block-level floor planning? Utilize tools like Cadence Innovus and Synopsys Fusion Compiler for implementation? Perform timing analysis, DRC/LVS closure, and physical verification? Work Location: In person

Urgent Hiring for Sr. Accountant who have zeal to work in Head Office. ⚫ Expertise in TALLY.ERP9 and TALLY PRIME Payable, Accounts Receivable, GST reconciliation, Ledger and Inventory Modules. ⚫ Expertise in preparing of weekly Bank, Cash ⚫ Expertise in Audit preparation of yearly financials auditors for auditing purpose ⚫ Strong in interaction with Auditors for Finalization ⚫ Experienced in preparation of MIS Report ⚫ Experienced in controlling Debtors & Creditors Outstanding list and reporting to Management. ⚫ Expertise in dealing with banks for issue other various issues ⚫ Expertise in Preparation and Return GST DRC 03 file & payment. ⚫ EWAY bill generation from tally prime & GST ⚫ Knowledge of RCM (reverse charge Mechanism). Contact Number - 9599379848 Job Type: Full-time Pay: ₹25,000.00 - ₹35,000.00 per month Schedule: Day shift Work Location: In person

Urgent Hiring for Sr. Accountant who have zeal to work for Manufacturing plant. ⚫ Expertise in TALLY.ERP9 and TALLY PRIME Payable, Accounts Receivable, GST reconciliation, Ledger and Inventory Modules. ⚫ Expertise in preparing of weekly Bank, Cash ⚫ Expertise in Audit preparation of yearly financials auditors for auditing purpose ⚫ Strong in interaction with Auditors for Finalization ⚫ Experienced in preparation of MIS Report ⚫ Experienced in controlling Debtors & Creditors Outstanding list and reporting to Management. ⚫ Expertise in dealing with banks for issue other various issues ⚫ Expertise in Preparation and Return GST DRC 03 file & payment. ⚫ EWAY bill generation from tally prime & GST ⚫ Knowledge of RCM (reverse charge Mechanism). Contact Number - 9599379848 Job Type: Full-time Pay: ₹25,000.00 - ₹35,000.00 per month Schedule: Day shift Work Location: In person

Your Job The PCB Designer will be responsible for creating and optimizing PCB layouts, ensuring high-quality design for manufacturability, reliability, and performance. This position requires strong knowledge of PCB design principles, proficiency in design software, and a collaborative approach to work effectively with cross-functional teams, including hardware, firmware, signal integrity, and manufacturing. Our Team The PCB Design Engineering Team at Koch Industries is a talented and innovative group dedicated to developing state-of-the-art hardware solutions. We work collaboratively across disciplines to design, prototype, and test high-quality hardware components that support our company's growth and technological advancements. Join us to be part of a dynamic team that values creativity, excellence, and teamwork. What You Will Do Execute PCB layout design for analog, digital, and mixed-signal boards using tools such as Altium Designer & Cadence Allegro. Work closely with electrical engineers to interpret schematics and translate design intent into accurate layouts. Handle multi-layer, high-density, fine-pitch components, impedance-controlled traces, and thermal management zones. Ensure optimal placement, routing, via management, and adherence to signal integrity and power delivery constraints. DFM/DFMA Integration: Apply DFM principles to ensure that PCB designs are optimized for fabrication, assembly, testing, and repair. Incorporate design constraints like spacing rules, via types, material constraints, and component clearances to support high-yield manufacturing. Understand and implement DFMA guidelines, such as reducing component count, orientation consistency, and minimizing manual handling in assembly lines. Run DRC, ERC, and DFM checks and validate outputs using tools like Valor NPI, CAM350, or equivalent. Prepare complete fabrication and assembly documentation (Gerber/ODB++, assembly drawings, fab notes, pick-and-place files, stack-ups, etc.). Participate in design reviews with internal stakeholders and external manufacturing partners. Support prototyping and production builds, and assist in resolving design or manufacturing-related issues. Cross-Functional Collaboration: Work closely with hardware engineers, SI/PI engineers, mechanical teams, and EMS vendors to ensure successful design-to-production transition. Provide input on component selection and library creation, ensuring part footprints follow IPC standards and are fabrication-friendly. Process & Quality: Maintain and adhere to internal design guidelines and checklist reviews to ensure high design quality. Document and improve PCB design processes and share learnings with peers and new joiners. High-Speed & Power Electronics Design: Work on high-speed interfaces (PCIe, DDR, USB, Ethernet, etc.). Design power distribution networks (PDN), LDOs, DC-DC converters, and ensure efficient power delivery. Schematic & PCB Reviews: Conduct peer design reviews and cross-functional collaboration with electrical, mechanical, and SI/PI teams. Perform SI/PI analysis, power plane optimization, and constraint management. Who You Are (Basic Qualifications) BE/B Tech in Electrical/Electronic & Communication Engineering 4 to 8 years of demonstrable experience as a PCB Design engineer. Education: Bachelor’s degree in Electronics Engineering, Electrical Engineering, or a related field (or equivalent experience). Experience: Minimum of 4-8 years of experience in PCB design, preferably with high-speed and/or complex multilayer boards and DFM/DFMA What Will Put You Ahead Strong attention to detail and commitment to delivering high-quality designs. Effective communication skills to work with cross-functional teams and present design considerations. Problem-solving skills and adaptability to new tools and design challenges Who We Are Molex is a subsidiary of Koch Industries, an MNC and industry leader in electronic solutions. We support a wide range of industries like data communications, consumer electronics, industrial, automotive, medical etc. Our presence is in 223 locations across 40 countries. We have a portfolio of 100,000 electronic products and a dedicated R&D facility driving technological innovation in Bangalore. We make a connected world possible to enable technology that transforms the future. Global Engineering Service (GES) a business unit of Molex, develops innovative products and manufacturing processes around automotive in-vehicle networking, infotainment, Medical and lighting segments. You may not see our name on the shelves, but our electronic solutions are inside the products you use every day. We work together with the world’s innovators to design and manufacture electronic solutions that solve complex technical challenges. At Molex, we not only employ some of the most talented people from all over the world, we work to help cultivate tomorrow's For further breakthroughs. From our corporate headquarters in Lisle, IL to manufacturing floors around the world, the Molex team is dedicated to helping further the limits of technology.

Chitkara University is Looking for Assistant Professor Research - Doctoral Research Centre. Job Description DRC deals in guiding and evaluating the progress of PhD students from the development of research proposal to the submission of final PhD thesis. DRC members are responsible for taking PhD coursework classes such as Research Methodology course, Advanced Research Methodology course, Research and Publication Ethics, etc. Apart from this, members are responsible for writing research projects, organizing research methodology workshops (using software's such as SPSS, AMOS, and Bibliometric analysis Vos viewer software, etc.) conferences, and publishing in leading high impact journals. Desired Skills Required Supervise Ph.D. Students for the executive doctoral programs. Teach Ph.D. coursework classes. Publish in scholarly journals and generate other IPs such as patents. Organize research-oriented events Research and Perks Research guiding allowance: You will be a financial stakeholder in every Ph.D. student you guide, as per the prevailing norm. Consultancy allowance: You are allowed to retain 90% of the share you earn on each consultancy project you take up. Academic allowance: After completion of a year of service with the University, you may be chosen for getting the required allowances to attend flagship international conferences in India and abroad, as per the prevailing norms. You are entitled to access on-line journals and publication databases to help you remain updated. You are entitled to receive Seed Fund to initiate any start-up, in case you wish so. You will be also sponsored with the entire fee required to lodge your patents. Education Qualification- Ph.D. in Finance, Marketing, Human Resource (Required) Interested candidates can mail their resume mentioning DRC-25 in the subject line at akriti.sharma@chitkara.edu.in

Job Title - Platforms Consultant Level - Consultant - S&C GN-CFO&EV Management Level: 09 – Consultant Location: Gurgaon, Mumbai, Bangalore, Pune, Hyderabad Must have skills: SAP FICO Implementation Good to have skills: Generic FICO, PS + Investment mgt, DRC, FSCM, CO, VIM+FI, OCR, Functional MDG, AFC/FCC, SAP ICMR, Intercompany, SAP CFIN Job Summary: Have been part of at least 3 end to end SAP implementations. Out of which 1 in S4 Understand the SAP roadmap for S/4 HANA and become a trusted advisor for clients in driving their S/4 HANA adoption. Have experience in defining a Business Case for S4 Transformation and RoI calculations. Have worked in the capacity of Solution Architect / Design Authority in Past and have done lot of advisory work for ERP’s for e.g. Product selection, Value realization, Fit Gap Assessment etc. Work closely with clients to understand their issues, define IT strategies, architecture solutions, win buy-in for your recommendations. Drive sales pipeline and independently own proposals related to Finance / Multi-function S/4 HANA engagements. Lead and transform the consulting industry by developing some key Assets and Accelerators which can help Clients in their digital transformation journey. Provide direction for complex SAP S/4 HANA issues, and can collaborate with the business and developers and execute on agreed timelines. Provide consulting solutions including how to leverage standard SAP S/4 HANA functionality and how to enable requirements while maximizing the ROI Lead intelligent conversations to guide clients through best-practice project scoping and delivery to ensure overall project success in implementing SAP S/4 HANA Have ability to manage project execution and manage client conversations during assessment, design, implementation, and status reporting Lead the problem solution design and implementation ensuring high quality adhering to the timelines and defined budget Supervision of Accenture Managers, Senior and Junior analysts and consultants and client personnel to drive delivery outcomes. Roles & Responsibilities: Should know how to lead and deliver S/4 HANA engagements across different implementation approaches including excellent understanding of client business processes, pain points, S/4 HANA solution options and organization structure Should know how to drive and build sales pipeline including BDs and Proposals Should be aware of digital finance technologies that drives business processes Should know how to lead business case creation for SAP design to implementation projects Drive continuous improvement capability with regards to methodology, tools, practices and maturity Professional & Technical Skills: MBA from a Tier-1 or Tier-2 B-school. CA or CPA 4-7 years of work experience preferably with at least three of the following: 1+ years’ experience of working on S4HANA 2+ years’ experience of working on SAP FICO 4+years’ experience in Finance Technology relevant projects At least one end-to-end implementation experience At least 2 years of consulting experience in a big4 or similar firms Process Expertise in Finance, accounting, treasury or tax operations. Finance business process knowledge related to Organization Structure, Master Data, Accounts Payable, Accounts Receivable, Asset Accounting, General Ledger, Chart of Accounts, Taxation, Treasury, etc. Experience in SAP Reporting capabilities in BI/BO, BW, SAC, etc. Understanding of SAP and Allied Systems’ Reporting and Customization capabilities Understanding of Fiori and Dashboard development capabilities in SAP Core ERP and Allied Systems Deep knowledge and experience in SAP System Integration projects, namely, SAP ECC and S/4HANA Finance modules / applications Drawing on extensive knowledge and experience across SAP System Integration projects to be able to deliver projects on design and implementation Proactive interest or certification in technologies other than SAP (Data science, blockchain, blackline, big data etc) would be added advantage Supervision of Accenture analysts and client personnel in limited capacity Ability to work independently with minimal supervision Additional Information: An opportunity to work on transformative projects with key G2000 clients Potential to Co-create with leaders in strategy, industry experts, enterprise function practitioners and, business intelligence professionals to shape and recommend innovative solutions that leverage emerging technologies. Ability to embed responsible business into everything—from how you service your clients to how you operate as a responsible professional. Personalized training modules to develop your strategy & consulting acumen to grow your skills, industry knowledge and capabilities Opportunity to thrive in a culture that is committed to accelerate equality for all. Engage in boundaryless collaboration across the entire organization. About Our Company | Accenture Experience: 4 - 7 years Educational Qualification: MBA(Finance) or CA or CMA

Job Title - Platforms Consultant Level - Consultant - S&C GN-CFO&EV Management Level: 09 – Consultant Location: Gurgaon, Mumbai, Bangalore, Pune, Hyderabad Must have skills: SAP FICO Implementation Good to have skills: Generic FICO, PS + Investment mgt, DRC, FSCM, CO, VIM+FI, OCR, Functional MDG, AFC/FCC, SAP ICMR, Intercompany, SAP CFIN Job Summary: Have been part of at least 3 end to end SAP implementations. Out of which 1 in S4 Understand the SAP roadmap for S/4 HANA and become a trusted advisor for clients in driving their S/4 HANA adoption. Have experience in defining a Business Case for S4 Transformation and RoI calculations. Have worked in the capacity of Solution Architect / Design Authority in Past and have done lot of advisory work for ERP’s for e.g. Product selection, Value realization, Fit Gap Assessment etc. Work closely with clients to understand their issues, define IT strategies, architecture solutions, win buy-in for your recommendations. Drive sales pipeline and independently own proposals related to Finance / Multi-function S/4 HANA engagements. Lead and transform the consulting industry by developing some key Assets and Accelerators which can help Clients in their digital transformation journey. Provide direction for complex SAP S/4 HANA issues, and can collaborate with the business and developers and execute on agreed timelines. Provide consulting solutions including how to leverage standard SAP S/4 HANA functionality and how to enable requirements while maximizing the ROI Lead intelligent conversations to guide clients through best-practice project scoping and delivery to ensure overall project success in implementing SAP S/4 HANA Have ability to manage project execution and manage client conversations during assessment, design, implementation, and status reporting Lead the problem solution design and implementation ensuring high quality adhering to the timelines and defined budget Supervision of Accenture Managers, Senior and Junior analysts and consultants and client personnel to drive delivery outcomes. Roles & Responsibilities: Should know how to lead and deliver S/4 HANA engagements across different implementation approaches including excellent understanding of client business processes, pain points, S/4 HANA solution options and organization structure Should know how to drive and build sales pipeline including BDs and Proposals Should be aware of digital finance technologies that drives business processes Should know how to lead business case creation for SAP design to implementation projects Drive continuous improvement capability with regards to methodology, tools, practices and maturity Professional & Technical Skills: MBA from a Tier-1 or Tier-2 B-school. CA or CPA 4-7 years of work experience preferably with at least three of the following: 1+ years’ experience of working on S4HANA 2+ years’ experience of working on SAP FICO 4+years’ experience in Finance Technology relevant projects At least one end-to-end implementation experience At least 2 years of consulting experience in a big4 or similar firms Process Expertise in Finance, accounting, treasury or tax operations. Finance business process knowledge related to Organization Structure, Master Data, Accounts Payable, Accounts Receivable, Asset Accounting, General Ledger, Chart of Accounts, Taxation, Treasury, etc. Experience in SAP Reporting capabilities in BI/BO, BW, SAC, etc. Understanding of SAP and Allied Systems’ Reporting and Customization capabilities Understanding of Fiori and Dashboard development capabilities in SAP Core ERP and Allied Systems Deep knowledge and experience in SAP System Integration projects, namely, SAP ECC and S/4HANA Finance modules / applications Drawing on extensive knowledge and experience across SAP System Integration projects to be able to deliver projects on design and implementation Proactive interest or certification in technologies other than SAP (Data science, blockchain, blackline, big data etc) would be added advantage Supervision of Accenture analysts and client personnel in limited capacity Ability to work independently with minimal supervision Additional Information: An opportunity to work on transformative projects with key G2000 clients Potential to Co-create with leaders in strategy, industry experts, enterprise function practitioners and, business intelligence professionals to shape and recommend innovative solutions that leverage emerging technologies. Ability to embed responsible business into everything—from how you service your clients to how you operate as a responsible professional. Personalized training modules to develop your strategy & consulting acumen to grow your skills, industry knowledge and capabilities Opportunity to thrive in a culture that is committed to accelerate equality for all. Engage in boundaryless collaboration across the entire organization. About Our Company | Accenture Experience: 4 - 7 years Educational Qualification: MBA(Finance) or CA or CMA

Job Description : Hands on experience in Block level PnR convergence with Synopsys ICC2/Cadence Innovus and timing convergence in PTSI/Tempus In this position, candidate is expected to lead all block/chip level PD activities including floor plans, placement, CTS, optimization and routing techniques, RC extraction, STA, EM/IR DROP, PV Familiar with deep sub-micron designs below 10nm preferred BE/B Tech/ME/M TECH

Lead and manage the analog and RF layout team for high-performance semiconductor products Oversee layout planning, floorplanning, and routing for RF, analog, and mixed-signal IC designs. Work closely with circuit design teams to optimize layouts for performance, area, and manufacturability. Ensure DFM (Design for Manufacturability), DRC (Design Rule Check), LVS (Layout vs. Schematic), and EM (Electromigration) compliance. Drive automation and layout methodologies to improve efficiency and quality. Collaborate with foundry partners for process design kits (PDKs), layout guidelines, and tape-out requirements. Provide technical mentorship to layout engineers and review critical blocks. Own full-chip layout integration and support post-layout simulations. Qualifications: 8+ years of experience in analog/mixed-signal/RF IC layout. Strong expertise in FinFET (e.g., 16nm, 7nm, 5nm) or advanced CMOS nodes. Hands-on experience with Cadence Virtuoso, Calibre DRC/LVS, and Mentor Graphics tools. Knowledge of high-frequency layout techniques, parasitic-aware layout design, and shielding strategies. Experience in power management, high-speed SerDes, RF front-ends, or ADC/DAC layouts is a plus. Proven ability to lead teams, review layouts, and drive tape-out schedules. Strong understanding of wafer-level packaging and chip integration. Excellent problem-solving and communication skills.

Job Title - Platforms Consultant Level - Consultant - S&C GN-CFO&EV Management Level: 09 – Consultant Location: Gurgaon, Mumbai, Bangalore, Pune, Hyderabad Must have skills: SAP FICO Implementation Good to have skills: Generic FICO, PS + Investment mgt, DRC, FSCM, CO, VIM+FI, OCR, Functional MDG, AFC/FCC, SAP ICMR, Intercompany, SAP CFIN Job Summary: Have been part of at least 3 end to end SAP implementations. Out of which 1 in S4 Understand the SAP roadmap for S/4 HANA and become a trusted advisor for clients in driving their S/4 HANA adoption. Have experience in defining a Business Case for S4 Transformation and RoI calculations. Have worked in the capacity of Solution Architect / Design Authority in Past and have done lot of advisory work for ERP’s for e.g. Product selection, Value realization, Fit Gap Assessment etc. Work closely with clients to understand their issues, define IT strategies, architecture solutions, win buy-in for your recommendations. Drive sales pipeline and independently own proposals related to Finance / Multi-function S/4 HANA engagements. Lead and transform the consulting industry by developing some key Assets and Accelerators which can help Clients in their digital transformation journey. Provide direction for complex SAP S/4 HANA issues, and can collaborate with the business and developers and execute on agreed timelines. Provide consulting solutions including how to leverage standard SAP S/4 HANA functionality and how to enable requirements while maximizing the ROI Lead intelligent conversations to guide clients through best-practice project scoping and delivery to ensure overall project success in implementing SAP S/4 HANA Have ability to manage project execution and manage client conversations during assessment, design, implementation, and status reporting Lead the problem solution design and implementation ensuring high quality adhering to the timelines and defined budget Supervision of Accenture Managers, Senior and Junior analysts and consultants and client personnel to drive delivery outcomes. Roles & Responsibilities: Should know how to lead and deliver S/4 HANA engagements across different implementation approaches including excellent understanding of client business processes, pain points, S/4 HANA solution options and organization structure Should know how to drive and build sales pipeline including BDs and Proposals Should be aware of digital finance technologies that drives business processes Should know how to lead business case creation for SAP design to implementation projects Drive continuous improvement capability with regards to methodology, tools, practices and maturity Professional & Technical Skills: MBA from a Tier-1 or Tier-2 B-school. CA or CPA 4-7 years of work experience preferably with at least three of the following: 1+ years’ experience of working on S4HANA 2+ years’ experience of working on SAP FICO 4+years’ experience in Finance Technology relevant projects At least one end-to-end implementation experience At least 2 years of consulting experience in a big4 or similar firms Process Expertise in Finance, accounting, treasury or tax operations. Finance business process knowledge related to Organization Structure, Master Data, Accounts Payable, Accounts Receivable, Asset Accounting, General Ledger, Chart of Accounts, Taxation, Treasury, etc. Experience in SAP Reporting capabilities in BI/BO, BW, SAC, etc. Understanding of SAP and Allied Systems’ Reporting and Customization capabilities Understanding of Fiori and Dashboard development capabilities in SAP Core ERP and Allied Systems Deep knowledge and experience in SAP System Integration projects, namely, SAP ECC and S/4HANA Finance modules / applications Drawing on extensive knowledge and experience across SAP System Integration projects to be able to deliver projects on design and implementation Proactive interest or certification in technologies other than SAP (Data science, blockchain, blackline, big data etc) would be added advantage Supervision of Accenture analysts and client personnel in limited capacity Ability to work independently with minimal supervision Additional Information: An opportunity to work on transformative projects with key G2000 clients Potential to Co-create with leaders in strategy, industry experts, enterprise function practitioners and, business intelligence professionals to shape and recommend innovative solutions that leverage emerging technologies. Ability to embed responsible business into everything—from how you service your clients to how you operate as a responsible professional. Personalized training modules to develop your strategy & consulting acumen to grow your skills, industry knowledge and capabilities Opportunity to thrive in a culture that is committed to accelerate equality for all. Engage in boundaryless collaboration across the entire organization. About Our Company | Accenture Experience: 4 - 7 years Educational Qualification: MBA(Finance) or CA or CMA

Artelia Consulting Engineers Limited (ACE) is based in Chennai, India and is subsidiary company of ARTELIA GROUP, focusing on Engineering, Project Advisory, Infrastructure Consulting and Sustainability Advisory services across sectors and geographies. ACE projects spread across India, neighbouring countries of India, GCC countries, and Africa. Today, ACE competes with leading players in the industry, and its assignments have grown, spreading across more than 25 Indian States and also in countries like Cameroon, Senegal, DRC, Madagascar, Mali, Rwanda, Tanzania, Liberia, Ghana, Malawi, Ethiopia, Nigeria, Namibia, South Africa, Zambia, Zimbabwe, Mozambique, Angola, Uganda, Kenya, Eswatini, Mauritius, Bangladesh, Nepal, Bhutan, Qatar, Oman and Saudi Arabia. ACE has positioned itself as Knowledge hub blended with a strong underlay of social inclusion, capacity building and smart, sustainable solutions. Job Role: Water and Wastewater Engineer Location: Chennai Experience Required: Minimum 5 to 10 years Education: B.E./B.Tech in Civil / Environmental Engineering M.E./M.Tech in Environmental Engineering or related field (preferred) Job Summary: Required a skilled and experienced Water and Wastewater Engineer to lead the planning, design, and execution of infrastructure projects related to water supply, sewerage, and wastewater treatment. Should bring strong technical expertise, leadership capabilities, and a proven track record in successfully delivering complex water and wastewater projects. This role requires close coordination with multidisciplinary teams, clients, consultants, and contractors. Certifications (Preferred but not Mandatory): PMP or equivalent project management certification ISO 9001/14001 awareness or training Safety certifications (e.g., OSHA) Note: Combination of office-based and site-based work depending on project phase. Willingness to travel for site visits, meetings, and supervision activities Key Roles and Responsibilities: Lead end-to-end execution of water and wastewater projects, including feasibility studies, detailed design, tendering, and construction supervision. Manage project schedules, budgets, and quality objectives. Serve as the primary technical point of contact for clients and stakeholders. Prepare and review designs, drawings, BOQs, technical specifications, and reports for water supply networks, sewerage systems, pumping stations, and treatment plants (WTP/WWTP/STP/ETP). Ensure compliance with national/international codes and standards. Liaise with government agencies, utility providers, and local authorities for project approvals and permissions. Coordinate with internal teams including structural, electrical, mechanical, and process engineers. Oversee construction activities to ensure adherence to design, specifications, and quality standards. Resolve site issues and provide technical guidance to contractors and junior engineers. Prepare progress reports, compliance documents, and as-built documentation. Assist in proposal writing and technical bid preparation when required. In-depth knowledge of water supply and wastewater treatment processes, hydraulics, and infrastructure design. Proficiency in software such as AutoCAD, WaterGEMS, SewerGEMS, EPANET, or similar hydraulic modeling tools. Strong project management and leadership skills. Excellent communication, coordination, and documentation abilities. Familiarity with environmental regulations and permitting processes. Ability to manage multiple projects and work in a fast-paced environment. Looking for an immediate joiner. Interested candidates kindly mention the position and share your resume to No calls (Only WhatsApp No:9840701512) Job Types: Full-time, Permanent Schedule: Day shift Work Location: In person Application Deadline: 04/07/2025 Expected Start Date: 07/07/2025

Must have experience in working with MNC clients Must be good at Honouring Committed Schedules, Quality delivery, Clarity in Communication Familiarity with Serdes components like serializer or de-serializer circuits Strong fundamentals and knowledge of AMS design flow Must have familiarity with layout issues, working with layout team to fix them Must be good at preparing the Review PPT, run through the review meeting and closing all action items Must ensure the design meets PPA goals Good at debugging to ensure meeting all performance simulation issues Must be able to pass QA checks as demanded by the client Must be able to generate all relevant design views using sign-off tools Qualification BE/BTech from any reputed University Masters Preferred Experience Between 3 to 10 years Hands on with any of the spice simulators (Hspice/ Spectre)