DFT Engineers Modernize Chip Solutions (MCS)

5.0 - 9.0 years

0 Lacs

karnataka

On-site

Role Overview: As a DFT Engineer at our company in Bangalore, you will be responsible for various aspects related to Design for Test (DFT) in ASIC projects. Your expertise in MBIST, Scan Insertion, DRC analysis & resolution, ATPG, and simulations will be crucial in ensuring the effectiveness of the testing processes. Key Responsibilities: - Execute MBIST, Scan Insertion, DRC analysis & resolution, ATPG, and simulations for ASICs. - Work on IOBIST (SerDes verification) and BIST sequence simulations for ASICs. - Implement test coverage improvement strategies and hierarchical test methodologies. - Utilize proven debugging skills to address issues within complex designs. - Utilize Synopsys DFT t...

Posted 1 month ago

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Physical Design Engineer Intel Corporation

6.0 - 9.0 years

0 Lacs

bengaluru, karnataka, india

On-site

Job Details Job Description: As an IP Structural/Physical Design Engineer, you will be working alongside Elite IP and SoC design teams to deliver next-generation Xeon products and related IPs for Server markets. We are looking for candidates with experience as physical design engineers as part of the Structural Design Expert Team in the IP organization. You will be fluent in all aspects of IP physical design flow from high-level block design to synthesis, place and route and timing and power convergence to build a design database that is ready for manufacturing. Your responsibilities will include all aspects of RTL2GDSII physical design flow convergence including but not be limited to: Overs...

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Principal Engineer Infineon Technologies

12.0 - 14.0 years

0 Lacs

bengaluru, karnataka, india

On-site

Expert in implementing Scan insertion, LPCT, LBIST, Hybrid-TK, Compression Logic and DRC analysis of implemented Testability logic structures. In your new role you will: Responsible for SoC DFT Architecture definition/implementation/verification/silicon debug of SoC/Full Chip. Need to implement Scan insertion, LPCT, LBIST, Hybrid-TK, Compression Logic and DRC analysis of implemented Testability logic structures. Responsible for ATPG, DRC analysis, Test coverage debug, Memory BIST implementation and verification. Owner ship of JTAG/BSCAN/iJTAG, P1500 implementation and verification, Stuck-at/TDF/Bridging/Cell-aware/iddq fault models. Good debug skills in ZERO delay and SDF based scan/MBIST/JT...

Posted 2 months ago

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HW Design_DFT Zilogic Systems

3.0 - 7.0 years

0 Lacs

karnataka

On-site

The ideal candidate for this role should possess a strong understanding of Design for Testability (DFT) concepts and have hands-on experience in DFT implementation and Extraction. You should have expertise in ATPG (Automatic Test Pattern Generation) and DRC (Design Rule Check) analysis. Proficiency in Coverage Analysis for SAF/TDF is essential for this position. Additionally, you should be adept at conducting simulations with and without timing, along with independent debugging capabilities. Experience in post-silicon support and debugging on ATE (Automated Test Equipment) is highly desirable. A positive attitude and the ability to work effectively as part of a team are important qualities w...

Posted 3 months ago

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