Senior Design Verification Engineer ACL Digital

4.0 - 6.0 years

0 Lacs

hyderabad, telangana, india

On-site

Job Location: Hyderabad Notice Period: 15 days to 30 Days Minimum: 4 Years Key Responsibilities: Developing test plans Coding and bring up of asm, c++ tests UVM test bench components coding and maintaining Debugging regression fails Protocol: DDR,PCIE,USB,MIPI Preferred Experience: Should have worked on Processor based System or Sub-system level verification Hands on experience with assembly, UVM, SV, C++ Experience in developing complex test bench/model in UVM, Verilog, System Verilog Hands on experience in developing test plans, coverage closure Ability to code readable, maintainable and verifiable code using UVM, SV, Strong digital design concepts Experience in developing asm/C++ tests wi...

Posted 1 month ago

AI Match Score

Apply

PCIE Verification Engineer ACL Digital

4.0 - 8.0 years

0 Lacs

hyderabad, telangana

On-site

The job is based in Bangalore/Hyderabad and requires a notice period of 15 to 30 Days with a minimum experience of 4 Years. As a candidate, your key responsibilities will include developing test plans, coding and bringing up asm, c++ tests, coding and maintaining UVM test bench components, debugging regression fails, and working with protocols such as DDR, PCIE, USB, MIPI, and PCIE. The ideal candidate should have experience working on Processor based Systems or Sub-system level verification. It is preferred that you have hands-on experience with assembly, UVM, SV, C++, and have worked on developing complex test bench/models in UVM, Verilog, and System Verilog. Additionally, you should have ...

Posted 3 months ago

AI Match Score

Apply

Start Your Job Search Today

Browse through a variety of job opportunities tailored to your skills and preferences. Filter by location, experience, salary, and more to find your perfect fit.