4.0 - 8.0 years

0 Lacs

hyderabad, telangana

On-site

The job is based in Bangalore/Hyderabad and requires a notice period of 15 to 30 Days with a minimum experience of 4 Years. As a candidate, your key responsibilities will include developing test plans, coding and bringing up asm, c++ tests, coding and maintaining UVM test bench components, debugging regression fails, and working with protocols such as DDR, PCIE, USB, MIPI, and PCIE. The ideal candidate should have experience working on Processor based Systems or Sub-system level verification. It is preferred that you have hands-on experience with assembly, UVM, SV, C++, and have worked on developing complex test bench/models in UVM, Verilog, and System Verilog. Additionally, you should have experience in developing test plans, achieving coverage closure, and coding readable, maintainable, and verifiable code using UVM, SV, with a strong understanding of digital design concepts. Any experience in developing asm/C++ tests, Power Management, Clock, Reset, or knowledge of DPI Interface, Ruby/Perl script programming skills will be considered an added advantage for this role. If you meet these qualifications and are interested in this position, please reach out to himabindu.jeevarathnam@acldigital.com for further details or referrals.,

Posted 1 week ago

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