7.0 - 11.0 years

0 Lacs

karnataka

On-site

You should be well versed with timing closure (STA) and timing closure methodologies, along with the ability to develop pre/post-layout constraints for timing closure. You will be required to collaborate with the design team to establish functional/DFT constraints and integrate IP level constraints. Additionally, you should have experience in defining multi-voltage/switching aware corner definitions, selecting RC/C models, and possessing expertise in abstraction techniques such as Hyperscale/ILM/ETM. In this role, you will be responsible for conducting RC balancing and scaling analysis of full chip clocks as well as critical data paths. Proficiency in automation using PERL, TCL, and EDA tool-specific scripting is essential. You should also have experience in DMSA at full chip level and developing custom scripts for timing fixes. As for qualifications, a BE/BTECH/MTECH in EE/ECE with proven experience in ASIC Physical Design is required. Detailed knowledge of EDA tools and flows, specifically Tempus/Primetime, is a must-have. The ideal candidate should have a minimum of 7 years of relevant experience in the field.,

Posted 1 month ago

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Synthesis/STA Semicon TechnoLabs

3.0 - 12.0 years

0 Lacs

karnataka

On-site

You will be joining a leading training institute in the semiconductor industry that is constantly seeking dedicated individuals who are enthusiastic about achieving excellence and eager to expand their knowledge. Our work environment is dynamic, fostering innovation and creativity, and we provide avenues for personal and professional growth through training programs, mentorship, and coaching. The position available is for Synthesis/STA in either Bengaluru or Noida with a requirement of 3-12 years of experience and a BTECH/MTECH qualification. Key Responsibilities: - Demonstrated proficiency in timing concepts and the ability to independently close timing of Block/SoC. - Hands-on experience in generating constraints. - Proficiency in Logical synthesis tools such as Design compiler/ Rc compiler. - Familiarity with Formal Verification and comfortable using LEC/formality tools. - Ability to generate and implement functional Ecos. - Experience in Pre-layout and Post layout timing analysis using industry standard tools like Primetime/ETS. - Hands-on experience in crosstalk timing closure. - Understanding of Path based analysis, AOCV, DMSA is advantageous. - Knowledge of the complete physical Design flow is considered a plus. If you are a self-driven, innovative individual with a strong commitment to excellence, we encourage you to submit your resume and cover letter to our HR department. Be part of our dedicated team of professionals and contribute to the advancement of the semiconductor industry.,

Posted 2 months ago

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Principal STA / Synthesis Engineer Mulya Consulting

10.0 - 20.0 years

100 - 150 Lacs

Hyderabad

Hybrid

Principal STA / Synthesis Engineer Hyderabad Founded by highly respected Silicon Valley veterans - with its design centers established in Santa Clara, California. / Hyderabad/ Bangalore A US based well-funded product-based startup looking for Highly talented Engineers for the following roles. Constraint development Constraint management Constraint validation Chip top level synthesis, sta and Timing Closure. RTL2GDS flow. Ability to handle synthesis,sta, lec, upf flow methodologies. TCL/perl/python scripting. Candidate with 12-17 yrs exp in Synthesis / STA role Experience in handling complex data path-oriented multi-million gate synthesis Working Knowledge of Physical synthesis using tools like Genus, Design Compiler Experience in debugging for multi-clock domains hierarchical/flat timing analysis. Hands-on experience in LEC along with strong debugging skills for resolving issues/aborts. Netlist and constraint sign in checks and validation. Prime time constraint development at full chip level and clean up. Multimode multi corner timing knowledge and timing closure at block/top level using tools like DMSA Excellent debugging skills in timing convergence issues and ability to come up with creative solutions . Technical leadership and ability to mentor and make the team deliver. Contact: Uday Mulya Technologies muday_bhaskar@yahoo.com "Mining The Knowledge Community"

Posted 3 months ago

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