689 Digital Design Jobs - Page 16

We are seeking a highly skilled and experienced Staff Engineer for Functional Modeling & Verification to join our innovative team in Bengaluru, India. As a Staff Engineer, you will play a crucial role in shaping our technical direction, leading complex projects, and mentoring junior engineers. Lead architectural decisions and provide technical guidance to cross-functional teams Collaborate with product managers and other stakeholders to define technical requirements and solutions Conduct code reviews and ensure code quality across projects Mentor and guide junior engineers, fostering their professional growth Identify and resolve complex technical issues across multiple projects Stay current with emerging technologies and industry trends, recommending innovations to improve our tech stack Contribute to the development of engineering best practices and coding standards Participate in system design discussions and technical planning sessions Optimize existing systems for improved performance and scalability Hands-on experience in C++ & System C based Model development/test creation Prior Experience with C based Tests/Test bench development Python coding would be a plus Knowledge on NAND concepts will be an advantage Knowledge on Memory and Digital Design Concepts would be preferable (SRAM/DRAM/ROM/Flash) Circuits/Logic Participate in design / modeling reviews and provide technical guidance to junior engineers. Document all phases of Modeling releases and development for future reference and maintenance. Stay updated with the latest technologies and trends in NAND Flash and Modeling. Languages Expertise - C, C++, Python, System C, SystemVerilog/UVM will be a plus - Tool Expertise - VisualStudio, Git, Bitbucket Hands-on contributions coding C++ & System C models & test creation Debug issues in Firmware environment Validating the developed model using SV/UVM testbench Debug failures and root-cause it by interacting with other teams/groups Etc. Qualifications Qualifications Bachelors or Masters degree in Computer Science or a related field BE/BTech/ME/MTech in Engineering with Computer Science, ECE or related field

Minimum qualifications: Bachelor's degree in Electrical Engineering, Computer Engineering, ComputerScience, a related field, or equivalent practical experience, 8 years of experience with verification methodologies and languages such as UVM and SystemVerilog, Experience developing and maintaining verification testbenches, test cases,and test environments, Preferred qualifications: Masters degree in Electrical Engineering, Computer Science, or equivalent practical experience, Experience with low power, debug, Gate Level Simulation (GLS), formal verification, Experience in driving cross functional teams for quality tape-outs Experience leading design verification of IPs, successfully delivered to many SoCs, Experience in driving or owning Sub system level verification and navigating the dependencies with Stakeholders, About The Job Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products You'll contribute to the innovation behind products loved by millions worldwide Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration, Google's mission is to organize the world's information and make it universally accessible and useful Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful We aim to make people's lives better through technology, Responsibilities Plan the verification of digital design blocks at Sub System level by fully understanding the design specification and interacting with design engineers to identify important verification scenarios, Create and enhance constrained-random verification environments using SystemVerilog and Universal Verification Methodology (UVM) or formally verify designs with SVA and industry leading formal tools, Debug tests with design engineers to deliver functionally correct design blocks, Participate with architecture, design teams, Sival and Software (SW) teams in defining the overall verification strategy of our SoCs, Be the primary point of contact for functional verification of the IP for cross-functional teams, Google is proud to be an equal opportunity workplace and is an affirmative action employer We are committed to equal employment opportunity regardless of race, color, ancestry, religion, sex, national origin, sexual orientation, age, citizenship, marital status, disability, gender identity or Veteran status We also consider qualified applicants regardless of criminal histories, consistent with legal requirements See also Google's EEO Policy and EEO is the Law If you have a disability or special need that requires accommodation, please let us know by completing our Accommodations for Applicants form ,

Job Description As an FPGA Engineer specialised in RTL (Register Transfer Level) coding, you will be responsible for designing, optimising, and implementing hardware solutions on Field-Programmable Gate Arrays (FPGAs) to support high-frequency trading strategies You will work closely with the trading systems team to develop and deploy ultra-low latency trading infrastructure, ensuring the highest levels of performance, reliability, and efficiency, Key Responsibilities RTL Design and Optimisation: Design and optimise FPGA-based solutions using RTL coding techniques to achieve ultra-low latency and high throughput for trading algorithms and strategies, Algorithm Implementation: Implement trading algorithms and strategies in hardware, leveraging FPGA capabilities to minimise latency and maximise performance, Hardware Acceleration: Identify opportunities for hardware acceleration of critical trading functions and develop FPGA-based solutions to achieve significant speedups, Performance Analysis and Tuning: Conduct performance analysis of FPGA designs, identify bottlenecks, and fine-tune the implementations to achieve optimal performance, Hardware Integration: Collaborate with software engineers and system architects to integrate FPGA-based solutions into the overall trading infrastructure, ensuring seamless operation and compatibility, Testing and Validation: Develop test benches and perform thorough testing and validation of FPGA designs to ensure correctness, reliability, and robustness under real-world trading conditions, Documentation and Reporting: Document FPGA designs, methodologies, and implementation details, and provide regular reports and updates to stakeholders on project progress and performance metrics, Requirements Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related field, Proven experience in FPGA design and development, with a focus on RTL coding using Verilog or VHDL, Deep understanding of computer architecture, digital design principles, and hardware/software co-design concepts Experience with high-frequency trading systems and ultra-low latency design techniques is highly desirable, Proficiency in FPGA development tools and workflows, such as Xilinx Vivado or Intel Quartus, Strong analytical and problem-solving skills, with the ability to optimise designs for performance, power, and resource utilisation, Excellent communication and collaboration skills, with the ability to work effectively in a fast-paced, team-oriented environment,

As an RTL Design Engineer, you will be responsible for designing and implementing high-quality RTL code for complex digital blocks and subsystems. You will collaborate with architects, verification, and physical design teams to create designs that meet functional, performance, and power requirements. Responsibilities: 1. Develop RTL designs for digital IPs, subsystems, and SoCs based on architectural specifications. 2. Collaborate with architects and system engineers to translate high-level requirements into detailed micro-architecture. 3. Perform design optimizations for area, power, and performance. 4. Conduct design reviews and ensure compliance with coding standards and best practices. 5. Work closely with verification teams to develop test plans and ensure 100% functional coverage. 6. Debug and resolve design and integration issues during simulation and post-silicon validation. 7. Participate in timing analysis and closure in collaboration with the physical design team. 8. Document design specifications, test cases, and user guides for IP and SoC designs. Requirements: 1. Bachelors or Masters degree in Electrical Engineering, Computer Engineering, or related field. 2. 210 years of experience in RTL design and implementation for VLSI systems. 3. Strong expertise in Verilog, SystemVerilog, and RTL design methodologies. 4. Solid understanding of digital design concepts such as pipelining, clock domain crossing, and low-power design techniques. 5. Experience with EDA tools like Synopsys Design Compiler, Cadence Genus, or equivalent. Proficiency in scripting languages (Python, Perl, TCL) for design automation. 6. Familiarity with SoC interfaces and protocols like AXI, AHB, PCIe, USB, or DDR. 7. Experience in static timing analysis (STA) and timing closure workflows. 8. Strong problem-solving skills and the ability to debug complex design issues. 9. Excellent communication and collaboration skills to work effectively in a team environment. Preferred Qualifications: 1. Experience with low-power design and multi-clock domain systems. 2. Knowledge of advanced process nodes (e.g., 7nm, 5nm, or below) and FinFET technologies. 3. Exposure to formal verification methodologies. Experience in hardware-software co-design and FPGA prototyping. 4. Familiarity with machine learning or AI-based RTL optimizations. How to Apply: If this role excites you, submit your updated resume at info@silcosys.com and any relevant project portfolios today. Join Silcosys Solutions Private Limited and shape the future.

BSEE and at least 5 years of prior experience are required. MSEE and at least 3 years of previous experience are strongly preferred. Prior experience in timing and or RTL design of high-speed interfaces. Prior experience collaborating with Physical Design teams in multiple successful ASIC/IP Tape Outs. Knowledge of the IP/SoC level timing closure flow and methodology. Strong command of Verilog/System Verilog language. Strong command of simulation, lint, synthesis, STA, formal verification, functional coverage, design for test, and design methodologies. Ability to handle multiple projects/tasks successfully. Experience in IP/ASIC timing constraints generation and timing closure. Expertise in STA tools and flow. Hands-on experience in timing constraints generation and management. Proficiency in scripting languages (TCL and Perl). Familiarity with synthesis, logic equivalence, DFT and backend-related methodology and tools. Capability to understand and implement improvements to existing methodologies and flows. Strong background in Constraint analysis and debugging, using industry-standard tools. Deep understanding and experience in timing closure of various test modes such as scan shift, scan capture, at speed and Best testing. Team player with a passion for innovating and a can-do attitude. Self-starter and highly motivated. Desired Skills : Knowledge of DDR/GDDR DRAM protocol; high-speed PHYs. Experience designing or integrating IP. Experience in high-speed and low-power digital design using advanced deep-micron processes. Experience with highly configurable designs

This role involves the development and application of engineering practice and knowledge in the following technologies: Design of mechanical systems, devices, equipment and machines; installing and maintaining mechanically functioning equipment; simulating a wide range of interactions and evaluate performance in real world scenarios; and develop prototype for manufacturability, testing and validation. Job Description - Grade Specific Focus on Mechanical Physical Engineering. Develops competency in own area of expertise. Shares expertise and provides guidance and support to others. Interprets clients needs. Completes own role independently or with minimum supervision. Identifies problems and relevant issues in straight forward situations and generates solutions. Contributes in teamwork and interacts with customers. Skills (competencies) Active Listening Adaptability Analytical Thinking CAD & Digital Twin Design: Generative Design & Additive Manufacturing Collaboration Material Science and Recycling Process Material Science: Metals, Composite, Surface and Nanomaterials Problem Solving Product Digital Design: AutoCAD Product Digital Design: Autodesk Fusion 360 Product Digital Design: CATIA V5 Project Management Project Planning Projects & QCT Management, Supplier Management Rapid Dynamics: Crash and Vulnerability Risk Management Scope Management Specification and Requirements Management Stakeholder Management Static Stress Analysis Static Stress: Physics & Simulation Science Strategic Thinking Sustainability-Electrification Sustainability-Green Hydrogen

Alstom Bid, Project, Planning Management Academy is hiring a Training Network Animation Manager at Group/Global level. In this role, you will o versee learning & competencies development by promoting the global training curriculum for the Bid & Project Management community. Your main responsibilities include: Main point of contact reporting to the Bid, Project, Planning Management & Certification Director for creation of communication, promotion deployment and coordination of all specific competency development/ recognition events regarding the Bid, Project, Planning Management academy. This includes animating the community network of certified Bid & Project Management members as well as onboarding and animating the specific training community. Main point of contact reporting to the Bid, Project, Planning Management & Certification Director for creation of communication, promotion deployment and coordination of all specific competency development/ recognition events regarding the Bid, Project, Planning Management academy. This includes animating the community network of certified Bid & Project Management members as well as onboarding and animating the specific training community. You will be responsible for: Propose communication strategy to promote new training launches, certification campaigns or learning week launches Design effective communication through various media with appealing design and key messages as per corporate communication policy: newsletter inputs, webinar slide design, sharepoint updates, scripts for video recordings, speaker notes etc. Prepare regular academy communication of new trainings/latest news for internal and external publishing on social media by liaising with all team members to capture latest key moments to promote Coordinate special learning workshops/events with academy members, mtiers owners, regions/product lines etc. by understanding their needs and identifying potential workshop formats/tools/best practices to animate. Develop, coordinate and execute organization of large yearly global certification ceremony day for all 3 certification programs. Guest speakers are top level leaders/special guests delivering speeches but also organizing special workshops and activities. In parallel on the same day, coordinate regional ceremony with HR/talent partners. This includes setting up the governance and review schedule leading up to the event as well as animating the review session to ensure all is on track with various stakeholders and activities required. Manage recognition certificates/awards/trophies for certification programs, trainers or special training programs: sourcing, shipping, receiving and distribution follow-up Animate newly forming Bid & Project community internal trainer network to ensure they know all Alstom processes and best practices for successful training deployment Maintain and enhance academy communication and event schedule and organize preparation for all activities accordingly Monitor communication impact by putting in place KPIs and dashboards for follow-up of site visits, impact of communication campaigns etc. In addition, you will: Be part of a team impacting Alstoms Projects and Bids at global scale Develop a multicultural mindset by interacting with teams located across the global the world Develop yourself in delivering key messages,simplification and problem solving Your profile: Business Masters degree Proven communication and marketing design experience with international corporate companies Strong experience in event management (remote or in-person) Successful learning workshop design planning and organization Digital design skills to create impactful communication Comfortable in an international and a multi-cultural environment Multi-Tasking in project mode on multiple projects at once Strong communication and powerpoint presentation skills with all levels of the organization Ability to challenge the status quo Critical Thinking / Problem solving Conflict resolution Business Acumen Teamwork / collaboration Idea generator Technical competencies regarding digital communication/learning tools and Alstom university toolbox is a big asset: MS Sharepoint, MS Forms, Bealink, Elucidat, Easymovie for video creations etc, Komodal-Metaverse.

Siemens EDA, a part of Siemens Digital Industries Software, is a global technology leader in electronic design automation. Our technologies enable companies around the world to develop new, highly innovative electronic products faster and more cost-effectively. Our customers use our solutions to push the boundaries of technology to deliver better products in the increasingly complex world of chip, board, and system design. Listener, Understander, Doer. Customers around the world trust in our products and our application engineers significantly contribute to that. You are the first on the scene to tackle any technical problem. You are a competent adviser, team player, and make things possible. Unsolvable is a foreign term, and you dont do unfair. Your focus on the customers needs makes you an invaluable partner. When you join our team, you will reach one hundred percent in your career. As an integral part of the technical team, you will contribute to Siemens EDA by increasing productivity and customer satisfaction Siemens EDAs Verification platform. This is an ambitious position that will assist in growing Siemens's business in India. Your new role: results-oriented and futuristic You will be working collaboratively with customers as well as customer support and engineering teams to optimally deploy Siemens EDAs Questa products and services. Youll fosters a climate conducive to help grow customer satisfaction with Siemens tools by helping them successfully deploy new flows and methodologies. Optionally mentor and lead a team of application engineers, supervise and guide them on the accounts and engagements that they are working on. Youll be working with customers with varying design styles and methodologies to craft the most effective technical solutions. Youll provide key expert advice and contribute to technical campaigns in other regions. Identify and qualify potential new business opportunities and work the account teams to build an engagement plan. Work with Account Managers and the world-wide teams for forming strategies and driving Siemens tools for customer projects to enable business success for Siemens EDA. Become a trusted advisor to your customers. Will have moderate travel within India and abroad We are not looking for superheroes, just super minds Youre a Graduate / Post Graduate (Bachelors/Masters) Electronics and Communication (E&C) / Electrical / Telecom Engineering / Computer Engineering with 4 - 10 years of meaningful experience in Digital design and Clock Domain Crossing or Lint EDA tools. Youve solid understanding on VHDL/Verilog, SystemVerilog and Assertions. Well versed with Multiple Clock and Reset Domains and Asynchronous clock or reset domain crossing verification ( Clock Domain Crossing - CDC & Reset Domain Crossing - RDC ) on designs Expertise in CDC tools like Questa/0in CDC, Spyglass or VC- CDC, or other CDC products is expected Expertise in Formal Verification products like Questa Formal, Jasper or any other Formal products is a plus Low power verification techniques using UPF and CPF is a plus Exposure to static timing analysis (STA) flows involving SDC is a plus

Job Description Experience: 3 to 18 years experience. Educational Qualification: B.E./ B.Tech. in Electronics and Communication, Electronics and Telecommunication, M.E. / M.Tech. Electronics & Communication Location: Bangalore Technical/Functional Skill Set : Substantial experience in the field of FPGA based Board Design, Embedded Hardware/Board Design. Expertise in Processor, Networking, Telecommunications, Bus interfaces, DDR memories, Test plan, Board bring-up, Networking, Telecommunications, Serial interfaces, Bus interfaces, DDR Memories Board bring up and debug skills Experience in system level architecture development would be preferred. Embedded HW designs for Defence applications Exposure to qualification process Tools: Schematic capture and layout tools like Orcad/Allegro SI analysis tools Soft Skills: Good Communication Skills People Management and leadership Skills Awareness of Quality Systems. Experience in handling small group sizes and projects Managerial Skills Job Description: To develop and test designs as per the project specification. To review modules developed by the group members. Monitor and Track effort and schedule of the tasks and hardware /software items of the project that are assigned to the group. Coordinate internal project meeting with Project Manager and other Group members, to present any suggestions for improvement Monitor and ensure the quality goals of the group. Co-ordinate Configuration activities and Quality Control Activities Participate, co-ordinate, implement/monitor defect prevention and process improvement activities in the project. Resolve any technical and interpersonal issues of the group members. Assist in annual performance reviews To ensure defect free and timely deliverable as per the project plan. To ensure adherence to defined processes. To provide guidance and technical assistance to Group Members. QMS and Process Adherence Learning and Growth and Group Development

Position: DFT Engineer (ASIC) Experience: 2+ Years Location: Hyderabad Job Summary: We are seeking a talented DFT (Design for Testability) Engineer with expertise in ASIC design and a strong background in EDA tools such as Synopsys . The ideal candidate will have hands-on experience in developing, implementing, and optimizing DFT architectures to ensure high test coverage and manufacturability. Key Responsibilities: Design and implement DFT methodologies for ASIC projects, including scan insertion, ATPG, and BIST. Work with EDA tools from Synopsys (such as TetraMAX, DFT Compiler, TestMAX, etc.) to achieve high test coverage and efficient test solutions. Develop and validate test strategies for scan-based testing, MBIST, and boundary scan. Collaborate with RTL and physical design teams to ensure seamless DFT integration. Perform fault simulations , analyze test results, and drive improvements in test efficiency. Optimize DFT architectures for low-power, high-performance, and manufacturability . Support silicon bring-up and debug of test patterns on actual hardware. Work closely with foundries and test teams to ensure smooth production testing. Keep up to date with the latest DFT methodologies, trends, and innovations. Required Skills & Qualifications: 4+ years of experience in DFT implementation for ASIC designs. Proficiency in Synopsys EDA tools for test implementation and validation. Solid understanding of digital design, scan insertion, ATPG, and BIST . Experience with fault modeling, test coverage analysis, and debugging . Strong scripting skills in Python, Perl, or TCL for automation. Ability to work in a multi-disciplinary team and communicate technical concepts effectively. Preferred Qualifications: Experience with Post-Silicon Debug and ATE Testing . Knowledge of Verilog/VHDL and simulation tools . Familiarity with industry-standard DFT flows and methodologies .

Candidate should be familiar with the concepts of behavioral modeling - both digital (Verilog-D) and analog (Verilog-A or Verilog-AMS). Experience in SV and UVM testbench development/modifications from mixed signal perspective is a plus. Job Description Candidate should have working experience with AMS Verification on multiple SOC s or sub-systems. One should have proficiency in AMS simulation environment using Cadence/Synopsys/Mentor tools . Knowledge of digital design techniques, Verilog HDL, and standard RTL coding styles, as we'll as analog circuit basics, with previous analog design experience a plus. Candidate should be familiar with the concepts of behavioral modeling - both digital (Verilog-D) and analog (Verilog-A or Verilog-AMS). Experience in SV and UVM testbench development/modifications from mixed signal perspective is a plus. Functional knowledge of analog and mixed signal building blocks, such as comparators, op-amps, switched cap circuits, various types of ADCs and DACs , current mirrors, charge pumps, and regulators is expected. Working knowledge of Perl / Skill/ Python/Tcl or other scripting relevant language is a plus. Candidate should have ability to lead a project team, and work collaboratively in a multi-site development environment. Your Profile You are best equipped for this task if you have: Bachelors with 5+ years or Masters with 4+ years of experience Analog: functional spec understanding of standard power management blocks, clock circuits and data converters. Loop analysis is an added advantage HDL/HVL: Verilog/Verilog-ams, SV/UVM added advantage Tools: Cadence Xcelium + spectre/ Synopsys XA-VCS/ Mentor Eldo ADMS Automation: Perl/python/shell Schedule and result oriented execution mindset, flexible in working as per the project scope needs, Exploring and experimentation for continuous methodology improvements Ability to drive projects and debug independently

Work Schedule Standard (Mon-Fri) Environmental Conditions Office Job Description Do you have a passion for innovative ideas and groundbreaking discoveries? With over $1 billion invested annually in R&D, at Thermo Fisher Scientific you ll help solve some of the world s toughest challenges, from giving cancer patients hope, ensuring safe drinking water and helping law enforcement tackle cases through forensics. We empower our teams to put science into meaningful action and give our R&D colleagues the autonomy, resources and tools they need to take science a step beyond. Role Purpose Summary: The Sr. Staff Engineer, Electrical is a member of a global R&D Team. The role is of a hands-on Electrical/Electronic engineer who is motivated to actively contribute to the new design and update of existing products. The person will play key role in architecting the systems, be involved from idea to product launch/update and own the design aspects and address all technical challenges including regulatory certifications. Roles & Responsibilities Serve thought process leadership for building depth of embedded design for team. Understand product function & convert relate design to Embedded requirements. Perform reviews on design concepts, component selections, trade off analysis drive culture of simulation, design calculations, margin analysis & design process rigor before design finalization. Build and review & approve the design documents and verification plan mapping to all the requirements including key performance & reliability requirements. Approve the design performance meets the requirements, stays in sync with the Manufacturability and Serviceability, and achieve the cost/reliability target. Work with cross function team to capture requirements, perform system / subsystem design, finalize electronics design requirement by reviewing with systems & global engineering teams. Provide design options & tradeoff analysis to meet the requirements Mentor & approve resolution for technical challenges. Collaborate closely with the other engineering team members to have design meet with compelling design and form-factors that also meet regulatory, safety, environmental, reliability, thermal and interface standard (Ethernet, USB, etc.) compliance requirements. Ensure design meets DFx requirements Continuously learns and grow technical depth and knowledge across product lines. Candidate Educational & Professional Experience Requirement: Masters or Bachelor s degree in Electrical/Electronics engineering, or related field or equivalent. 15+ years of proven experience in hardware design and development in embedded system design with strong understanding on testing & manufacturing. Proficiency Requirements Must Have: Should have demonstrated proficiency in working with system / software / Firmware / hardware / Electrical requirements development and validation Hands on experience in analog, digital and power supply design. Also, interfacing electro-mechanical and other peripherals in instrument design with sensors and control algorithm. Strong knowledge in alternate design analysis/part substitute for cost out ideas and obsolescence management including design analysis for quality, reliability, power consumption, timing parameters etc. Should have good knowledge on the compliance requirement & should support product regulatory compliance testing including EMC/EMI, CCC, UL, RoHS, etc. Proficient in debugging instruments (digital oscilloscopes, logic analyzers, spectrum analyzers); Experience in practices for Design for Test (DFT), DFR and Design for Manufacturing (DFM) background. Strong analytical and problem-solving skills and communication skills. Strong knowledge of Software & Firmware Engineering principles Agility to multiple simultaneous projects, tasks & programs to suit business needs Desirable Experience with cost take out/VAVE methodologies and Phase gate process C/C++ Embedded Programming FPGA based Design with programming using HDL Benefits We offer competitive remuneration, annual incentive plan bonus, healthcare, and a range of employee benefits. Thermo Fisher Scientific offers employment with an innovative, forward-thinking organization, and outstanding career and development prospects. We offer an exciting company culture that stands for integrity, intensity, involvement, and innovation!

Work Schedule Standard (Mon-Fri) Environmental Conditions Office Job Description Do you have a passion for innovative ideas and groundbreaking discoveries? With over $1 billion invested annually in R&D, at Thermo Fisher Scientific you ll help solve some of the world s toughest challenges, from giving cancer patients hope, ensuring safe drinking water and helping law enforcement tackle cases through forensics. We empower our teams to put science into meaningful action and give our R&D colleagues the autonomy, resources and tools they need to take science a step beyond. Role Purpose Summary: The Staff Engineer, Electrical is a member of a global R&D Team. The role is of a hands-on Electrical/Electronic engineer who is motivated to actively contribute to the new design and update of existing products. The person will play key role in architecting the systems, be involved from idea to product launch/update and own the design aspects and address all technical challenges including regulatory certifications. Roles & Responsibilities Work with cross function team to capture requirements, perform system / subsystem design, finalize electronics design requirement by reviewing with systems & global engineering teams. Provide design options & tradeoff analysis to meet the requirements Design schematic of digital, mix signal & power electronics circuit board that satisfied the design requirement Build and review the design documents and verification plan mapping to all the requirements including key performance & reliability requirements. Ensure the design performance meets the requirements, stays in sync with the Manufacturability and Serviceability, and achieve the cost/reliability target. Perform reviews on design concepts, component selections, trade off analysis and resolve technical challenges Collaborate closely with the other engineering team members to have design meet with compelling design and form-factors that also meet regulatory, safety, environmental, reliability, thermal and interface standard (Ethernet, USB, etc.) compliance requirements. To work with the sourcing team and the supplier to coordinate the manufacturing and provide detailed requirement for FCT of PCBA to make sure the PCBA from production line can meet design requirement. Continuously learns and grow technical depth and knowledge across product lines. Candidate Educational & Professional Experience Requirement: Masters or Bachelor s degree in Electrical/Electronics engineering, or related field or equivalent. 12+ years of experience in hardware design and development in embedded system design with 8/16/32-bit microprocessor design Proficiency Requirements Must Have: Should have shown strength in working with system / software / Firmware / hardware / Electrical requirements development and validation Hands on experience in analog, digital and power supply design. Also, interfacing electro-mechanical and other peripherals in instrument design with sensors and control algorithm. Indepth understanding in alternate design analysis/part substitute for cost out ideas and obsolescence management including design analysis for quality, reliability, power consumption, timing parameters etc. Should have good knowledge on the compliance requirement & should support product regulatory compliance testing including EMC/EMI, CCC, UL, RoHS, etc. Proficient in debugging instruments (digital oscilloscopes, logic analyzers, spectrum analyzers); Experience in practices for Design for Test (DFT), DFR and Design for Manufacturing (DFM) background. Strong analytical and problem-solving skills and communication skills. Strong knowledge of Software & Firmware Engineering principles Agility to multiple simultaneous projects, tasks & programs to suit business needs Desirable Experience with cost take out/VAVE methodologies and Phase gate process C/C++ Embedded Programming FPGA based Design with programming using HDL Benefits We offer competitive remuneration, annual incentive plan bonus, healthcare, and a range of employee benefits. Thermo Fisher Scientific offers employment with an innovative, forward-thinking organization, and outstanding career and development prospects. We offer an exciting company culture that stands for integrity, intensity, involvement, and innovation!

Senior Designer Job Description We are seeking a seasoned Senior Designer with a passion for creative storytelling, strong expertise in Branding, UI/UX and Publications design and a proven track record in leading design teams. This role oversees all visual aspects of Shalom Worlds programming, digital media, publications, and events. The ideal candidate is both a strategic thinker and a hands-on designer adept at juggling multiple projects and motivating a high-performing creative team to deliver world-class, brand-consistent visual content. Essential Job Functions Leadership & Team Management Provide creative vision, mentorship, and guidance to the design team. Delegate tasks based on team strengths and project requirements. Set clear performance goals, deliver regular feedback, and identify growth opportunities. Foster a collaborative, innovative, and productive work environment. Ensure workload balance, meet deadlines, and maintain design excellence across all touchpoints. Program & Broadcast Design Collaborate with the Creative Director and production teams to design on-air graphics: titles, lower thirds, transitions, and more. Maintain visual consistency across all programs as per brand standards. Offer design solutions that elevate viewer engagement and storytelling. UX/UI & Digital Media Design Lead UI/UX strategies for websites, apps, and OTT platforms. Oversee design and optimization of digital assets including social media creatives, promotional banners, ads, and interactive content. Stay updated on digital design trends, platform guidelines, and user behavior. Print & Publication Design Design print-ready materials for magazines, brochures, ads, and promotional items with high attention to detail. Coordinate with publication editors to ensure adherence to house style and visual storytelling. Review, proof, and prepare Kindle versions of the magazine. Ensure visual layouts are consistent, appealing, and brand-aligned Liaise with external printers and partners to ensure top production quality. Event Design & Branding Create compelling visuals for internal and external events: backdrops, signage, invites, merch, etc. Collaborate with event coordinators to reflect themes and objectives through design. Uphold and evolve the organization s brand identity through all design outputs. Brand & Project Management Enforce and evolve brand guidelines across all creative assets. Present ideas and design concepts to leadership and stakeholders for approval. Manage multiple design projects simultaneously, ensuring on-time delivery, within budget, and at a high standard of quality. Conduct regular quality checks, assess process inefficiencies, and implement improvements. Content Collaboration Work closely with writers, editors, and creative leads to integrate visuals with copy seamlessly. Provide design support for fundraising efforts through visually engaging materials and creative campaign ideas. Contribute to the creation of ad scripts, social visuals, and engaging copy when needed. Required Skills & Qualifications: Bachelor s or Master s degree in Graphic Design, Visual Communication, UX/UI, or a related field. 5+ years of professional experience in graphic design, including leadership roles. Strong portfolio showcasing expertise in UX/UI, layout design, publication, and branding. Proficiency in Adobe Creative Suite, Figma, Sketch, and other design tools. Strong knowledge of print production processes and digital asset optimization. Excellent aesthetic sense with a keen eye for detail, consistency, and typography. Strong organizational and project management skills. Exceptional communication and interpersonal abilities. Desirable Traits: Passion for faith-based media and Shalom World s mission. Ability to work under tight deadlines and handle feedback constructively. A proactive attitude with strong problem-solving skills. Experience working in broadcasting or publication design is a plus. Job Details Job

: We are looking for a highly skilled & experienced PD expert to join our Flows & Methodologies team. The candidate must be experienced, hands-on and have robust understanding of physical design including Floorplan, Power-plan, Place & Route, UPF, CTS. This role requires strong analytical skills, attention to detail, and the ability to work collaboratively with cross-functional teams. Proficiency in relevant EDA tools and a solid understanding of digital design principles are essential for success in these positions Scope of Responsibilities: As part of the Design Enablement team of the organization, you need to work closely with SoC cross functional teams to develop and define Physical Design methodology to meet SoC & IP level objectives on low geometry nodes (3/5/16nm) Your scope of work will cover tools and flows definition, requirement management for SoC Place & Route, UPF, Formal Verification, Floorplan & Power-Plan You will work with EDA Vendors to proactively review latest tools and flows offerings in Physical Implementation domains. Evaluate latest offerings and benchmark with organization used tools, flows, and methodologies. Work with EDA Vendors to review and resolve blocking issues You will be an actor of change for deploying new tools & methodologies across the organization Qualifications Specific skills & knowledge : Bachelor or Master or Ph. D. in Electronics Engineering and specialization in VLSI domain 10+ years of hands-on experience in Physical Design : UPF, Formal & Physical verification, floorplan, power-plan, Place & Route Proven experience in delivering physical implementation closure methodology ensuring timing & physical convergence Experience in Synopys & Cadence tool sets (Fusion Compiler, Innovus) , low geometry node issues, working with EDA team in reviewing & resolving blocking issues in project Experience in customizing flows & methodology to meet low power & area objectives of SoC Strong scripting skills for Automation and Flow development using PERL/TCL/Python. Can - do attitude, openness to new environment, people and culture Strong communication skills (written and verbal), problem solving, attention to detail, commitment to task, and quality focus Ability to work independently and as part of a team

Strong portfolio demonstrating colour matching skills & image editing abilities. Illustrating concepts by designing examples of art arrangement, size, type size & style and submitting them for approval.Preparing finished art by operating necessary Required Candidate profile Ensure final graphics and layouts are visually appealing and on-brand

We are looking for a creative and detail-oriented Textile Designer to develop original fabric designs. The ideal candidate should be skilled in digital design, with a strong understanding of color, texture, and fabric behavior.

This role involves the development and application of engineering practice and knowledge in the following technologies: Design of mechanical systems, devices, equipment and machines; installing and maintaining mechanically functioning equipment; simulating a wide range of interactions and evaluate performance in real world scenarios; and develop prototype for manufacturability, testing and validation. Job Description - Grade Specific Focus on Mechanical Physical Engineering. Develops competency in own area of expertise. Shares expertise and provides guidance and support to others. Interprets clients needs. Completes own role independently or with minimum supervision. Identifies problems and relevant issues in straight forward situations and generates solutions. Contributes in teamwork and interacts with customers. Skills (competencies) Active Listening Adaptability Analytical Thinking CAD & Digital Twin Design: Generative Design & Additive Manufacturing Collaboration Material Science and Recycling Process Material Science: Metals, Composite, Surface and Nanomaterials Problem Solving Product Digital Design: AutoCAD Product Digital Design: Autodesk Fusion 360 Product Digital Design: CATIA V5 Project Management Project Planning Projects & QCT Management, Supplier Management Rapid Dynamics: Crash and Vulnerability Risk Management Scope Management Specification and Requirements Management Stakeholder Management Static Stress Analysis Static Stress: Physics & Simulation Science Strategic Thinking Sustainability-Electrification Sustainability-Green Hydrogen.

The focus of this role is to plan, build, and execute the verification of new and existing features for AMD s graphics processor IP, resulting in no bugs in the final design. THE PERSON: You have a passion for modern, complex processor architecture, digital design, and verification in general. You are a team player who has excellent communication skills and experience collaborating with other engineers located in different sites/ timezones . You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems. KEY RESPONSIBILITIES: Collaborate with architects, hardware engineers, and firmware engineers to understand the new features to be verified Build test plan documentation, accounting for interactions with other features, the hardware, the firmware, and the software driver use cases Estimate the time required to write the new feature tests and any required changes to the test environment Build the directed and random verification tests Debug test failures to determine the root cause; work with RTL and firmware engineers to resolve design defects and correct any test issues Review functional and code coverage metrics modify or add tests or constrain random tests to meet the coverage requirements PREFERRED EXPERIENCE: Proficient in IP level ASIC verification Proficient in debugging firmware and RTL code using simulation tools Proficient in using UVM testbenches and working in Linux and Windows environment' s Experienced with Verilog, System Verilog, C, and C++ Graphics pipeline knowledge Developing UVM based verification frameworks and testbenches, processes and flows Automating workflows in a distributed compute environment . Exposure to simulation profile, efficiency improvement, acceleration, HLS tools/process Strong background in the C++ language, preferably on Linux with exposure to Windows platform Good understanding and hands-on experience in the UVM concepts and SystemVerilog language Good working knowledge of SystemC and TLM with some related experience . Scripting language experience: Perl, Ruby, Makefile , shell preferred. Exposure to leadership or mentorship is an asset Desirable assets with prior exposure to video codec system or other multimedia solutions . ACADEMIC CREDENTIALS: Bachelors or Masters degree in computer engineering/Electrical Engineering

Visual Designer Industry Category: Design Marketing Location: Bangalore Experiance: 2-3 Years Employment Type: Full-time (WFO) POSITION OVERVIEW: We re seeking a Visual Designer with 2 3 years of professional experience to bring creative vision and design execution to our brand communications, marketing campaigns, and product visuals. You ll collaborate closely with our marketing, product, and UX teams to create compelling visuals that elevate the Livprotec brand across multiple touchpoints. KEY RESPONSIBILITIES: Create high-quality visual assets for digital campaigns, social media, landing pages, email marketing, and presentations. Work closely with the brand and marketing teams to ensure visual consistency across all platforms Contribute to the evolution of Livrotec s visual identity, ensuring alignment with brand guidelines. Collaborate with UX/UI designers to ensure visual harmony across web and app interfaces. Develop illustrations, icons, infographics, and motion graphics to support storytelling. Help refine and maintain a scalable visual design system. Stay up-to-date with design trends, tools, and techniques to keep our visuals fresh and engaging. SKILLS QUALIFICATIONS 2 3 years of experience in visual design, preferably in tech, consumer products, or agency environments. Proficiency in tools such as Adobe Creative Suite (Photoshop, Illustrator, XD), Figma, and After Effects (for basic motion). Strong portfolio showcasing a range of design projects marketing campaigns, digital design, branding, etc. Solid understanding of typography, color theory, layout, and visual hierarchy. Ability to work in a fast-paced environment and manage multiple projects simultaneously. Strong communication and presentation skills; able to articulate design decisions clearly. A team player who welcomes feedback and thrives in a collaborative setting

We are seeking a highly skilled and experienced Synthesis and Static Timing Analysis (STA) expert to join our semiconductor team. The ideal candidate will have a strong background in digital design and a deep understanding of synthesis and STA processes. This role involves working closely with cross-functional teams to ensure the successful implementation and optimization of digital designs. Key Responsibilities: Good Understanding of RTL, Synthesis, LEC, VCLP, Timing Constraints Generation, UPF, Timing Closure and Signoff. Develop TCL scripts and design constraints to perform synthesis, DFT insertion, and static timing analysis. Interface for DFT strategy and implementation. Responsible for design convergence in timing and logic equivalence. Experience with EDA tools like Genus, Fusion Compiler, Primetime, Tempus, LEC, VCLP. Knowledge of scripting languages such as Perl, Python, or TCL. Qualifications Exp : 2 to 5 years of experience Company Description

Siemens EDA is a global technology leader in Electronic Design Automation software. Our software tools enable companies around the world to develop highly innovative electronic products faster and more cost-effectively. Our customers use our tools to push the boundaries of technology and physics to deliver better products in the increasingly complex world of chip, board, and system design. This role is based in Noida. But you’ll also get to visit other locations in India and globe, so you’ll need to go where this job takes you. In return, you’ll get the chance to work with teams impacting entire cities, countries, and the shape of things to come. We make real what matters! This is your role This role involves developing and implementing emulation test plans to validate sophisticated semiconductor products. The engineer will leverage hardware description languages such as Verilog and VHDL to design, implement, and debug emulation models. Teamwork is a key aspect of this role, as it requires close coordination with design, verification, and software teams to troubleshoot and resolve technical issues optimally. The position plays a meaningful role in ensuring the functionality, performance, and reliability of products before they reach the market. Key Responsibilities Develop and implement emulation test plans for product validation. Use HDL languages (Verilog, VHDL) to design, implement, and debug emulation models. Collaborate with design, verification, and software teams to identify and resolve issues. Requirement We are looking for candidates with Bachelor’s or Master’s degree in Electrical/Electronics Engineering or a related field. We are seeking Candidates with 2+ Years of Experience. We need someone who has experience with HDL languages (Verilog, VHDL) and digital design. Strong background in emulation and validation of complex digital systems. Excellent problem-solving skills and attention to detail! We are Siemens A collection of over 377,000 minds building the future, one day at a time in over 200 countries. All employment decisions at Siemens are based on qualifications, merit and business need. Bring your curiosity and creativity and help us shape tomorrow! We offer a comprehensive reward package which includes a competitive basic salary, variable pay, other benefits, pension, healthcare and actively support working from home. We are an equal opportunity employer and value diversity at our company. We do not discriminate based on race, religion, color, national origin, sex, gender, gender expression, sexual orientation, age, marital status, veteran status, or disability status. Transform the everyday #LI-EDA #LI-Hybrid

Siemens EDA is a global technology leader in Electronic Design Automation software. Our software tools enable companies around the world to develop highly innovative electronic products faster and more cost-effectively. Our customers use our tools to push the boundaries of technology and physics to deliver better products in the increasingly complex world of chip, board, and system design. Aprisa offers complete functionality for top-level hierarchical design and block-level implementation for complex digital IC designs. The detail-route-centric architecture and hierarchical database enable fast design closure and optimal quality of results at a competitive runtime. This role is based in Bangalore. But you’ll also get to visit other locations in India and globe, so you’ll need to go where this job takes you. In return, you’ll get the chance to work with teams impacting entire cities, countries, and the shape of things to come. This is your role Lead a Team of Engineers working on solving the latest design challenged in Logic Synthesis Collaborate with RnD and drive the roadmap for next generation RTL2GDSII solution. Work with design community in solving critical designs problems to achieve desired performance, area and power targets. Deployment of Synthesis solution with various customers working on cutting edge technologies (7nm and forward). Develop & deploy training and technical support to customers using Siemens EDA tools. We don’t need superheroes, just superminds! Typically requires minimum of 9+ years of experience in Logic Synthesis flows Proficiency in Verilog, System Verilog & VHDL. Strong knowledge of RTL2GDSII flow with strong fundamentals in digital design & implementation. Prior experience in IC digital design flows and front-end EDAT tools including Synthesis, DFT, Formal Verification, Logic Equivalence Checks Hands-on experience using commercial synthesis tools like Synopsys-DC/FC, Cadence-Genus is a must. Experience with advance technology nodes 7nm and below. Hands-on experience in debug & deliver solutions to critical design issues related to synthesis. TCL, Perl or Python scripting is a plus. Self-motivated team player with a zeal to drive high team performance. Good problem solving and debugging skills. Strong verbal & written communication skills We are Siemens A collection of over 377,000 minds building the future, one day at a time in over 200 countries. All employment decisions at Siemens are based on qualifications, merit and business need. Bring your curiosity and creativity and help us shape tomorrow! We offer a comprehensive reward package which includes a competitive basic salary, variable pay, other benefits, pension, healthcare and actively support working from home. We are an equal opportunity employer and value diversity at our company. We do not discriminate based on race, religion, color, national origin, sex, gender, gender expression, sexual orientation, age, marital status, veteran status, or disability status. Transform the everyday #LI-EDA #LI-Hybrid

We are seeking a highly skilled and experienced Synthesis and Static Timing Analysis (STA) expert to join our semiconductor team. The ideal candidate will have a strong background in digital design and a deep understanding of synthesis and STA processes. This role involves working closely with cross-functional teams to ensure the successful implementation and optimization of digital designs. Key Responsibilities: Good Understanding of RTL, Synthesis, LEC, VCLP, Timing Constraints Generation, UPF, Timing Closure and Signoff. Develop TCL scripts and design constraints to perform synthesis, DFT insertion, and static timing analysis. Interface for DFT strategy and implementation. Responsible for design convergence in timing and logic equivalence. Experience with EDA tools like Genus, Fusion Compiler, Primetime, Tempus, LEC, VCLP. Knowledge of scripting languages such as Perl, Python, or TCL. Qualifications Exp : 5 to 12 years of experience Company Description Renesas is one of the top global semiconductor companies in the world. We strive to develop a safer, healthier, greener, and smarter world, and our goal is to make every endpoint intelligent by offering product solutions in the automotive, industrial, infrastructure and IoT markets. Our robust product portfolio includes world-leading MCUs, SoCs, analog and power products, plus Winning Combination solutions that curate these complementary products. We are a key supplier to the world s leading manufacturers of electronics you rely on every day; you may not see our products, but they are all around you. Renesas employs roughly 21, 000 people in more than 30 countries worldwide. As a global team, our employees actively embody the Renesas Culture, our guiding principles based on five key elements: Transparent, Agile, Global, Innovative, and Entrepreneurial. Renesas believes in, and has a commitment to, diversity and inclusion, with initiatives and a leadership team dedicated to its resources and values. At Renesas, we want to build a sustainable future where technology helps make our lives easier. Join us and build your future by being part of what s next in electronics and the world.

As a Logic design lead in the IBM Systems division, you will be responsible for the micro architecture, design and development of a high-bandwidth, low-latency on-chip interconnect (NoC) and chip-to-chip interconnect and integration into high-performance IBM Systems. Design and architect different interconnect topologies as driven by bandwidth, latency and RAS requirements Develop the features, present the proposed architecture in the High level design discussion Develop micro-architecture, Design RTL, Collaborate with the Verification, DFT, Physical design, FW, SW teams to develop the feature Signoff the Pre-silicon Design that meets all the functional, area and timing goals Participate in silicon bring-up and validation of the hardware Required education Bachelor's Degree Preferred education Master's Degree Required technical and professional expertise 8+ years of relevant experience - At least 1 generation of processor interconnect design delivery leadership (eg UPI, axi, amba, NoC). - Expertise of SMP coherency - Experience in different on-chip interconnect topologies (e.g., mesh, crossbar) - Understanding of various snoop and data network protocols - Understanding of latency & bandwidth requirements and effective means of implementation - Working knowledge of queuing theory - numa/nuca architecture - Proficient in HDLs- VHDL / Verilog - Experience in High speed and Power efficient logic design -Experience in working with verification, validation, physical design teams for design closure including test plan reviews and verification coverage - Good understanding of Physical Design and able to collaborate with physical design team for floor planning, wire layer usage and budgets, placement of blocks for achieving high-performance design - Experience in leading uarch, RTL design teams for feature enhancements.