683 Digital Design Jobs - Page 14

Forza Silicon is a Business Unit in the Materials Analysis Division of AMETEK, Inc. Forza s history begins at the formation of the CMOS imaging industry where company co-founders, Barmak Mansoorian and Daniel Van Blerkom were a critical part of the Photobit team. Along with Photobit Co-founder, Dr. Eric Fossum, and many others, the team pioneered the development of CMOS imaging technology. Founded in 2001, Forza Silicon has established itself as an innovator and industry leader in the field of mixed-signal IC and CMOS imaging designs that have set the standard of the possible. Primarily through long standing customer relationships and partner referrals, Forza Silicon has grown to where today the company employs one of the industry s largest and most experienced independent CMOS imaging engineering teams. To learn more about Forza Silicon, please go to www.forzasilicon.com Postition Summary: This position will involve all phases of a design project, including specification and architectural design, detailed digital block design, simulation, verification, and design bring-up and test. This role involves collaborating with cross-functional teams to ensure that the design meets specifications. The candidate will also be expected to interface with customers to communicate specifications, design status, technical details, etc. Primary Responsibilities: Work with customers to understand sensor requirements, translate requirements to detailed specifications, and develop sensor architecture to ensure specifications are met. Work collaboratively with a team of engineers to execute design according to technical specification and schedule in an efficient manner. Design architecture and RTL coding of digital blocks, with complex operating modes. Participate in design verification, chip bring-up, and debugging in the lab by writing scripts, analyze data, and propose experiments, etc. Create and maintain detailed documentation of design processes, methodologies, and best practices. Participate in technical reviews with design team and customer. Able to work independently and collaborate with local technical lead. Work with test engineers to facilitate development of test hardware, test plans, and participate in block level bring-up and characterization efforts and results. Position Requirements Bachelor s or master s degree in electrical engineering, computer engineering, or a related field. 3-5 years of experience in RTL design, mixed signal concepts, and verification, with a strong understanding of the entire ASIC design flow. Strong knowledge of digital design principles, front-end tools, clock design, datapath, timing analysis of CMOS digital circuits, Verilog, SystemVerilog. Strong knowledge of FPGA design, firmware development for test systems, and high-speed data transmission. Working knowledge of synthesis, static timing, DFT is a plus. Proficiency in scripting languages such as Perl, Python, or Tcl for automation. Excellent problem-solving abilities, with a keen eye for detail and a methodical approach to debugging and optimization. Effective communication skills, with the ability to collaborate with cross-functional teams and present technical information clearly. Ability to adapt to new tools, technologies, and methodologies, staying current with industry trends and advancements.

Senior Staff Physical Verification Engineer Bengaluru, Karnataka, India Engineering Employee Apply Save Job Share Email LinkedIn X Facebook Jump to Overview Job Description Benefits Culture How We Hire Overview Synopsys software engineers are key enablers in the world of Electronic Design Automation (EDA), developing and maintaining software used in chip design, verification and manufacturing. They work on assignments like designing, developing, and troubleshooting software, leveraging the state-of-the-art technologies like AI/ML, GenAI and Cloud. Their critical contributions enable world-wide EDA designers to extend the frontiers of semiconductors and chip development. Play Video Job Description Category Engineering Hire Type Employee Job ID 11903 Remote Eligible No Date Posted 22/06/2025 We Are: At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation. You Are: You are an experienced and proactive professional with a strong technical background in physical design and physical verification at the IP, block, and full-chip levels. You excel in addressing challenges associated with advanced FinFET and GAA processes and have a proven ability to deliver high-quality results in complex design environments. Your expertise spans RTL-to-GDS implementation, physical verification, and signoff methodologies, and you are adept at collaborating with cross-functional teams to achieve optimal design solutions. You are detail-oriented, innovative, and thrive in a collaborative environment where continuous improvement is valued. Your strong communication skills enable you to effectively engage with internal teams and external customers, ensuring alignment and success in project execution. With a passion for technology and a commitment to excellence, you are eager to contribute to the development of cutting-edge semiconductor solutions that shape the future. What You ll Be Doing: Conceptualizing, designing, and productizing state-of-the-art RTL-to-GDS implementations for SLM monitors using ASIC design flows. Designing on-chip Process, Voltage, Temperature, Glitch, and Droop monitors to track silicon biometrics. Performing physical verification tasks, including DRC, LVS, PERC, ERC, ESD, EM, and antenna cleaning. Collaborating with the Place & Route team to resolve full-chip/IP/block-level layout integration issues and drive physical verification closure. Coordinating with internal IP owners to address IP-related issues and with the manufacturing team to resolve DRC-related challenges. Creating and updating flows/methodologies in collaboration with architects and circuit design engineering teams. The Impact You Will Have: Accelerating the integration of next-generation intelligent in-chip sensors and analytics into cutting-edge technology products. Optimizing performance, power, area, schedule, and yield across semiconductor lifecycle stages. Enhancing product reliability and differentiation in the market while reducing risk. Driving innovation in physical verification and signoff design methodologies and tools. Contributing to the development of industry-leading SLM monitors and silicon biometrics solutions. Collaborating with cross-functional teams to ensure the successful deployment of advanced technologies. What You ll Need: Educational Background : BS/B.Tech or MS/M.Tech in Electrical Engineering with 5+ years of relevant industry experience. Technical Expertise : Strong experience in physical verification and signoff, including DRC, LVS, DFM, ANT, ERC, ESD, EM, and PERC cleaning. Proficiency with digital design tools from any EDA vendor, preferably Synopsys tools like FC and ICV. Solid understanding of physical design, physical verification, and signoff concepts. Proven track record of successful physical verification closure and tape-outs in advanced nodes (14nm, 10nm, 7nm, 5nm, 3nm, 2nm). Experience with design methodologies, including developing custom scripts and enhancing flows for better execution (TCL/PERL scripting required). Additional Skills : Exposure to floorplan and PnR flows and tools such as ICC2/FC/Innovus is an added advantage. Good understanding of reliability physics, including EM, ESD, crosstalk, shielding, latch-up, and deep sub-micron challenges. Who You Are: Proactive and detail-oriented with excellent problem-solving skills. Adept at working independently and providing physical verification and signoff solutions. A strong communicator and teamer, capable of collaborating effectively with diverse teams. An innovative thinker with a passion for technology and continuous improvement. Committed to delivering high-quality results and achieving project goals. The Team You ll Be A Part Of: You will join a dynamic and collaborative team of engineers focused on developing cutting-edge semiconductor solutions. The team works on advanced physical verification methodologies, physical design, and signoff processes, driving innovation and excellence in the development of next-generation technology products. Together, you will tackle complex challenges, push the boundaries of technology, and contribute to the success of Synopsys industry-leading solutions. Rewards and Benefits: We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process. At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability. Apply Save Job test Share Email LinkedIn X Facebook Benefits At Synopsys, innovation is driven by our incredible team around the world. We feel honored to work alongside such talented and passionate individuals who choose to make a difference here every day. Were proud to provide the comprehensive benefits and rewards that our team truly deserves. Visit Benefits Page Health & Wellness Comprehensive medical and healthcare plans that work for you and your family. Time Away In addition to company holidays, we have ETO and FTO Programs. Family Support Maternity and paternity leave, parenting resources, adoption and surrogacy assistance, and more. ESPP Purchase Synopsys common stock at a 15% discount, with a 24 month look-back. Retirement Plans Save for your future with our retirement plans that vary by region and country. Compensation Competitive salaries. ** Benefits vary by country and region - check with your recruiter to confirm Get an idea of what your daily routine around the office can be like Explore Bengaluru View Map Hiring Journey at Synopsys Apply As an applicant your resume, skills, and experience are being reviewed for consideration. Phone Screen Once your resume has been selected a recruiter and/or hiring manager will reach out to learn more about you and share more about the role. Interview You will be invited to meet with the hiring team to measure your qualifications for the role. Our interviews are held either in person or via Zoom. Offer Congratulations! When you have been selected for the role, your recruiter will reach out to make you a verbal offer (a written offer will follow your conversation), and we hope you accept! Onboarding There will be some steps you need to take before you start to ensure a smooth first day, including new hire documentation. Welcome! Once you ve joined, your manager, team, and a peer buddy will help you get acclimated. Over the next few weeks, you ll be invited to join activities and training to help you ramp up for a successful future at Synopsys!

Sr Staff STA Engineer Bengaluru, Karnataka, India Engineering Employee Apply Save Job Share Email LinkedIn X Facebook Jump to Overview Job Description Benefits Culture How We Hire Overview Synopsys software engineers are key enablers in the world of Electronic Design Automation (EDA), developing and maintaining software used in chip design, verification and manufacturing. They work on assignments like designing, developing, and troubleshooting software, leveraging the state-of-the-art technologies like AI/ML, GenAI and Cloud. Their critical contributions enable world-wide EDA designers to extend the frontiers of semiconductors and chip development. Play Video Job Description Category Engineering Hire Type Employee Job ID 11904 Remote Eligible No Date Posted 22/06/2025 We Are: At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation. You Are: You are an experienced and driven professional with a strong technical background in Static Timing Analysis (STA) and physical design at the IP, block, and full-chip levels. You excel in tackling challenges associated with advanced FinFET and GAA processes and have a proven ability to deliver high-quality results in complex design environments. Your expertise spans RTL-to-GDS implementation, timing closure, and signoff methodologies, and you are adept at collaborating with cross-functional teams to achieve optimal design solutions. You are detail-oriented, proactive, and thrive in a collaborative environment where innovation and continuous improvement are valued. Your strong communication skills enable you to effectively engage with internal teams and external customers, ensuring alignment and success in project execution. With a passion for technology and a commitment to excellence, you are eager to contribute to the development of cutting-edge semiconductor solutions that shape the future. What You ll Be Doing: Conceptualizing, designing, and productizing state-of-the-art RTL-to-GDS implementations for SLM monitors using ASIC design flows. Designing on-chip Process, Voltage, Temperature, Glitch, and Droop monitors to track silicon biometrics. Developing digital back-end activities, including synthesis, pre-layout STA, SDC constraints development, placement, CTS, and routing, while collaborating with functional teams to achieve optimal design solutions. Performing post-layout STA, timing and functional ECO development, and timing signoff for high-frequency IP designs. Collaborating with the Place & Route team to resolve full-chip/IP/block-level layout integration issues and drive timing closure. Coordinating with internal RTL IP owners to address constraints-related issues. Creating and updating flows/methodologies in collaboration with architects, physical design, and RTL design engineering teams. Ensuring pre-layout and post-layout timing closure and timing model characterizations across various design corners to meet reliability and aging requirements for automotive and consumer products. The Impact You Will Have: Accelerating the integration of next-generation intelligent in-chip sensors and analytics into cutting-edge technology products. Optimizing performance, power, area, schedule, and yield across semiconductor lifecycle stages. Enhancing product reliability and differentiation in the market while reducing risk. Driving innovation in STA and signoff design methodologies and tools. Contributing to the development of industry-leading SLM monitors and silicon biometrics solutions. Collaborating with cross-functional teams to ensure the successful deployment of advanced technologies. What You ll Need: Educational Background : BS/B.Tech or MS/M.Tech in Electrical Engineering with 5+ years of relevant industry experience. Technical Expertise : Strong experience in physical design, pre- and post-layout STA, and signoff, including SDC development and multi-mode design development. Proven expertise in functional and test constraints development (shift, capture, and at-speed) and timing closure with MCMM. Experience in generating ECOs for DRV cleaning and timing closure. Proficiency with digital design tools from any EDA vendor, preferably Synopsys tools like FC/PT/PT-PX. Solid understanding of OCV, POCV, derates, crosstalk, and design margins. Advanced Node Experience : Successful timing closure and tape-outs in advanced nodes (14nm, 10nm, 7nm, 5nm, 3nm, 2nm). Scripting Skills : Experience in scripting with TCL/PERL for developing custom scripts and enhancing design flows. Who You Are: Proactive and detail-oriented with excellent problem-solving skills. Adept at working independently and providing physical design and signoff solutions. A strong communicator and team player, capable of collaborating effectively with diverse teams. An innovative thinker with a passion for technology and continuous improvement. Committed to delivering high-quality results and achieving project goals. The Team You ll Be A Part Of: You will join a dynamic and collaborative team of engineers focused on developing cutting-edge semiconductor solutions. The team works on advanced STA methodologies, physical design, and signoff processes, driving innovation and excellence in the development of next-generation technology products. Together, you will tackle complex challenges, push the boundaries of technology, and contribute to the success of Synopsys industry-leading solutions. Rewards and Benefits: We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process. At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability. Apply Save Job test Share Email LinkedIn X Facebook Benefits At Synopsys, innovation is driven by our incredible team around the world. We feel honored to work alongside such talented and passionate individuals who choose to make a difference here every day. Were proud to provide the comprehensive benefits and rewards that our team truly deserves. Visit Benefits Page Health & Wellness Comprehensive medical and healthcare plans that work for you and your family. Time Away In addition to company holidays, we have ETO and FTO Programs. Family Support Maternity and paternity leave, parenting resources, adoption and surrogacy assistance, and more. ESPP Purchase Synopsys common stock at a 15% discount, with a 24 month look-back. Retirement Plans Save for your future with our retirement plans that vary by region and country. Compensation Competitive salaries. ** Benefits vary by country and region - check with your recruiter to confirm Get an idea of what your daily routine around the office can be like Explore Bengaluru View Map Hiring Journey at Synopsys Apply As an applicant your resume, skills, and experience are being reviewed for consideration. Phone Screen Once your resume has been selected a recruiter and/or hiring manager will reach out to learn more about you and share more about the role. Interview You will be invited to meet with the hiring team to measure your qualifications for the role. Our interviews are held either in person or via Zoom. Offer Congratulations! When you have been selected for the role, your recruiter will reach out to make you a verbal offer (a written offer will follow your conversation), and we hope you accept! Onboarding There will be some steps you need to take before you start to ensure a smooth first day, including new hire documentation. Welcome! Once you ve joined, your manager, team, and a peer buddy will help you get acclimated. Over the next few weeks, you ll be invited to join activities and training to help you ramp up for a successful future at Synopsys!

Shell is seeking an experienced Product Designer to help shape the future of user-centric experiences across both digital and non-digital touchpoints . This role demands a designer who can seamlessly blend business understanding, user empathy, and creative execution to support Shell s innovation, digital transformation, and sustainability goals. Key Responsibilities: Lead the design of intuitive, scalable, and inclusive digital experiences across web and mobile platforms, aligned with Shell s business and customer objectives. Work on non-digital design initiatives, including physical interfaces, printed materials, and service environments to ensure a consistent Shell brand experience. Conduct user research, usability testing, and translate insights into actionable design improvements. Collaborate with cross-functional teams including product owners, developers, business stakeholders, and other designers in an agile delivery environment. Design wireframes, mockups, prototypes, and user journeys using tools like Figma, Adobe XD, or similar. Ensure alignment with Shell s global design system, brand standards, and accessibility best practices. Continuously iterate based on user feedback, business inputs, and performance analytics. Required Qualifications: 7 10 years of experience in product design with a strong emphasis on UI/UX. Proven ability to design across digital (web/mobile apps) and non-digital experiences. Strong portfolio demonstrating problem-solving, creativity, and business impact. Proficient in Figma, Adobe Creative Suite, Sketch, or equivalent design tools. Familiarity with front-end capabilities (HTML/CSS knowledge a plus). Strong communication, stakeholder engagement, and presentation skills. Preferred Attributes: Experience working in large-scale enterprise or global matrix environments. Exposure to energy, industrial, or sustainability-focused projects is a plus. Comfortable working in fast-paced, agile environments. Ability to mentor junior designers and promote design thinking culture.

Domain : RTL FPGA SoC ASIC Design Must-Have Skills: RTL Coding, IP Design, SoC Development, Lint, CDC, Micro-architecture Protocol experience in PCIe DDR Ethernet (any one) Exposure to I2C UART SPI protocols Tool expertise in Spyglass Lint/CDC Synopsys DC Verdi Xcellium (any one)Scripting with Makeflow, Perl, Shell, Python (any one) Good to Have: Knowledge of ARM debug architecture Ability to debug across multiple subsystems Experience creating/reviewing design documentation Ability to collaborate with Physical Design, DFT, SW, and Verification teams Role Insights: Expertise in SoC Subsystem IP Design Deep understanding of RTL Quality Checks (Lint, CDC) Familiarity with Low Power Design & Synthesis Strong grasp of AMBA protocols (AXI, AHB, ATB, APB) Proficiency with multiple design & verification tools Effective communicator across multi-disciplinary teams Location : Bangalore | Hyderabad | Cochin | Pune

We're looking for a highly skilled Senior Digital Verification Engineer with extensive hands-on experience in SystemVerilog (SV) and UVM methodology. In this role, you'll be instrumental in developing robust verification plans, building reusable testbench components, and driving comprehensive coverage closure for complex digital blocks at various levels. Responsibilities: Collaborate with cross-functional teams to meticulously review and refine architecture and design specifications. Develop comprehensive verification plans for complex digital modules at the IP, Subsystem, and SoC levels. Design and implement reusable testbench components , including drivers, monitors, and scoreboards, utilizing SV-UVM methodology. Work closely with design teams to achieve rigorous coverage closure. Coordinate with silicon test and evaluation teams to develop and deliver effective test patterns. Required Qualifications: Extensive hands-on experience (6+ years) in digital verification using SystemVerilog (SV) and UVM methodology . Proven expertise in developing verification plans for complex digital blocks. Proficiency in creating testbench environments at IP and/or Subsystem levels. Experience in constrained random stimulus generation and coverage closure . Competence in Gate-Level Simulation (GLS) setup and debugging. Strong debugging skills and analytical problem-solving capabilities . Familiarity with ARM-AMBA protocols . Advantageous Skills: Experience in formal verification and SystemVerilog Assertions (SV-Assertion) coding. Exposure to mixed-signal verification . Exposure to Ethernet interface standards .

We're looking for a skilled and highly motivated Digital Design Engineer to join our team. In this role, you'll be instrumental in translating complex design specifications into optimal micro-architectures for digital blocks, driving the development of high-performance, power-efficient, and area-optimized silicon. Key Responsibilities: Translate design specifications into optimal micro-architectures for digital blocks, ensuring efficiency and performance. Perform RTL coding using Verilog and SystemVerilog, bringing designs to life. Achieve stringent power, performance, and area (PPA) goals through meticulous micro-architecture optimization. Conduct block-level design verification, ensuring the robustness and correctness of your designs. Collaborate closely with the Design Verification (DV) team to develop comprehensive test plans. Drive front-end implementation activities, including Lint/CDC checks, synthesis, and timing constraint development. Work closely with Design-for-Test (DFT) and Physical Design (PD) teams for successful sign-off. Support Silicon validation, ensuring the fabricated chip meets all design specifications. Position Requirements: BE/BS/MTech/ME/PhD degree in Electrical/Electronics/Computer Science from a reputed institute. 3-10 years of relevant experience in digital design. Hands-on experience in digital logic design, RTL coding, simulation, and debug. Proven experience in writing and debugging timing constraints at both block and full-chip levels. Experience in Synthesis and Logical Equivalence Checking (LEC). Excellent verbal and written communication skills to effectively collaborate with geographically dispersed teams. Experience in digital signal processing and MATLAB modeling is highly desirable. Experience in Processor Subsystem design or System-on-Chip (SoC) development is a plus.

Analog Devices is seeking a talented and dynamic Digital Design Engineer to join our team. In this role, you'll be instrumental in creating engaging and visually appealing digital assets that enhance the user experience across a variety of platforms. This is an exciting opportunity to embark on a rewarding career journey with a leading innovator. Key Responsibilities: Design compelling digital assets for web and mobile applications, email campaigns, social media platforms, and other digital channels. Collaborate with cross-functional teams to deeply understand design requirements and develop innovative, creative solutions. Ensure all digital designs are user-friendly and meticulously optimized for both performance and functionality. Create and maintain comprehensive design guidelines and templates for all digital assets, ensuring consistency and efficiency. Work closely with developers to guarantee accurate implementation of designs, bridging the gap between design and development. Present design concepts and ideas to stakeholders , effectively articulating your vision and gathering feedback for continuous improvement. Meet or exceed individual and team performance goals , contributing to the overall success of our digital initiatives. Qualifications: Proficiency in industry-standard design software and tools , including Adobe Creative Suite, Sketch, Figma, or InVision. Strong problem-solving and analytical skills , enabling you to tackle complex design challenges effectively. Excellent communication and interpersonal skills , fostering seamless collaboration within teams and with stakeholders.

Create visually compelling assets for websites, landing pages, social media, paid ads, and presentations. Work closely with content strategists, developers, and marketing teams to bring ideas to life. Maintain consistency across all visual materials in line with client brand guidelines. Translate complex SaaS ideas into simple and visually appealing graphics. Collaborate on creative direction and push forward new ideas for visual storytelling. Iterate quickly based on feedback and performance metrics. Requirements 0-3 years of experience in visual/graphic design (SaaS or B2B experience is a big plus). Strong portfolio showcasing a range of digital design work (especially for SaaS brands). Proficiency in tools like Figma, Adobe Creative Suite (Photoshop, Illustrator, After Effects), and Canva. Understanding of responsive web design, UI/UX basics, and modern design trends. Experience designing for performance marketing and growth-driven content is a plus. Strong attention to detail and an eye for clean, minimal, yet effective design Nice to Have Familiarity with Lottie, motion graphics, or video editing. Experience using tools like Notion, Slack, Clickup, or Asana. Ability to understand marketing goals and translate them visually.

Lead development efforts for AMS design collaterals generation fortop level integration, ensuring optimized performance Job Description In your new role you will: Lead development efforts for AMS design collaterals generation for top level integration, ensuring optimized performance. Enforce consistency of all required views for AMS macro integration. Ensure quality of digital design deliverables to RTL2GDS counter parts by running preliminary RTL synthesis and timing checks. Identify and apply methodologies to allow optimal timing closure of complex AMS IP (ADCs, clocking) in the context of digital-on-top integration. Collaborate with cross-functional teams, including digital design,AMS design, layout, and test engineers, to ensure successful productintegration. Interface with design system community, design flow and methodologyteams across multiple sites (Europe, US and Asia). Validate AMS views generation flow to guarantee smooth execution incase of design system and/or design package updates. Your Profile You are best equipped for this task if you have: Master s or Ph.D. in Electrical Engineering or a related field. 15+ years of experience in complex AMS & SoC integration within thesemiconductor industry Proven track record of successful product implementation in advancedCMOS and BCD technologies Deep technical knowledge of mixed-signal IC design and integrationflows Very good understanding of RTL2GDS flows and experience in runningsynthesis, timing closure, DFT insertion Ability to work in a multinational environment and connect designteams with RTL2GDS and SoC integration teams across the organization Ability to support project planning and commitment to ensure timelyexecution. Ability to report progress and issues related to SoC integration tosenior executives

The focus of this role is to plan, build, and execute the verification of new and existing features for AMD s graphics processor IP, resulting in no bugs in the final design. THE PERSON: You have a passion for modern, complex processor architecture, digital design, and verification in general. You are a team player who has excellent communication skills and experience collaborating with other engineers located in different sites/ timezones . You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems. KEY RESPONSIBILITIES: Collaborate with architects, hardware engineers, and firmware engineers to understand the new features to be verified Build test plan documentation, accounting for interactions with other features, the hardware, the firmware, and the software driver use cases Estimate the time required to write the new feature tests and any required changes to the test environment Build the directed and random verification tests Debug test failures to determine the root cause; work with RTL and firmware engineers to resolve design defects and correct any test issues Review functional and code coverage metrics modify or add tests or constrain random tests to meet the coverage requirements PREFERRED EXPERIENCE: Proficient in IP level ASIC verification Proficient in debugging firmware and RTL code using simulation tools Proficient in using UVM testbenches and working in Linux and Windows environment s Experienced with Verilog, System Verilog, C, and C++ Graphics pipeline knowledge Developing UVM based verification frameworks and testbenches, processes and flows Automating workflows in a distributed compute environment . Exposure to simulation profile, efficiency improvement, acceleration, HLS tools/process Strong background in the C++ language, preferably on Linux with exposure to Windows platform Good understanding and hands-on experience in the UVM concepts and SystemVerilog language Good working knowledge of SystemC and TLM with some related experience . Scripting language experience: Perl, Ruby, Makefile , shell preferred. Exposure to leadership or mentorship is an asset Desirable assets with prior exposure to video codec system or other multimedia solutions . Expertise in Verilog, System Verilog, and Object-Oriented Programming Experience with UVM or similar Verification Methodology Requires strong Computer Architecture knowledge Comfortable in python / perl and editing / maintaining scripts Experience working in a team environment through the ASIC Project lifecycle from Planning to Tape Out Experience with DRAM controllers, DDR Phys or DRAM Interface Protocols is a plus. Strong communication skills and the ability to work independently as we'll as in a cross-site team environment ACADEMIC CREDENTIALS: Bachelors or Masters degree in computer engineering/Electrical Engineering

As a Fortune 50 company with more than 450,000 team members worldwide, Target is an iconic brand and one of America's leading retailers. Target in India operates as a fully integrated part of Targets global team and has more than 4,000 team members supporting the companys global strategy and operations. About Target Tech: Every time a guest enters a Target store or browses Target.com nor the app, they experience the impact of Targets investments in technology and innovation. Were the technologists behind one of the most loved retail brands, delivering joy to millions of our guests, team members, and communities. Join our global in-house technology team of more than 5,000 of engineers, data scientists, architects and product managers striving to make Target the most convenient, safe and joyful place to shop. We use agile practices and leverage open-source software to adapt and build best-in-class technology for our team members and guestsand we do so with a focus on diversity and inclusion, experimentation and continuous learning About team Join a world-class Product Design (UX) and Accessibility team responsible for connecting the guest to the product and UX team for key context and insights that better inform the design process. Here, we pride ourselves on designing tangible, inspiring and impactful solutions that serve our guests, team members and business. And we make sure that all of Target's Digital experiences, both in-store and online, are fully accessible to people with disabilities. About you: You thrive at the intersection of design craft and strategy. Youre a curious person who falls in love with problems and enjoys iterating toward a solution. Youre passionate about making an impact and effectively connect data insights, business goals and users needs to set your direction. You present work clearly and effectively to educate others and gain support. You value design that is welcoming, inspiring and simple. As a Lead Product Designer, youll... Own the full design process, from early discovery and testing to asset delivery and pixel-tweaking with engineers Design flows that are intuitive, elegant and provide value for our guests while accounting for a wide variety of scenarios Leverage data, business and internal users needs to inform and advocate for your direction Have full ownership and match the global standards of experience for enterprise applications used by team members at headquarters offices. Apply Lean UX with an Information Architect lens Define/be an prominent contributor of Design processes/disciplines and tools WoW around the agile methodologies with the Product and the Engineering teams which help our design team members in efficiently designing and delivering valuable solutions and experiences to our end-users Collaborate with Product designers, writers, engineers, product managers, QA, accessibility team members, UX researchers and partners in marketing Consult with teams across Target(design systems, guest facing, internal tools and accessibility) to ensure cohesiveness in the team member experience Utilize & contribute to a pattern library maintained by our design systems team Evolve as an SME in your product space with the help of business partnering, prioritising, communicating, directing and also behold a broader level vision of the overall Big picture Minimum requirements: 10+ years of visual and interaction design experience A portfolio featuring digital design work enclosing in-depth case studies and clean/modern design thought process Experience designing digital products (web, apps or software) and Customer facing portals/ modules in preferably in retail domain Demonstrated expertise with modern design, prototyping and collaboration tools (such as Figma and Miro) Awareness of data and research methodologies and ability to conduct or partner with research experts Proficiency in building metric-based-apps through data visualizationExcellent collaboration and influential skills Know More Here: Life at Target- https://india.target.com/ Benefits- https://india.target.com/life-at-target/workplace/benefits Follow us on social media: https://www.linkedin.com/company/target/ Target Tech- https://tech.target.com/

CONTENT STRATEGIST ABOUT ERP BUDDIES ERP Buddies Inc. is comprised of dynamic business and specialized technical experts in the ERP industry. ERP Buddies applies best practices in the consultation, implementation, integration, and customization of cloud-based products. We provide a 360 approach to our clients to ensure they are receiving the best possible solutions. At ERP Buddies, we focus on our core values and work as a team to get the job done. We are more than just co-workers; we are like family. With our dynamic and unique work environment, our employees have the opportunity to take ownership of projects and learn and grow within the company. We know that when you surround yourself with the best, you achieve success and in turn, achieve success for our clients. To learn more about ERP Buddies Inc., please visit www.erpbuddies.com. We are looking for amazing talent who can contribute to our efforts and deliver results! ERP Buddies is seeking a Content Strategist who will immediately contribute to the organization s marketing efforts. If you love technology, are interested in technical content writing, are well organized, and are keen to join an industry leader we would love to hear from you! Responsibilities: Developing clear and engaging content that is consistent with the company s brand image and addresses both business goals and consumer needs. Take in charge of entire company socials including posts, stories and community engagement. Delegating tasks to marketing assistants and co-ordinators and providing feedback. Manage and produce digital design work, including banner sizing and versioning Requirement A Confident personality that doesn t shy away in front of cameras / mics Multitask and manage simultaneous projects within short deadlines. Research ERP and technology industry-related topics to come up with new content ideas. Communicate status, timelines and updates real-time to key stakeholders. Multitask and manage simultaneous projects within short deadlines. Qualifications: Completed a University/College degree in Business, Marketing, Communications, Journalism, Advertising or a related field preferred. 2-3 years of experience in content management systems, keyword research tools, social media platforms, search engine optimization (SEO), and search engine marketing (SEM). Previous experience in content creation for an IT consulting or ERP based profile is required. Proficient with social media platforms like Facebook, Twitter, Instagram, LinkedIn, Pinterest, and YouTube. Experience with HootSuite, Buffer and any other publishing tools. Google Certifications (SEO, SEM, GStudio) will be considered an asset. Strong portfolio and/or demo reel that demonstrates conceptual thinking and final outputs. Creative mindset and out of the box thinker that enjoys storytelling through media We wish to thank all applicants for their interest and effort in applying for this position, however, only candidates selected for interviews will be contacted. ERP Buddies Inc. is an equal opportunity employer. In addition, ERP Buddies Inc. is committed to providing accommodations for people with disabilities in accordance with provincial legislation. Please let us know if you require a reasonable accommodation due to a disability during any aspect of the recruitment process and we will work with you to address your needs. To provide the best experiences, we use technologies like cookies to store and/or access device information. Consenting to these technologies will allow us to process data such as browsing behavior or unique IDs on this site. Not consenting or withdrawing consent, may adversely affect certain features and functions. The technical storage or access is strictly necessary for the legitimate purpose of enabling the use of a specific service explicitly requested by the subscriber or user, or for the sole purpose of carrying out the transmission of a communication over an electronic communications network. The technical storage or access is necessary for the legitimate purpose of storing preferences that are not requested by the subscriber or user. The technical storage or access that is used exclusively for statistical purposes. The technical storage or access that is used exclusively for anonymous statistical purposes. Without a subpoena, voluntary compliance on the part of your Internet Service Provider, or additional records from a third party, information stored or retrieved for this purpose alone cannot usually be used to identify you. The technical storage or access is required to create user profiles to send advertising, or to track the user on a website or across several websites for similar marketing purposes.

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 6+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 5+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience. Join Qualcomm's design verification team in verifying the high-speed mixed-signal IP designs ( PCIe, USB, MIPI, CXL, C2C, D2D, DDR, PLL, DAC, ADC, Sensors, etc.) for exciting products targeted for 5G, AI/ML, compute, IOT, and automotive applications. The team is responsible for the complete design verification lifecycle, from system-level concept to tape out and post-silicon support. Responsibilities Define pre-silicon and post-silicon testplans based on design specs and using applicable standards working closely with design team. Architect and develop the testbench using advanced verification methodology such as SystemVerilog/UVM, Analog/mixed signal simulation, Low power verification, Formal verification and Gate level simulation to ensure high design quality. Author assertions in SVA, develop testcases, coverage models, debug and ensure coverage closure. Work with digital design, analog circuit design, modeling, controller/subsystem, & SoC integration teams to complete the successful PHY level verification, integration into subsystem and SoC, and post-silicon validation. Minimum Qualifications Master's/Bachelor’s degree in Electrical Engineering, Computer Engineering, or related field. 12+ years ASIC design verification, or related work experience. Knowledge of a HVL methodology like SystemVerilog/UVM. Experience working with various ASIC simulation/formal tools such as VCS, Xcellium/NCsim, Modelsim/Questa, VCFormal, Jaspergold, 0In and others. Preferred Qualifications Experience with Low power design verification, Formal verification and Gate level simulation. Knowledge of standard protocols such as PCIe, USB, MIPI, LPDDR, etc., Experience in scripting languages (Python, or Perl). Experience with mixed-signal IP design verification, such as USB, PCIe, CXL, C2C, D2D, MIPI, UFS, DDR, PLL, Data Convertors (DAC, ADC), or sensors.

Job Area: Engineering Services Group, Engineering Services Group > Layout Engineer General Summary: Develops block, macro, or chip level layouts and floorplans according to project requirements, specifications, and design schematics. Applies understanding of design manuals, established processes, layout elements, and basic electronic principles to create accurate designs that meet project needs. Conducts analyses, tests, and verifies designs using different tools and techniques to identify and troubleshoot issues, and stays abreast of new verification methods. Works with multiple internal and external stakeholders to align on projects, provide updates, and resolve issues. Minimum Qualifications: Bachelor's degree in Electrical Engineering, Computer Science, Mathematics, Electronic Engineering, or related field and 2+ years of experience designing custom layouts in relevant domain (e.g., analog, mixed signal, RF, digital design), or related work experience. OR Associate's degree in Computer Science, Mathematics, Electrical Engineering or related field and 4+ years of experience designing custom layouts in relevant domain (e.g., analog, mixed signal, RF, digital design), or related work experience. OR High School diploma or equivalent and 6+ years of experience designing custom layouts in relevant domain (e.g., analog, mixed signal, RF, digital design), or related work experience. 2+ years of experience using layout design and verification tools (e.g., cadence, LVS, rmap). Qualcomm is a company of inventors seeking to revolutionize the CPU market in an age of new possibilities. Are you interested in joining Qualcomm’s high performance CPU team as an SRAM Mask Layout DesignerYou will have the opportunity to work with some of the most talented and passionate engineers in the world to create designs that push the envelope on performance, energy efficiency and scalability. We offer a fun, creative and flexible work environment, with a shared vision to build products to change the world. As a Mask Layout Designer, you will develop block or macro level layouts and floorplans for high performance custom memories according to project requirements, specifications, and design schematics. Minimum qualifications 5+ years of experience and a high school diploma or equivalent OR 5+ years experience and BS in Electrical Engineering OR 3+ years experience and MS in Electrical Engineering Direct experience with custom SRAM layout Experience in industry standard custom design tools and flows. Knowledge of leading-edge FinFET and/or nanosheet processes (5nm or newer). Experience in Layout design of library cells, datapaths, memories in deep sub-micron technologies. Knowledge of all aspects of Layout floorplanning and hierarchical assembly. Knowledge of Cadence Virtuoso and Calibre LVS/DRC. Preferred qualifications Good understanding of device parasitics and reliability considerations during layout. Good understanding of critical circuits and layout styles. Ability to write Skill code for layout automation. Knowledge of improving EMIR in layout. Good communication skills to work with different teams to accurately describe issues and follow them through for completion. Roles and Responsibilities Design layout for custom memories and other digital circuits based on provided schematics. Read and interpret design rule manuals to create optimal and correct layout. Own the entire layout process from initial floorplanning to memory construction to physical verification. Use industry standard verification tools to validate LVS, DRC, ERC etc. Interpret the results from the verification suite and perform layout fixes as needed. Provide layout fixes as directed by the circuit design engineers. Work independently and execute memory layout with little supervision. Provide realistic schedules for layout completion. Provide insight into strategic decisions regarding memory layout and

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: Job Summary: Position for 5-8 years of experience in design verification of complex Qualcomm propriety DSP/NPU IP DSP team is responsible for delivering high-performance DSP/NPU cores which are at the heart of Qualcomm's multi-tier SoC roadmap targeted for mobile space, AI, Automotive and more. Qualcomm is one of the largest fabless semiconductor design companies in the world, generating over $35 Billion in annual revenues from chipsets and royalties from intellectual property. Job Responsibilities: Drive design verification of DSP IP by working with a global DSP design team involving architecture, implementation, power, post silicon and back-end teams. Implement and improve System Verilog/UVM Testbench Architecture. Develop and deploy new verification methodologies, automation to continuously improve quality and efficiency. Develop design corresponding test plans, architect and develop verification environments, and meet coverage goals. Hands-on simulations and ability to debug not only IP level, but Subsystem and SoC level fails and bugs. Complete all required verification activities at IP level and ensure high quality commercial success of our products. Assertions, simulation, formal verification (static property checking), HW-SW co-verification, constraint/HVL-based verification, simulation acceleration, emulation are all tools you will use on a daily basis. Responsible gate level simulation bring-up, gate level verification with timing simulations. Responsible for power aware RTL verification and gate level simulation. Skillset/Experience: 5-8 years experience in processor/ASIC design verification Solid background and understanding of Digital Design, Processor Architecture , Processor Verification and Power aware verification. Expertise in System Verilog Testbench Architecture and implementation. Experience in writing C based and assembly level testcases is preferred. Exposure to power aware implementation and verification using UPF is a plus. Experience with advanced verification techniques such as formal and assertions is a plus. Gate-Level Simulation and Debug — 0-delay, timing annotated and power aware. Experience in System Verilog/UVM, and with simulators from Synopsys/Mentor/Cadence . Scripting/Automation Skills — Perl, Python, Shell, Make file TCI . Solid analytical and debugging skills, strong knowledge of digital design and good understanding of Object Oriented Programming (OOP) concepts. Experience in Hardware verification languages (HVL) such as SystemVerilog testbench (OVM/UVM) and SystemC and Hardware description languages (HDL) such as Verilog, SystemVerilog is preferred. Experience in verification of Processor subsystems is preferred. Experience in creating validation suite and building automation. Should have excellent inter-personal and communication skills. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience.

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: NUVIA is now part of Qualcomm. Our mission is to reimagine silicon and create computing platforms that will transform the industry. You will have the opportunity to work with some of the most talented and passionate engineers in the world to create designs that push the envelope on performance, energy efficiency and scalability. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 6+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 5+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience. As CPU Physical Design CAD engineer, you will build and support the world’s best implementation tools and flows. Your tools and flows will ensure our custom CPUs have industry-leading power, performance and area. Roles and Responsibilities Develop, integrate and release new features in our high-performance place-and-route CAD flow Architect and recommend methodology improvements to ensure our silicon has the best power, performance and area Maintain, support and debug implementation flows, and resolve project-specific issues Work closely with worldwide CPU physical design teams, and provide methodology guidance, tools/flows support and help achieve class-leading PPA. Work with EDA vendors to define roadmap and to resolve tool issues Preferred Qualifications: Bachelors/Masters degree in Electrical/Electronics Engineering or Computer Science Ten+ years of hands-on experience in place-and-route of high-performance chips - either in a design or CAD role High level of proficiency in Tcl as well as Python Experience with automation Experience with a wide variety of Physical Design tasks - ranging all the way from place-and-route, analysis, timing sign-off and PDV Experience with advanced technology nodes (5nm or lower) Solid understanding of digital design, timing analysis and physical verification Strong user of industry-standard place-and-route tools such as Cadence Innovus Proven track record of managing and regressing place-and-route flows

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 8+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 7+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 6+ years of Hardware Engineering or related work experience. J Principal Responsibilities: Senior leader with 20+ CAD/Methodology development experience for team in Bengaluru. Drive tools, flows, methodologies globally as part of world-wide CAD organization. Develop and implement advanced CAD flows and methodologies for front end RTL Design to Verification Methodologies and framework development. Utilize scripting languages (python) to automate CAD/IT processes and increase efficiency. Collaborate with cross-functional teams to ensure successful integration of CAD flows. Stay up-to-date with cutting-edge technology (AI/ML), conduct thorough analysis of CAD tools and make improvements. Work closely with users to troubleshoot and resolve any issues that arise in tools, flows, environment, and infrastructure. Preferred Qualifications: Experience building full stack AI applications, with a focus on practical, production-grade solutions Strong proficiency in Rust for performance-critical systems and Python for AI development and scripting . Solid understanding of large language models (LLMs), their mechanics, and their real-world applications. Experience implementing tool use capabilities for LLMs and agent frameworks Knowledge of evaluation methodologies for fine-tuned language models Good grasp of Retrieval-Augmented Generation (RAG) and latest AI Agent frameworks Ability to stay current with the fast-evolving AI landscape]. Including advancements in LLMs and neural networks Strong understanding of CAD/EDA tools and methodologies. Hands on experience with regression systems, CI/CD, Revision Control System (git, perforce) workflow. Strong fundamentals in digital design, design verification methodologies and EDA tools. Knowledge of SOC architecture is a plus Preferred – Masters in VLSI or Computer Science Minimum – Bachelors in Electronics/Electrical Engineering/Computer Science Atleast 15 years’ experience in development of tools/flows/methodologies in either RTL, DV, synthesis, PnR or Signoff. Should have a proven record of driving new innovative tool/flow/methodology solutions. Should have managed a medium sized team. Level of Responsibility: Works independently with minimal supervision. Work with chip leads in support of design verification. Collaborate with chip leads to understand the design methodology. high-level requirements, determine other areas to support current or future designs that can benefit from automation and tooling. Provides supervision/guidance to other team members. Decision-making is significant in nature and affects work beyond immediate work group. Requires verbal and written communication skills to convey complex information. May require negotiation, influence, tact, etc.

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field. As a digital ASIC R&D Engineer, you will play a vital role in addressing challenges with Performance, Power, and Area (PPA) scaling tradeoffs to qualify technology entitlement of advance process nodes. You will be responsible for research and develop methods to improve efficiency of digital design, power and chip quality/yield. The job scope includes design automation, Design-Device/process Interaction Analysis, post-silicon yield debug and data mining. Required Skills Coding with Python, Perl, TCL and/or C Strong fundamental and working knowledge of SPICE, Parametric Testing Basic fundamental of Post Si Bring Up/Wafer Probing and System Level Testing Strong fundamentals in CMOS Device Physics, Process Engineering & Digital Design Working knowledge of digital VLSI implementation (netlist to GDS) with expertise in STA Expected Experience 1 –3 years of relevant industry experience

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: Qualcomm's Bangalore WLAN PHY (Baseband) team is seeking VLSI Digital Design Engineers to lead IP development for the latest WiFi standards. Our WLAN PHY team, comprised of highly passionate and seasoned domain experts, prides itself on years of experience in taking WLAN PHY designs from concept to silicon independently. WLAN PHY team is responsible for delivering the end-to-end Tx/Rx DSP chains – all the way from antenna samples post ADC to raw bits for upper layers and on the reverse path from raw bits to DAC. The team specializes in working with challenges of practical high-speed wireless communication systems and finding innovative solutions to counter them. The team works extensively on typical signal processing functions like filters, matrix transformations (e.g.QR, Cholesky decomposition), channel estimation, equalization (MMSE, MRC, ML), decoders/encoders (e.g.LDPC, Viterbi) , demodulators, FFT etc. on a day-to-day basis, and contributes to the development/ enhancement/ evaluation of signal processing algorithms to cater to new requirements. We are looking for someone as passionate as us and takes pride in their work. WiFi's ubiquity in modern times is undeniable, and the IEEE 802.11 Working Group is continually developing new standards to satisfy the growing demand for high throughput and low-latency real-time applications, such as VR and AR. Qualcomm is at the forefront of the WiFi revolution, aiming to become the global leader in WiFi chip solutions. The WLAN PHY team in Bangalore is instrumental in realizing this vision. : Looking for a candidate with 1 to 3 years of hands-on experience in micro-architecting and developing complex IPs. Expertise in digital design, VLSI concepts, and experience in creating power/area-efficient IPs across multiple clock domains are essential. Proficiency in RTL coding and familiarity with RTL QA flows such as PLDRC, CDC, and CLP (optional) is expected. Candidates should be capable of proposing design alternatives to meet area/power/performance specifications and presenting these options for review. Experience in leading, guiding, or managing junior team members is advantageous. Repeated success in taking IP designs from requirements to silicon is required. While not mandatory, having developed IPs for wireless technologies (WLAN, LTE, NR, BT, UWB, etc.) or past HLS experience would be beneficial. Skills: Must have: Proficient in Verilog RTL coding, uArch, CDC check, PLDRC, Timing constraints, Python/Perl. Experience in design/debugging complex data-path/control-path IPs. Good communication, analytical & leadership skills. Good to have: System Verilog, Visio, Knowledge of signal processing concepts/algorithms and Wi-Fi standards (802.11a/b/g/n/ac/ax), experience with HLS. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field.

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: Excellent Design verification domain expertise. Develop test strategy, TB architecture and test plan for new IP’s/new features Develop strategies for re-useable, scalable and enhance Sub system level verification environment Excellent C/System Verilog/Verilog skills to handle C based TB environment Strong skills in debug, post silicon debug-failure re-creation and root cause analysis Scripting proficiency - PERL, Python, for developing applicable automation AMBA, AXI bus protocols Power intent verification, GLS etc. Capable of communicating effectively with all stakeholders across the globe Capable of seeding a new team for new IPs, able to hire and expand the team in expertise and efficiency Capable of mentoring the team members for their career growth, maintaining diversity in the team, collaborating with other leads and managing multiple parallel projects Take initiatives to enable various ideas for improving efficiencies. Good to have Image Processing, DSI/DP/HDMI Protocols Good knowledge of new methodologies, flows and tools to be incorporated. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 6+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 5+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience.

Software Principal Engineer The Software Engineering team delivers next-generation application enhancements and new products for a changing world. Working at the cutting edge, we design and develop software for platforms, peripherals, applications and diagnostics all with the most advanced technologies, tools, software engineering methodologies and the collaboration of internal and external partners. Join us to do the best work of your career and make a profound social impact as a Software Principal Engineer on our 5G RAN FPGA Verification Team in Bangalore . What you ll achieve As a Software Principal Engineer, you will be responsible for developing sophisticated systems and software based on the customer s business goals, needs and general business environment creating software solutions. You will: Contribute to the design and architecture of high-quality, complex systems and software/storage environments Prepare, review and evaluate software/storage specifications for products and systems Contribute to the development and implementation of test strategies for complex software products and systems/for storage products and systems Take the first step towards your dream career Every Dell Technologies team member brings something unique to the table. Here s what we are looking for with this role: Essential Requirements Experience in FPGA systems design and verification with Verilog coding, System Verilog, and VHDL coding practices. Experience in UVM Verification framework, Assertion based Verification, Code coverage, Unit level simulations. Experience in E2E bench setup and HW validation. Very strong debugging skills Experience in RTL Design Digital Design Principles and peripheral protocol. Strong fundamentals in both analog and digital design practices with a desire to share knowledge and mentor others Experience and deep knowledge of hardware and software interactions, and ability to apply this understanding to resolve issues. Desirable Requirements 8-12 years of relevant experience or equivalent combination of education and work experience Experience in MATLAB and Simulink modelling for 5G flow Application closing date: 20 July 2025

Grow with us We are starting a new Silicon R&D center in Bangalore. Join our team as we pioneer the IPs that power the digital ASICs of tomorrows mobile standards. Ericsson System on a Chip (SoC) devices are custom-made for mobile networks and spans across the Ericsson Radio System - RAN Compute, Radio and Transport - to enable communication service providers to surpass the expectations of their end-customers. At our state-of-the-art design centers, we dont just follow industry trends we set them. By leveraging cutting-edge tools and methodologies, we lead innovation in the telecommunications sector. As a valued team member, youll play a pivotal role in shaping the future of global connectivity, contributing to the advancement of 5G and 6G technologies. As part of our global R&D organization, youll collaborate with talented teams across Sweden, the US, and beyond. We are committed to fostering a collaborative and innovative work environment that encourages creativity and teamwork. What We Offer: Creative Freedom: Immerse yourself in an environment that champions innovation and critical thinking. Youll have the opportunity to explore advanced design technologies alongside skilled experts. Global Impact: Contribute to projects with far-reaching impacts, transforming industries, advancing digital economies, and enhancing communication worldwide. Work-Life Balance: We prioritize the well-being of our team members, offering a balanced work-life environment to help you excel professionally without compromising your personal life. Professional Growth: Engage in continuous learning opportunities, tackle exciting challenges, and collaborate with brilliant minds in a supportive and forward-thinking atmosphere. What you will do Key Responsibilities: Develop ASIC IP blocks and subsystems, contributing to the advancement of 5G and 6G communication technology. Take full ownership of a design, whether at the block or subsystem level. Generate comprehensive documentation throughout the design lifecycle. Perform digital design and conduct all RTL sign-off checks. Continuously enhance and optimize design methodologies and processes. Collaborate with IP Architects to break down requirements and create detailed IP architecture and design specifications. Work closely with verification engineers to review and refine verification plans. Build competence in the technical domain. Engage in cross-team collaboration to ensure successful project delivery. Required Qualifications: Bachelor s degree in electrical or computer engineering. 5+ years industry experience in ASIC design. Additional experience will allow placement at higher job levels. Strong Experience in/with: Understanding of ASIC technology, design environments, and methodologies. SystemVerilog RTL static sign-off tools such as SpyGlass. Scripting languages like TCL, Python, or similar. SystemVerilog Assertions. The skills you bring Additional Requirements: Experience with Cadence and Synopsys front-end and middle-end design suites. Team-oriented, prioritizing team success within the team, across teams, and across sites over individual results. Specifically, experienced at communicating and meeting expectations within and across teams in an agile environment. High attention to detail and commitment to quality. Strong focus on meeting project deadlines and deliverables. Proficient in English, with strong communication skills. Preferred Skills: Understanding of radio access systems and their components. Expertise in low-power design, including specifying power intent using UPF or similar standards. Working knowledge of systems for continuous integration (e.g., Jenkins), simulation and analysis environments (e.g., Simscope), issue-tracking (e.g., Jira). Experience designing one or more of the following hardware domains: AMBA-based designs especially AXI and CHI. ARM-based real-time microcontroller systems including their control and interface peripherals. Wireless infrastructure specific protocols and interfaces and protocols. Implementation of hardware-based digital signal processing systems (filters, adaptation, etc.) Why join Ericsson? What happens once you apply? Primary country and city: India (IN) || Bangalore Req ID: 768630

SE NIOR SILICON DESIGN ENGINEER THE ROLE: The focus of this role is to plan, implement, and execute the Physical design and verification of processing subsystems IP, resulting in meeting the signoff criteria for tapeout. THE PERSON: You have a passion for modern, complex processor architecture, digital design, and Implementation in general. You are a team player who has excellent communication skills and experience collaborating with other engineers located in different sites/ timezones . You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems. PREFERRED EXPERIENCE: 5+ Years of experience in relevant domain. Experienced with Blocklevel and Toplevel Physical implementation. Good understanding and hands-on experience in Lower node technologies. (7nm/5nm or below) Preferably working on Lowpower or processor designs. Proficient in Working with various EDA tools. Innovus, Fusion compiler/ICCompiler2, Primetime etc.., Scripting language experience: Perl, Ruby, Makefile , shell preferred. Exposure to leadership or mentorship is an asset ACADEMIC CREDENTIALS: Bachelors or Masters degree in computer engineering/Electrical Engineering #LI-SR4 Benefits offered are described: AMD benefits at a glance .

About Marvell . Your Team, Your Impact Built on decades of expertise and execution, Marvell s custom Processor/ASIC solution offers a differentiated approach with a best-in-class portfolio of data infrastructure intellectual property (IP) and a wide array of flexible business models. In this unique role, you ll have the opportunity to work on both the physical design and methodology for future designs of our next-generation, high-performance processor chips in a leading-edge CMOS process technology, targeted at server, 5G/6G, and networking applications. What You Can Expect This role is based in Bangalore - India. You will work with both local and global team members on the physical design of complex chips as well as the methodology to enable an efficient and robust design process. This position also provides an exciting platform to engage with diverse engineering challenges within a collaborative and innovative environment at Marvell. Key responsibilities include: Work with design teams across various disciplines such as Digital/RTL/Analog to ensure design convergence and integration in a timely manner. Implement/support designs with multi-voltage designs through all aspects of implementation (place and route, static timing, physical verification) using industry standard EDA tools. Work with RTL design teams to drive assembly and design closure. Provide technical direction, coaching, and mentoring to junior employees and colleagues when necessary to achieve successful project outcomes. Write scripts in Shell, Python, and TCL to extract data and achieve productivity enhancements through automation. What Were Looking For To be successful in this role you must: Bachelor s, Master s, or PhD degree in Electrical Engineering, Computer Engineering, or a related field. 9+ years of progressive experience in back-end physical design and verification. Expertise in full-chip & sub-hierarchy integration. Experience integrating and taping out large designs utilizing a digital design environment. Good understanding of RTL to GDS flows and methodology. Good scripting skills in Perl, tcl and Python. Good understanding of digital logic and computer architecture Knowledge of Verilog. Good communication skills and self-discipline contributing in a team environment. Experience with multi-voltage and low-power design techniques is a plus. Experience with Cadence Innovus is preferred. Additional Compensation and Benefit Elements With competitive compensation and great benefits, you will enjoy our workstyle within an environment of shared collaboration, transparency, and inclusivity. We re dedicated to giving our people the tools and resources they need to succeed in doing work that matters, and to grow and develop with us. For additional information on what it s like to work at Marvell, visit our Careers page. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status. #LI-MN1