Memory Layout Engineer Nivansys Technologies

3.0 - 8.0 years

3 - 5 Lacs

bengaluru

Work from Office

1 Job Description for Memory Layout Location: Bangalore Experience : 3yrs-10 Yrs - Memory leaf cell layout development - Migration of layout from one tech node to another - Block and top level integration - Quality and timely delivery - EM-IR, area intensive layouts, Quality checks (QC) - Understanding of design rules for 90nm and below - Understanding of design rules for 14ff and 16ff is a plus. - Drive multiple projects and provide necessary technical guidance to the engineers - Understanding of DFM and DFY - Understanding of memory compiler architectures - Good debugging skills - Knowledge of scripting in PERL/Shell/TCL scripting etc - Proficient with tools like Cadence Virtuoso, Calibre ...

Posted 1 week ago

AI Match Score

Apply

Physical Design Engineer/Lead SoCtronics

5.0 - 10.0 years

0 Lacs

hyderabad, telangana

On-site

As an experienced Physical Design Engineer, you will be responsible for executing block level P&R and Timing closure activities. Your primary role will involve owning up block level P&R and performing Netlist2GDS on blocks. You will be working on the implementation of multimillion gate SoC designs in cutting-edge process technologies such as 28nm, 16nm, 14nm, and below. Your expertise should cover various aspects of physical design, including Synthesis, Floor Planning, Power Plan, Integrated Package and Floorplan design, Place and Route, Clock Planning and Clock Tree Synthesis, complex analog IP integration, Parasitic Extraction, Timing Closure, Power / IR Drop (Static and Dynamic), Signal I...

Posted 3 weeks ago

AI Match Score

Apply

CPU Physical Verification Engineer Qualcomm

5.0 - 9.0 years

0 Lacs

karnataka

On-site

**Role Overview:** As a Qualcomm Hardware Engineer at Qualcomm India Private Limited, you will be involved in planning, designing, optimizing, verifying, and testing electronic systems. You will work on a variety of systems including circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems to develop cutting-edge products. Collaboration with cross-functional teams will be essential to meet performance requirements and deliver innovative solutions. **Key Responsibilities:** - Excellent understanding of PV rules such as DRC, LVS, Antenna, Density, DFM, DFY, DPT at lower technology nodes and capable of resolving these issue...

Posted 1 month ago

AI Match Score

Apply

Physical Design Engineer/Lead SoCtronics

5.0 - 10.0 years

0 Lacs

hyderabad, telangana

On-site

You will be responsible for executing block level P&R and Timing closure activities, including owning up block level P&R and performing Netlist2GDS on blocks. You will work on the implementation of multimillion gate SoC designs in cutting edge process technologies such as 28nm, 16nm, 14nm, and below. Your role will require strong hands-on expertise in physical design aspects like Synthesis, Floor Planning, Power Plan, Integrated Package and Floorplan design, Place and Route, Clock Planning, Clock Tree Synthesis, complex analog IP integration, Parasitic Extraction, Timing Closure, Power / IR Drop (Static and Dynamic), Signal Integrity Analysis, Physical Verification (DRC, ERC, LVS), DFM, and ...

Posted 3 months ago

AI Match Score

Apply

Start Your Job Search Today

Browse through a variety of job opportunities tailored to your skills and preferences. Filter by location, experience, salary, and more to find your perfect fit.