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Lead Design Engineer Cadence

5.0 - 7.0 years

0 Lacs

hyderabad, telangana, india

On-site

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. Role : Lead Design Engineer, Digital Physical Desing Responsibilities Block level Netlist to GDS delivery Subsystem level floorplan, PnR and timing closure FCFP/FCI/FCT activities - Full Chip Floor planning, Full chip Integration, Full Chip timing Leading/Guiding a team of 2-3 Engineers Required Skills 5+ years of experience in PnR and STA Handson experience in RTL/Netlist to GDS delivery of blocks Good understanding of DFT stitching and clock tree strategies Strong at density and congestion issues resolution Complex blocks floorplan, PnR and STA such as DDRIP. PCIE IP Capable of doi...

Posted 2 months ago

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