STA Engineer (Static Timing Analysis) Zafify

3.0 - 8.0 years

0 Lacs

noida, uttar pradesh, india

On-site

JD - Domain :: STA (Static Timing Analysis) Work Experience :: 3 8 years Location :: Noida Tool Expertise :: PrimeTime & PT-ECO Technical Expertise :: Block level Timing Constraints generation, enablement & analysis across Functional & DFT modes ; Clocking & Data flow understanding ; Good in interaction with Design (FE) & DFT teams for better understanding ; Well versed in reviewing check timing and Constraints QoR checks + Constraints Validation understanding ; Able to interact with Implementation team counterparts for block timing closure ; CTS building understanding along with Clock Tree spec review/closure ; Timing ECOs & Final Timing last mile closure at block level ; Scripting like TCL...

Posted 1 month ago

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DFT Design Engineer Evnek

12.0 - 15.0 years

6 - 10 Lacs

hyderabad, bengaluru, delhi / ncr

Work from Office

What youll have 12+ Years of experience in developing and implementing DFT architecture and test strategies for complex ASIC/SoC Designs In-Depth knowledge and hands-on experience of industry standard and proprietary DFT techniques, such as, SCAN/ATPG, Built-in-Self Test (MBIST/LBIST) Architecture , JTAG (IEEE 1149.x/1500/1687), Boundary Scan (BSCAN) and compression/decompression technologies on Digital and Mixed Signal SoCs In-Depth knowledge of EDA tools used for DFT, especially Mentor/Synopsys tools Scripting expertise in Python/PERL, TCL, etc Experience in RTL coding and SDC creation for DFT Modes Recent Tapeout experience in advanced nodes Location: Remote- Bengaluru,Hyderabad,Delhi / N...

Posted 3 months ago

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