6 Dft Methodology Jobs

As an engineer of the Software Quality Assurance (QA) team at NVIDIA, you will play a crucial role in ensuring the quality of CAD tools and flows for semiconductor products. Your responsibilities will include: - Providing hardware, software, and lab support for testing and validation processes. - Architecting highly automated and customizable Software Quality processes for design flows using software engineering techniques. - Crafting feature test plans, identifying test cases based on user requirements, and automating testing. - Maintaining regression testing frameworks and developing test reporting mechanisms. - Performing code reviews, static analysis, and dynamic testing. - Delivering hi...

Role Overview: Sandisk is looking for a highly skilled and experienced DFT Engineer to join their dynamic team of engineers in developing the next-generation Flash Controllers. As an SoC DFT Engineer, you will be responsible for defining and implementing industry-leading DFT solutions, with a focus on SCAN, MBIST, BSDL, and more. The ideal candidate should have a deep understanding of DFT Architecture, Implementation flow, MBIST, SCAN ATPG, and Simulation expertise. Key Responsibilities: - Define DFT Architecture for SoC development - Lead complex activities and provide solutions for intricate DFT problems - Collaborate with cross-functional teams to define and refine SoC DFT requirements, e...

Job Description ROLE & RESPONSIBILITIES: Incumbent will be responsible for Scan insertion and validation, BIST, MBIST insertion and validation, ATPG, IP Tests and Pattern validation w/wo Timing, DFT mode timing Analysis and sign off. Be responsible for a comprehensive DFT plan. Incumbent to work with DFT and cross functional teams. To architect and implement solutions for Scan and built-in self-test (Memory and Logic BIST) circuitry to test devices in the field. ESSENTIAL SKILLS & EXPERIENCE: Strong fundamentals on DFT and ASIC cycle. Sound expertise in Tcl, Perl, Shell scripting. Technically sound & good team player. Hands-on experience with DFT implementation using standard EDA and flow is...

At Cadence, we are seeking a talented individual to join our team and contribute to the world of technology. In this role, you will collaborate closely with various cross-functional teams across different locations to ensure alignment on project goals and deliverables. Your responsibilities will also include mentoring junior engineers, fostering innovation, and driving automation initiatives. The ideal candidate should hold a BE/B.Tech/M.E/M.Tech degree with at least 7 years of relevant work experience. A strong understanding of Design for Testability (DFT) concepts and excellent communication skills are essential. Additionally, hands-on experience with industry-standard EDA tools and logic ...

You are invited to join our team at Sandisk as a DFT Engineer, where you will play a crucial role in developing the next-generation Flash Controllers. As an SoC DFT Engineer, your primary responsibility will be to define and implement cutting-edge DFT solutions, focusing on SCAN, MBIST, BSDL, and other key aspects. The ideal candidate should possess a profound understanding of DFT Architecture, Implementation flow, MBIST, SCAN ATPG, and Simulation expertise. As a DFT Engineer at Sandisk, you will be involved in various essential duties and responsibilities, including: - Defining DFT Architecture for SoC development. - Leading complex activities and offering solutions for intricate DFT proble...

Location :- Bangalore Experience :- 12-20 years Required Skills And Experience: This role is for a Principal DFT engineer with 15 years plus experience Technical leadership in DFT and ability to train/work with junior team members Experience with Perl, TCL, and/or python with ability to build and deploy generic DFT flows Proficient in Unix/Linux environments One or more core DFT skills are considered crucial for this position including some of the following Knowledge of at-speed testing, test insertion and test coverage assessment, test pattern development, scan compression, Memory BIST, Logic BIST, JTAG, IJTAG, fault simulation, debug, verification, SSN, designing and conducting experiments...