1105 Dft Jobs - Page 9

Job Summary: We are seeking a skilled and detail-oriented PCB Design Engineer to join our engineering team. The ideal candidate will be responsible for designing and developing high-quality printed circuit boards (PCBs) that meet performance, reliability, and manufacturability standards for a variety of electronic products. Key Responsibilities: Design multilayer PCBs from schematic to final layout using CAD tools such as Altium Designer, Eagle, OrCAD, or KiCad. Collaborate with electrical engineers and mechanical designers to ensure PCB layouts meet system and enclosure requirements. Perform component placement, routing, and DFM/DFT (Design for Manufacturing/Testing) checks. Generate fabrication and assembly drawings, Gerber files, and BOMs. Review and incorporate design changes during the product development cycle. Conduct signal integrity, thermal, and EMC considerations during layout. Work with manufacturing partners to resolve fabrication or assembly issues. Required Qualifications: Diploma / Bachelor’s degree in Electronics Engineering, Electrical Engineering, or a related field. Proven experience in PCB layout and design ( 2-3 years ). Proficiency with PCB CAD tools (Altium, Eagle, OrCAD, KiCad, etc.). Understanding of IPC standards and PCB fabrication processes. Strong understanding of circuit design, component footprints, and electronic schematics. Familiarity with high-speed design, power delivery, and grounding techniques. Job Type: Full-time Pay: ₹14,156.69 - ₹35,000.00 per month Benefits: Health insurance Leave encashment Paid sick time Provident Fund Work Location: In person

Job Description – Sr Quality Engineer (Engineering/Manufacturing – Solids & Automation Technologies) Job Title: Senior Quality Engineer – Fabrication, Welding, Assembly, FAT & Trials Department: Quality Assurance / Quality Control Reporting To: Quality Manager Location: [Insert Location] Job Purpose: To oversee the quality of fabrication, welding, in-process activities, assembly, Factory Acceptance Tests (FAT), and performance trials. Ensure that all engineering equipment and systems meet technical, dimensional, and functional specifications before delivery to customers. Key Responsibilities:1. Fabrication & Welding Quality · Inspect fabricated components such as screw conveyors, silos, hoppers, bin activators, mixers, and ducting assemblies. · Verify dimensional accuracy, fit-up, and visual standards of fabricated parts as per engineering drawings. · Monitor welding operations: WPS adherence, weld joint preparation, root pass inspection, and final weld finish. · Identify weld defects (undercut, porosity, cracks) and coordinate repair and rework. 2. In-Process & Stage-Wise Inspection · Conduct in-process inspection during sub-assembly and fabrication stages. · Approve key checkpoints before moving items to next process (machining, painting, assembly). · Ensure quality plans/checklists are followed at each stage. · Maintain records of stage inspections and deviations. 3. Assembly & Functional Testing · Inspect final assembly of mechanical, pneumatic, and automation components. · Validate alignment, fitment, bolt torqueing, sensor mounting, and panel connections. · Ensure component-level and system-level checks (e.g., valve actuation, screw rotation, mixer blade clearance). · Check cleanliness, painting, and aesthetic finish. 4. Factory Acceptance Testing (FAT) & Trials · Coordinate and conduct FAT along with customer and project teams. · Prepare FAT checklist, protocols, and test setup in advance. · Ensure trial operation (dry or live test) for screw conveyors, mixers, vibrators, diverter valves, etc. · Log performance parameters, vibrations, leakage, and function test results. · Get client sign-off and ensure all test certificates are filed. 5. Non-Conformance & Corrective Actions · Raise NCRs for fabrication defects, weld failures, or functional non-conformities. · Collaborate with production for immediate rework or rectification. · Support root cause analysis and implement CAPA. · Track NCR closure and update quality reports. 6. Documentation & Reporting · Prepare inspection reports, weld maps, FAT protocols, calibration logs, and quality dossiers. · Ensure traceability of materials and components used in assemblies. · Support internal audits and client document submission. · Maintain equipment-wise and project-wise quality records. Key Skills & Competencies: · In-depth understanding of fabrication, welding (MIG, TIG, ARC), and assembly processes. · Skilled in interpreting fabrication drawings, weld symbols, and GD&T. · Proficient in using inspection instruments: vernier, gauges, DFT meter, spirit level, welding fillet gauges, etc. · Knowledge of WPS, PQR, visual inspection techniques, and dimensional QC. · FAT coordination, trial testing and client-facing inspection experience. · Strong documentation, NCR management, and communication skills. Qualifications & Experience: · Education: Diploma / B.E. in Mechanical or Production Engineering. · Experience: 5–8 years in quality inspection of fabricated engineering equipment with hands-on exposure to welding, assembly, and FAT. Working Conditions: · Shopfloor-based role with regular exposure to fabrication, welding, and trial areas. · Coordination with design, production, and project teams. · Involvement in client inspections and FATs. · May include extended hours or urgent support during trials or dispatch readiness. Job Types: Full-time, Permanent Pay: ₹25,000.00 - ₹30,000.00 per month Benefits: Provident Fund Work Location: In person

Primary skills: ASIC / DFT / Simulation / Validation Mandatory skills: VLSI Design For Testability - DFT & worked in at least one Full chip DFT Experience with tools: ATPG - TestKompress, MBIST - MentorETVerify, Simulation - VCS (preferred), ModelSim

We are seeking highly motivated DFT engineer to be part of Hardware team. Join a great team of engineering professionals who are involved in development, validation, and delivery of DFT patterns for IBM’s chip design team. As a member of DFT team you will be required but not restricted to pattern generation, simulation, validation, characterization, delivery to TAE, IBM’s Hardware Bring-up and Silicon Debug. You will play a key role in silicon bring-up, workload execution and validation. Required education Bachelor's Degree Preferred education Master's Degree Required technical and professional expertise Proficiency inC and Pythonfor validation and automation Hands on experiencec in Writing/ maintaining test programs and automation scripts using C and Python Experience in chip bring-up /debug Experience in chip-level throttling issuesincluding power, thermal, and frequency-related behavior Knowledge on Analyzing trace data/logs and on-chip debug outputs for failure root cause Should be able to InterpretVerilog RTLto support functional and performance debug Collaborate with RTL, firmware, validation, and DFT teams for end-to-end issue resolution Strong understanding ofchip boot flowsandbring-up sequences Familiarity withassembly-level debuggingon RISC/V, ARM, or other architectures Ability to read and debugVerilog RTL code In depth understanding of chip internals, including resets, clocking, and register programming Preferred technical and professional experience Experience inpost-silicon validation, emulation or pre-silicon environments Exposure to firmware-hardware interactions Knowledge of debug infrastructure and on-chip monitoring tools Familiarity with version control tools like Git

Company Description Renesas is one of the top global semiconductor companies in the world. We strive to develop a safer, healthier, greener, and smarter world, and our goal is to make every endpoint intelligent by offering product solutions in the automotive, industrial, infrastructure and IoT markets. Our robust product portfolio includes world leading MCUs, SoCs, Analog and power products, plus Winning Combination solutions that curate these complementary products. We are a key supplier to the world’s leading manufacturers of electronics you rely on every day; you may not see our products, but they are all around you. Renesas employs roughly 21,000 people in more than 30 countries worldwide. As a global team, our employees actively embody the Renesas Culture, our guiding principles based on five key elements: Transparent, Agile, Global, Innovative, and Entrepreneurial. Renesas believes in, and has a commitment to, diversity and inclusion, with initiatives and a leadership team dedicated to its resources and values. At Renesas, we want to build a sustainable future where technology helps make our lives easier. Join us and build your future by being part of what’s next in electronics and the world. Job Description Collaborate with system architects and micro-architects to define high-level, implementable SoC specifications. Own end-to-end SOC RTL delivery while analysing and optimizing design for power, performance, and area (PPA) targets. Influence SoC definition, features, and adopt physical design friendly partitioning. Lead RTL design and integration of multi-subsystem SoCs, supporting complex architectures with multi-core, multi-power, and multi-reset domains. Demonstrate strong proficiency with front-end flows, including Lint, CDC, low-power (UPF) checks, synthesis, DFT, and Static Timing Analysis (STA). Drive the development of robust Safety, Security, and Debug architectures for advanced SoCs with multiple interconnects. Design and integrate standard interface protocols such as AHB, AXI, CHI, and memory interfaces including ROM, RAM, Flash, LPDDR/DDR3/4. Engage cross-functionally with DFT, physical design, verification, emulation, and validation teams to ensure first-time-right silicon and on-time project delivery. Support post-silicon debug, bring-up, and validation, working closely with lab and silicon validation teams. Continuously evaluate and adopt new design methodologies and best practices to improve productivity and shift-left the design cycle. Mentor junior engineers, review their work, and provide technical leadership and guidance across multiple design projects. Provide overall leadership and tracking of the team’s goals. Contribute to the innovation quotient of the team via Desing Patents, Industry Standard Publications, AI-enabled design methodologies etc. Qualifications M.Tech/ B.Tech in Electrical Engineering or Computer Science with 12+ years of RTL design experience. Proven expertise in Verilog/SystemVerilog RTL design, integration, and microarchitecture. Strong understanding of SoC architecture, AMBA protocols (AXI, AHB, APB), clock/power domains, and memory subsystems. Experience with EDA tools for synthesis, lint, CDC, RDC, and timing analysis. Familiarity with UPF/low-power design, formal verification techniques, and static/dynamic checks. Excellent leadership, communication, and project management skills. Experience working with global cross-functional teams. Additional Information Renesas is an embedded semiconductor solution provider driven by its Purpose ‘ To Make Our Lives Easier .’ As the industry’s leading expert in embedded processing with unmatched quality and system-level know-how, we have evolved to provide scalable and comprehensive semiconductor solutions for automotive, industrial, infrastructure, and IoT industries based on the broadest product portfolio, including High Performance Computing, Embedded Processing, Analog & Connectivity, and Power. With a diverse team of over 21,000 professionals in more than 30 countries, we continue to expand our boundaries to offer enhanced user experiences through digitalization and usher into a new era of innovation. We design and develop sustainable, power-efficient solutions today that help people and communities thrive tomorrow, ‘ To Make Our Lives Easier .’ At Renesas, You Can Launch and advance your career in technical and business roles across four Product Groups and various corporate functions. You will have the opportunities to explore our hardware and software capabilities and try new things. Make a real impact by developing innovative products and solutions to meet our global customers' evolving needs and help make people’s lives easier, safe and secure. Maximize your performance and wellbeing in our flexible and inclusive work environment. Our people-first culture and global support system, including the remote work option and Employee Resource Groups, will help you excel from the first day. Are you ready to own your success and make your mark? Join Renesas. Let’s Shape the Future together. Renesas Electronics is an equal opportunity and affirmative action employer, committed to supporting diversity and fostering a work environment free of discrimination on the basis of sex, race, religion, national origin, gender, gender identity, gender expression, age, sexual orientation, military status, veteran status, or any other basis protected by law. For more information, please read our Diversity & Inclusion Statement.

Company Description Renesas is one of the top global semiconductor companies in the world. We strive to develop a safer, healthier, greener, and smarter world, and our goal is to make every endpoint intelligent by offering product solutions in the automotive, industrial, infrastructure and IoT markets. Our robust product portfolio includes world leading MCUs, SoCs, Analog and power products, plus Winning Combination solutions that curate these complementary products. We are a key supplier to the world’s leading manufacturers of electronics you rely on every day; you may not see our products, but they are all around you. Renesas employs roughly 21,000 people in more than 30 countries worldwide. As a global team, our employees actively embody the Renesas Culture, our guiding principles based on five key elements: Transparent, Agile, Global, Innovative, and Entrepreneurial. Renesas believes in, and has a commitment to, diversity and inclusion, with initiatives and a leadership team dedicated to its resources and values. At Renesas, we want to build a sustainable future where technology helps make our lives easier. Join us and build your future by being part of what’s next in electronics and the world. Job Description Collaborate with system architects and micro-architects to define high-level, implementable SoC specifications. Own end-to-end SOC RTL delivery while analysing and optimizing design for power, performance, and area (PPA) targets. Influence SoC definition, features, and adopt physical design friendly partitioning. Lead RTL design and integration of multi-subsystem SoCs, supporting complex architectures with multi-core, multi-power, and multi-reset domains. Demonstrate strong proficiency with front-end flows, including Lint, CDC, low-power (UPF) checks, synthesis, DFT, and Static Timing Analysis (STA). Drive the development of robust Safety, Security, and Debug architectures for advanced SoCs with multiple interconnects. Design and integrate standard interface protocols such as AHB, AXI, CHI, and memory interfaces including ROM, RAM, Flash, LPDDR/DDR3/4. Engage cross-functionally with DFT, physical design, verification, emulation, and validation teams to ensure first-time-right silicon and on-time project delivery. Support post-silicon debug, bring-up, and validation, working closely with lab and silicon validation teams. Continuously evaluate and adopt new design methodologies and best practices to improve productivity and shift-left the design cycle. Mentor junior engineers, review their work, and provide technical leadership and guidance across multiple design projects. Provide overall leadership and tracking of the team’s goals. Contribute to the innovation quotient of the team via Desing Patents, Industry Standard Publications, AI-enabled design methodologies etc. Qualifications M.Tech/ B.Tech in Electrical Engineering or Computer Science with 12+ years of RTL design experience. Proven expertise in Verilog/SystemVerilog RTL design, integration, and microarchitecture. Strong understanding of SoC architecture, AMBA protocols (AXI, AHB, APB), clock/power domains, and memory subsystems. Experience with EDA tools for synthesis, lint, CDC, RDC, and timing analysis. Familiarity with UPF/low-power design, formal verification techniques, and static/dynamic checks. Excellent leadership, communication, and project management skills. Experience working with global cross-functional teams. Additional Information Renesas is an embedded semiconductor solution provider driven by its Purpose ‘ To Make Our Lives Easier .’ As the industry’s leading expert in embedded processing with unmatched quality and system-level know-how, we have evolved to provide scalable and comprehensive semiconductor solutions for automotive, industrial, infrastructure, and IoT industries based on the broadest product portfolio, including High Performance Computing, Embedded Processing, Analog & Connectivity, and Power. With a diverse team of over 21,000 professionals in more than 30 countries, we continue to expand our boundaries to offer enhanced user experiences through digitalization and usher into a new era of innovation. We design and develop sustainable, power-efficient solutions today that help people and communities thrive tomorrow, ‘ To Make Our Lives Easier .’ At Renesas, You Can Launch and advance your career in technical and business roles across four Product Groups and various corporate functions. You will have the opportunities to explore our hardware and software capabilities and try new things. Make a real impact by developing innovative products and solutions to meet our global customers' evolving needs and help make people’s lives easier, safe and secure. Maximize your performance and wellbeing in our flexible and inclusive work environment. Our people-first culture and global support system, including the remote work option and Employee Resource Groups, will help you excel from the first day. Are you ready to own your success and make your mark? Join Renesas. Let’s Shape the Future together. Renesas Electronics is an equal opportunity and affirmative action employer, committed to supporting diversity and fostering a work environment free of discrimination on the basis of sex, race, religion, national origin, gender, gender identity, gender expression, age, sexual orientation, military status, veteran status, or any other basis protected by law. For more information, please read our Diversity & Inclusion Statement.

You will need a Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience. Additionally, you should have at least 4 years of experience with digital logic design principles, RTL design concepts, and languages such as Verilog or SystemVerilog. It is also essential to have experience in the design and development of Security or Audio blocks, as well as with a scripting language like Perl or Python. Familiarity with DSI2 or MIPI C/D Phy is necessary. Ideally, you should have a Master's or PhD degree in Electrical Engineering, Computer Engineering, or Computer Science. Preferred qualifications include experience with ASIC or FPGA design verification, synthesis, timing/power analysis, and DFT. Knowledge of high-performance and low-power design techniques, assertion-based formal verification, FPGA and emulation platforms, and SOC architecture is also beneficial. As a part of the team working on custom silicon solutions for Google's direct-to-consumer products, you will play a crucial role in shaping the future of hardware experiences. Your contributions will drive innovation behind products that are beloved by millions worldwide, delivering exceptional performance, efficiency, and integration. The Platforms and Devices team at Google focuses on various computing software platforms and first-party devices and services. By researching, designing, and developing new technologies, the team aims to enhance user interaction with computing, making it faster and more seamless, and creating innovative experiences for users globally. Your responsibilities will include collaborating with architects to develop microarchitecture, performing Verilog/SystemVerilog RTL coding, functional/performance simulation debugging, and conducting Lint/CDC/FV/UPF checks. You will also participate in test planning and coverage analysis, develop RTL implementations meeting power, performance, and area goals, and be involved in synthesis, timing/power closure, pre-silicon, and post-silicon bring-up. Additionally, you will create tools/scripts to automate tasks, track progress, and collaborate with multi-disciplined, multi-site teams in Architecture, RTL design, verification, DFT, and Partner Domains.,

As a member of the Cadence team, you will have the opportunity to contribute to the world of technology by designing and implementing DFT IP using Verilog/SystemVerilog and/or VHDL. Your responsibilities will include designing and implementing RTL for DFT IP, including POST and IST. You will play a key role in developing synthesis automation for DFT IP, which involves synthesis and timing constraints, RTL insertion, and verification. Additionally, you will be responsible for owning, maintaining, extending, and enhancing existing DFT IP such as LBIST. Join us in our mission to make a difference in the technology industry. Be a part of our team and help us tackle challenges that others cannot.,

Roles and Responsibility Experience in Subsystem or SoC verification and experience including C based test cases development Experience in IP verification using UVM Exposure to all stages of verification: requirements collection, verification plans, testbench implementation, test case development and coverage closure Good Problem Solving and Debugging skills. Experience with ARM-based designs, AMBA APB, AXI, CHI, and Cache coherency concepts Porting peripheral driver software for SoC test cases. Experienced in GLS, DFT/DFD, Power Aware verification techniques

Roles and Responsibility Senior IO-MMU Design Engineer Role Overview: Leads the design and integration of IO Memory Management Units (IO-MMUs) for secure, virtualized, and high-performance SoC architectures. Key Responsibilities: Architect and implement RTL for IO-MMU subsystems Define IO translation and access control logic Collaborate with SoC, interconnect, and virtual memory teams Ensure compliance with IOMMU standards (SMMU, PCIe ATS/PRI, RMRR) Deliver Lint, CDC, synthesis, and DFT clean designs Required Skills: 8+ years of experience in SoC and IP-level RTL design Strong in SystemVerilog, with knowledge of memory protection and address translation Experience with SoC virtual memory systems and PCIe/AXI protocols Familiar with coherency, TLB, page walk and IOVA mechanisms Skilled in timing closure and formal/CDC tools

Roles and Responsibility Experience: 6 - 15 years Responsibilities: Verification engineer with a knowledge of SoC integration verification, SoC scenario verification, SoC performance verification, CHI/DDRx/LPDDRx/AI accelarator integration verification in SoC RTL. Your key responsibilities will include writing test plans, defining test methodologies, developing C based software tests, SystemVerilog/Verilog testbenches and tests, and debugging of test failures and issues. Working with project management and leads on planning tasks, schedules, and reporting progress Collaborate with engineers from other teams including architecture, design, implementation, modelling, performance analysis, silicon validation, FPGA and board development Required Skills and Experience : Proven understanding of digital hardware verification language Verilog/Systemverilog HDL Experience in SoC verification using Embedded Low-level programming including C/C++ tests and assembly language(preferably ARM) Experienced in one or more of various verification methodologies - UVM/OVM, formal, power aware verification, emulation Exposure to all stages of verification: requirements collection, creation of verification methodology plans, test plans, testbench implementation, test case development, documentation, and support Good Problem Solving and Debugging skills. Knowledge of SoC Verification Flow and strategy. Experience with ARM-based designs and/or ARM System Architectures, SoC Boot flow, Cache coherency Porting peripheral driver software for SoC tests Clock Domain Crossing verification Experienced in GLS, DFT/DFD, Experienced in UPF Power Aware verification Automation experience with shell programming/scripting (g. Tcl, Perl, Python etc.)

Hiring now Criteria - B.Tech below 2022 and M.Tech below 2024 Location - Bangalore Preferred Engineers who have completed their Training in #VLSI domains for below requirements #PD #AL #RTL #DFT Share profiles to kartikchandu@juntrantech.com Health insurance Provident fund

Overview: WHAT YOU DO AT AMD CHANGES EVERYTHING We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences – the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world’s most important challenges. We strive for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives. AMD together we advance_ Responsibilities: AECG ASIC DFX - SMTS SILICON DESIGN ENGINEER T HE ROLE : AECG SSD ASIC is a centralized ASIC design group within AMD’s Adaptive and Embedded Computing Organization. The group consists of design teams located in several AMD locations in North America and Asia. It is primarily responsible for architecture, design, and implementation of critical Design-for-Test (DFT) and Design-for-Debug (DFD) features for cutting edge AMD products. As a member of the AECG SSD ASIC Group, you will help bring to life cutting-edge designs. As a member of the DFT design/integration team, you will work closely with the architecture, IP design, Physical Design teams, and product engineers to achieve first pass silicon success. THE PERSON: A successful candidate will work with senior silicon design engineers. The candidate will be highly accurate and detail-oriented, possessing good communication and problem-solving skills. K EY RESPONSIBLITIES : Implementation and verification of DFT architecture and features Scan insertion and ATPG pattern generation ATPG patterns verification with gate-level simulation Test coverage and test cost reduction analysis Post silicon support to ensure successful bring up and enhance yield learning Working with a multi-functional and cross-GEOs team of engineers on DFT (design-for-test) and DFD (design-for-debug) architecture and methodology. Performing design-for-test (DFT) RTL design using architectural specifications and design generation flows Performing DFT RTL integration, synthesis, equivalency checking, timing analysis and defining constraints, verification of DFx logic at RTL and GLS. Writing and maintain DFT documentation and specifications. Developing CAD software, scripts and other support technology to enable successful construction of DFT logics in complex SoC design. Performing scan insertion, ATPG verification and test pattern generation Providing DFT feature bring-up and pattern debug support to production engineering team during first silicon bring-up, qualification and failure analysis. P REFERRED EXPERIENCE : Minimum 12 years of DFT design, integration, verification, ATPG and Silicon Debug experience. Demonstrated technical leadership and works well with cross-functional teams. Excellent communication and interpersonal skills Understanding of Design for Test methodologies and DFT verification experience (eg. IEEE1500, JTAG 1149.x, Scan, memory BIST etc.) Experience in complex ASIC design (multi-million gates) in DFT/DFD techniques such as JTAG/IEEE standards, scan and ATPG, on-chip test pattern compression and at-speed testing using PLL, memory BIST and repair, logic BIST, power-gating, on-chip debug logic, testing of high speed SerDes IO and analog design. Understanding various technologies that must work with DFT/DFD technology such as CPU’s, memory and I/O controllers, etc. Expertise in scan compression architecture, scan insertion and ATPG methodologies are essential. Working knowledge and experience in Verilog simulator and waveform debugging tools, proficiency in debugging both RTL and gate level simulations Experience in solving logic design or timing issues with integration, synthesis and PD teams. Good working knowledge of UNIX/Linux and scripting languages (e.g., TCL, c-shell, Perl), C++ programming Knowledge in EDA tools/methodology, such as synthesis, equivalency checking, static timing analysis. Knowledge of ATE and digital IC manufacturing test is a plus. Strong problem-solving skills. Team player with strong communication skills. ACADEMIC CREDENTIALS: Bachelors or Masters degree in computer engineering/Electrical Engineering #LI-RP1 Qualifications: Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

Job Description We are seeking a talented and detail-oriented Physical Backend Design Engineer to join our IC (Integrated circuit) development team. The role involves key aspects of physical design, including automated place and route, floorplanning, clock tree synthesis (CTS), static timing analysis (STA), power analysis, and physical verification (DRC/LVS). The ideal candidate will have a strong knowledge of physical design methodologies, experience with industry-standard tools, and a passion for delivering high-quality semiconductor solutions. How You Will Contribute And What You Will Learn Perform floorplanning, partitioning, and optimization to achieve area, power, and performance targets. Execute automated place and route (PnR) using industry-standard tools to generate physical layouts. Implement clock tree synthesis (CTS), ensuring low skew and efficient clock distribution. Conduct static timing analysis (STA) to verify timing closure and ensure the design meets performance requirements. Perform power analysis, including IR drop and electromigration (EM) checks, to optimize power distribution networks. Conduct physical verification tasks, including design rule checks (DRC) and layout vs. schematic (LVS) checks, to ensure manufacturability and compliance with foundry standards. Collaborate with design, verification, and DFT teams to resolve physical design challenges and improve chip performance. Work closely with foundry teams to address process technology issues and implement best practices. Key Skills And Experience You have: Bachelor’s Degree in Electrical Engineering, Computer Engineering, or a related field (Master’s preferred) 3+ years of experience in physical backend design for ICs. Complex chip designs through all stages of physical implementation Experience with tape-out of designs for advanced nodes is highly desirable Strong knowledge of physical design concepts, including place and route (PnR), clock tree synthesis (CTS), static timing analysis (STA) and power grid design Experience with physical verification tools like Cadence Pegasus or Mentor Calibre Familiarity with parasitic extraction tools (e.g., StarRC, Quantus, Calibre xRC) Scripting skills in Python, Tcl, Perl, or Shell for automation Required Tools: Cadence Innovus, Cadence Quantus, Cadence Tempus, Cadence Pegasus suite It would be nice if you also had: Experience with advanced process nodes (e.g., 7nm and below) Knowledge of low-power design techniques, such as multi-Vt, multi-Vdd, or clock gating Familiarity with DFT concepts and tools, Chip packaging and thermal analysis considerations, FinFET technology and 3D IC design methodologies About Us Come create the technology that helps the world act together Nokia is committed to innovation and technology leadership across mobile, fixed and cloud networks. Your career here will have a positive impact on people’s lives and will help us build the capabilities needed for a more productive, sustainable, and inclusive world. We challenge ourselves to create an inclusive way of working where we are open to new ideas, empowered to take risks and fearless to bring our authentic selves to work What we offer Nokia offers continuous learning opportunities, well-being programs to support you mentally and physically, opportunities to join and get supported by employee resource groups, mentoring programs and highly diverse teams with an inclusive culture where people thrive and are empowered. Nokia is committed to inclusion and is an equal opportunity employer Nokia has received the following recognitions for its commitment to inclusion & equality: One of the World’s Most Ethical Companies by Ethisphere Gender-Equality Index by Bloomberg Workplace Pride Global Benchmark At Nokia, we act inclusively and respect the uniqueness of people. Nokia’s employment decisions are made regardless of race, color, national or ethnic origin, religion, gender, sexual orientation, gender identity or expression, age, marital status, disability, protected veteran status or other characteristics protected by law. We are committed to a culture of inclusion built upon our core value of respect. Join us and be part of a company where you will feel included and empowered to succeed. About The Team Nokia Bell Labs is the world-renowned research arm of Nokia, having invented many of the foundational technologies that underpin information and communications networks and all digital devices and systems. This research has produced nine Nobel Prizes, five Turing Awards and numerous other awards.

Quality Engineer Qualification : Diploma& B.Tech In Mech Work Exp : 2-6 Year(s) Salary : 25-35K PM (No Bar for Good Candidate) Skill : All type of Micrometer, All Type of Vernier Caliper, height gauge, bevel protector, surface finishing related all instrument bore gauge, dial bore gauge, Surface roughness tester. Fabrication Knowledge welding, Drawing, coating, painting, DFT Meter, GDNT symbole In Process Inspection & Audit. Good Knowledge and Practice about Kiezen, 5S, 7 QC tools, 8D, CAPA, MSA,. Transmission Gear Shaft, Crown wheel & Pinions Bavel & Transmission Assembly. Regards Balbir Singh 7876783183 Job Types: Full-time, Permanent Pay: ₹20,000.00 - ₹35,000.00 per month Benefits: Food provided Health insurance Provident Fund Schedule: Day shift Morning shift Work Location: In person

Company Qualcomm India Private Limited Job Area Engineering Group, Engineering Group > Hardware Engineering General Summary As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. IPPD: Physical design engineer Physical Implementation activities for high performance Cores for 16/14/7/5nm or lower technologies, which includes all or some of the below. Floor-planning, Place and Route, CTS, Formal verification, Physical Verification (DRC/LVS), Low Power verification, PDN, Timing Closure and / or power optimization Exposure to PD implementation of PPA critical cores. Exposure to timing convergence of high frequency data-path intensive Cores and advanced STA concepts. Able to handle Block level PnR convergence with Synopsys ICC2/ Cadence Innovus and timing convergence in PTSI/Tempus in latest technology nodes. Understanding of clocking architecture. Tcl/Python/Perl Scripting aware for small automation Strong problem-solving skills , good communication skills and good team player Collaborate with design, DFT and PNR teams and support issue resolutions wrt constraints validation, verification, STA, Physical design, etc. Applicants : Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries). Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law. To all Staffing and Recruiting Agencies : Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications. If you would like more information about this role, please contact Qualcomm Careers. 3069942

5+ years of experience in PCB design including high-speed & high-density layouts Proficiency in PCB design tool ( Altium Designer, Cadence Allegro, Mentor Graphics) Strong knowledge of DFM, DFT standards & signal integrity principles

Job Summary: This position offers an excellent career opportunity for a computational chemist to leverage quantum chemistry skills in chemical process optimization and product development in agrochemical industry. Job Requirement Thorough understanding of DFT and ab initio electronic structure theory methods. Proficiency with Quantum Chemistry based software tools like Turbomole, Gaussian, deMon, GAMESS-US, Quantum espresso, VASP, etc. Proficiency with any of the scripting languages like Bash, Python, Perl, etc. Proficiency with working in Linux environment and high-performance computing platforms. Demonstrated experience in using electronic structure based software tools in understanding chemical reactivity and reaction mechanisms. Demonstrated experience in catalyst design is preferred. Demonstrated experience in use of data based models to optimize industrial processes is preferred. Experience in utilizing in-house experimental data and modelled parameters towards predictive modelling, statistics would be a plus. Working knowledge of classical methods like force fields and molecular dynamics simulations. Ability to work in collaborative multidisciplinary scientific environment. Ability to communicate technical results to experimentalists Educational Qualification 3+ years of postdoc or industrial experience in related field, with a PhD in Chemistry / Physics with specialization in Theoretical Chemistry / Computational Chemistry / Chemical Physics / or related discipline from a reputed University / Institute from India or overseas with excellent academic credentials.

Key Responsibilities: Collaborate on ASIC backend design activities including synthesis, place-and-route, timing analysis, and physical verification. Develop and optimize design flows using EDA tools (e.g., Synopsys, Cadence, Mentor). Perform static timing analysis (STA) and fix timing violations to meet design constraints. Conduct signal integrity analysis, power analysis, and floorplanning. Work with RTL designers to optimize designs for manufacturability and performance. Generate design documentation, scripts, and reports to support ASIC development. Support debugging and silicon validation activities. Participate in design reviews, sign-off processes, and tape-out preparation. Qualifications and Requirements: Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or related field. 3+ years of experience in ASIC backend design or physical design. Proficiency with ASIC EDA tools (e.g., Synopsys Design Compiler , IC Compiler , PrimeTime , Cadence Innovus ). Strong knowledge of ASIC design flow, timing closure, and verification. Experience with scripting languages (TCL, Perl, Python) for automation. Understanding of semiconductor process technologies and constraints. Excellent problem-solving and communication skills. Desirable Skills: Experience with low-power design techniques and methodologies. Familiarity with DFT (Design for Test) insertion and ATPG tools. Knowledge of mixed-signal ASIC design is a plus. Exposure to RTL design and verification flows. Experience with FPGA prototyping and emulation.

Qualcomm India Private Limited is a leading technology innovator that is committed to pushing the boundaries of what's possible. We strive to enable next-generation experiences and drive digital transformation to create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will be responsible for planning, designing, optimizing, verifying, and testing electronic systems. This includes working on circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems to launch cutting-edge, world-class products. Collaboration with cross-functional teams is essential to develop solutions that meet performance requirements. Minimum Qualifications: - Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field with 3+ years of Hardware Engineering or related work experience. OR - Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field with 2+ years of Hardware Engineering or related work experience. OR - PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field with 1+ year of Hardware Engineering or related work experience. Qualcomm is currently hiring for multiple roles in the following domains: 1. Physical Design 2. RTL Design 3. Design Verification 4. STA/Synthesis 5. DFT 6. FPGA Emulation 7. Validation Qualcomm is an equal opportunity employer that is committed to providing accommodations for individuals with disabilities during the application/hiring process. If you require an accommodation, you can email disability-accommodations@qualcomm.com or call the toll-free number provided on our website. Reasonable accommodations will be provided upon request to support individuals with disabilities in participating in the hiring process. Our workplace is designed to be accessible for individuals with disabilities. Employees at Qualcomm are expected to adhere to all applicable policies and procedures, including those related to security and the protection of confidential information. This extends to safeguarding Company confidential information and other proprietary information in accordance with applicable laws. For Staffing and Recruiting Agencies: Our Careers Site is exclusively for individuals seeking job opportunities at Qualcomm. Staffing and recruiting agencies, as well as individuals being represented by an agency, are not authorized to use this site or submit profiles, applications, or resumes. Any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Kindly refrain from forwarding resumes to our jobs alias, Qualcomm employees, or any other company location. Qualcomm will not be responsible for any fees related to unsolicited resumes or applications. For more information about the available roles, please reach out to Qualcomm Careers.,

SMTS SILICON DESIGN ENGINEER T HE ROLE : As a member of the Radeon Technologies Group, you will help bring to life cutting-edge designs. As a member of the front-end design/integration team, you will work closely with the architecture, IP design, Physical Design teams, and product engineers to achieve first pass silicon success. THE PERSON: A successful candidate will work with senior silicon design engineer s . The candidate will be highly accurate and detail-oriented, possessing good communication and problem-solving skills. K EY RESPONSIBLITIES : Implementation and verification of DFT architecture and features Scan insertion and ATPG pattern generation ATPG patterns verification with gate-level simulation Test coverage and test cost reduction analysis Post silicon support to ensure successful bring up and enhance yield learning P REFERRED EXPERIENCE : Understanding of Design for Test methodologies and DFT verification experience ( eg. IEEE1500, JTAG 1149.x, Scan, memory BIST etc .) Experience with Mentor testkompress and/or Synopsys Tetramax /DFTMAX Experience with VCS simulation tool, Perl/Shell scripting, and Verilog RTL design ACADEMIC CREDENTIALS: Bachelors or Masters degree in computer engineering/Electrical Engineering #LI-SR5

: As part of the methodology team, you will be responsible for developing and leading sophisticated power estimation and optimization methodologies at the netlist (gate-level) stage across SoC and IP designs. You will drive correlation strategies, automation flows, and accuracy improvements to ensure power estimates are tightly aligned with final silicon behavior. This role requires deep technical expertise in power analysis tools, a strong understanding of low-power design techniques, and collaboration with multi-functional teams across the design and verification cycle. Responsibilities: Define and drive netlist-level power estimation methodologies using industry-leading tools (e.g., Synopsys PrimeTime PX, Cadence Voltus). Establish and maintain correlation frameworks between RTL and gate-level power, and between estimated and silicon power. Develop automated flows for toggling activity generation, vector-based and vectorless power estimation, and regression reporting. Analyze power consumption trends and identify hotspots; provide recommendations for low-power design optimization. Collaborate with RTL design, physical design, DFT, and architecture teams to ensure early and accurate power signoff. Lead methodology development for corner analysis, dynamic/static power separation, and voltage scaling assessments. Support signoff reviews, audits, and compliance to power specifications and constraints. Provide mentorship and technical leadership within the team and across global sites. Required Skills and Experience : 10+ years of proven experience in power estimation, optimization, and methodology development at the gate-level/netlist stage. Hands-on expertise with tools such as Synopsys PrimeTime PX, Cadence Voltus, and related signoff flows. Strong understanding of digital design principles, low-power architecture techniques, clock gating, and multi-voltage domains. Proficient in scripting (Python, Perl, TCL) to develop scalable and automated power analysis flows. Demonstrated experience in analyzing switching activity data (SAIF/VCD/FSDB) and correlating to real application workloads. Confirmed ability to handle large SoC designs and deliver accurate power metrics under tight schedules. Excellent problem-solving skills, attention to detail, and ability to drive technical discussions and decisions. Nice To Have Skills and Experience : Experience with UPF/CPF power intent validation and integration. Exposure to thermal and IR-drop analysis in relation to power consumption. Familiarity with AI/ML-based power modeling or anomaly detection. Previous contributions to methodology deployment in domains such as mobile, automotive, or server-grade SoCs. Participation in EDA tool evaluations, benchmarking, and vendor teamwork. Publications or presentations in technical forums (e.g., SNUG, DVCon, DAC) related to power estimation or optimization. In Return: We are proud to have a set of behaviors that reflects who we are and guides our decisions, defining how we work together to surpass ordinary and shape outstanding! Partner and dedication towards or customers Collaborate and communication Originality and resourcefulness Team and personal development Impact and influence Deliver on your promises Accommodations at Arm At Arm, we want to build extraordinary teams. . To note, by sending us the requested information, you consent to its use by Arm to arrange for appropriate accommodations. All accommodation or adjustment requests will be treated with confidentiality, and information concerning these requests will only be disclosed as necessary to provide the accommodation. Although this is not an exhaustive list, examples of support include breaks between interviews, having documents read aloud, or office accessibility. Please email us about anything we can do to accommodate you during the recruitment process. Equal Opportunities at Arm Hybrid Working at Arm Accommodations at Arm At Arm, we want to build extraordinary teams. . To note, by sending us the requested information, you consent to its use by Arm to arrange for appropriate accommodations. All accommodation or adjustment requests will be treated with confidentiality, and information concerning these requests will only be disclosed as necessary to provide the accommodation. Although this is not an exhaustive list, examples of support include breaks between interviews, having documents read aloud, or office accessibility. Please email us about anything we can do to accommodate you during the recruitment process. Equal Opportunities at Arm

Post-Silicon ATE Lead to lead and manage post-silicon validation and production testing efforts using ATE platforms. This role requires strong technical expertise in silicon characterization, test development, and working closely with cross-functional teams including design, DFT, packaging, and product engineering. Own and lead post-silicon validation and ATE characterization for silicon devices (SoC/MCU/ASIC). Develop and debug ATE test programs for characterization, qualification, and production ramp-up. Collaborate with design and DFT teams to define test coverage and validation strategy. Analyze silicon test data to identify functional/parametric failures, yield issues, or corner case behaviours. Lead silicon debug and root cause analysis of test failures. Define and drive test cost optimization strategies (e. g. , multisite, parallel test, retest strategy). Work with OSATs and vendors for probe card, loadboard, and socket development. Define test limits, corner conditions, and environmental conditions (HTOL, AC/DC, ESD, etc. ). Support qualification testing (e. g. , HTOL, HAST, Temp Cycle) and drive correlation Qualifications B. E. / B. Tech or M. E. / M. Tech in Electronics, Electrical, or related field. 12+ years of experience in post-silicon validation and ATE development. Strong hands-on experience with ATE platforms (e. g. , Teradyne UltraFlex, Advantest 93K, NI STS). Solid understanding of mixed-signal, digital, and analog test methodologies. Experience with scripting (Python, Perl, and C) for automation and data analysis. Familiarity with lab equipment (oscilloscopes, source meters, BERTs, etc. ) for correlation and debug. Excellent problem-solving skills and ability to work across global teams. Company Description Renesas is one of the top global semiconductor companies in the world. We strive to develop a safer, healthier, greener, and smarter world, and our goal is to make every endpoint intelligent by offering product solutions in the automotive, industrial, infrastructure and IoT markets. Our robust product portfolio includes world leading MCUs, SoCs, Analog and power products, plus Winning Combination solutions that curate these complementary products. We are a key supplier to the world s leading manufacturers of electronics you rely on every day; you may not see our products, but they are all around you. Renesas employs roughly 21, 000 people in more than 30 countries worldwide. As a global team, our employees actively embody the Renesas Culture, our guiding principles based on five key elements: Transparent, Agile, Global, Innovative, and Entrepreneurial. Renesas believes in, and has a commitment to, diversity and inclusion, with initiatives and a leadership team dedicated to its resources and values. At Renesas, we want to build a sustainable future where technology helps make our lives easier. Join us and build your future by being part of what s next in electronics and the world.

Key Responsibilities Lead physical design activities for SoC or large subsystems, including floorplanning, placement, CTS, routing, and signoff closure. Define and drive physical design strategies to meet aggressive performance, power, and area goals. Collaborate cross-functionally with architecture, RTL design, STA, power, verification, and backend teams to ensure seamless integration and closure. Develop and maintain physical design methodologies, design guidelines, and automation scripts to enhance productivity and quality. Manage congestion, timing, power integrity, and manufacturability challenges during physical implementation. Communicate design status, risks, and mitigation plans effectively to senior management and stakeholders. Qualifications 14+ years of experience in SoC physical design with expertise in physical implementation flows (floorplanning, placement, CTS, routing) at advanced nodes (7nm, 5nm, or below). Proven track record leading complex SoC or subsystem physical design projects, balancing power, performance, and area while managing congestion and timing closure. Strong proficiency with industry-standard EDA tools (Synopsys ICC2, Cadence Innovus, PrimeTime) and scripting skills (Tcl, Python, Perl) for automation and methodology development. Deep understanding of SoC design flows with demonstrated ability to collaborate effectively across timing closure, power integrity, clocking, verification, and backend teams, including experience in developing physical design methodologies. Knowledge of power delivery network (PDN) design and integration. Familiarity with low-power design techniques including power gating and clock gating. Understanding of design for test (DFT) and its influence on physical design. Excellent leadership, communication, and collaboration skills to drive cross-team success. Company Description Renesas is one of the top global semiconductor companies in the world. We strive to develop a safer, healthier, greener, and smarter world, and our goal is to make every endpoint intelligent by offering product solutions in the automotive, industrial, infrastructure and IoT markets. Our robust product portfolio includes world leading MCUs, SoCs, Analog and power products, plus Winning Combination solutions that curate these complementary products. We are a key supplier to the world s leading manufacturers of electronics you rely on every day; you may not see our products, but they are all around you. Renesas employs roughly 21, 000 people in more than 30 countries worldwide. As a global team, our employees actively embody the Renesas Culture, our guiding principles based on five key elements: Transparent, Agile, Global, Innovative, and Entrepreneurial. Renesas believes in, and has a commitment to, diversity and inclusion, with initiatives and a leadership team dedicated to its resources and values. At Renesas, we want to build a sustainable future where technology helps make our lives easier. Join us and build your future by being part of what s next in electronics and the world.

Position: DFT-Design Engineer 2 Experience: 2+ years relevant experience. Location - India Education: B.Tech/M.Tech To be successful in this role you will: Seeking highly motivated, energetic, team-oriented Individual contributors willing to take the challenge of delivering of complex IPs using the latest advance Design for Test skills and Tools . Technical Skillset Required: Good knowledge in DFT Skills Sound knowledge in DFT Architecture and hands on in Scan , ATPG , Simulation GLS . Prior experience in Synsopsys or Cadence or Mentor tools Like Tetramax, Modus ,Tessent and DC tools Hands on in MBIST insertion and simulation Knowledge on JTAG is an added advantage . Good Simulation debugging skills Technical Documentation: uArchitecture Specification, SoC Integration Specification Good exposure to Scripting skills like Perl or Python or Shell or TCL . About us: Tessolve Semiconductors, a venture of Hero Electronix, is a Design and Test Engineering Service Company providing End to End Solutions from Product Engineering, Software, Hardware, Wireless, Automotive and Embedded Solutions. Tessolve offers a unique combination of pre-silicon and post-silicon expertise to provide an efficient turnkey solution for silicon bring-up, spec to the product. With 2500+ employees worldwide, Tessolve provides a one-stop-shop solution with full-fledged hardware and software capabilities, including its advanced silicon and system testing labs. Tessolve offers a Turnkey ASIC Solution, from design to packaged parts. We have a global presence with office locations in the United States, India, Singapore, Malaysia, Germany, United Kingdom, China, UK, Japan, Thailand, Philippines, and Test Labs in India, Singapore, Malaysia, Austin, San Jose. Tessolve offers a highly competitive compensation and benefits along with an electric work environment to scale one s intellect, skills and growth.