1121 Dft Jobs - Page 32

NVIDIA has been transforming computer graphics, PC gaming, and accelerated computing for more than 25 years. It s a unique legacy of innovation that s fueled by great technology and amazing people. Today, we re tapping into the unlimited potential of AI to define the next era of computing. An era in which our GPU acts as the brains of computers, robots, and self-driving cars that can understand the world. Doing what s never been done before takes vision, innovation, and the world s best talent. As an NVIDIAN, you ll be immersed in a diverse, supportive environment where everyone is inspired to do their best work. Come join the team and see how you can make a lasting impact on the world. As part of the CAD team our engineers develop and support tools for all of NVIDIAs semiconductor products. In addition, they also develop in-house tools in the area of Design for Test (DFT) and Design for Power (DFP) using C++, Python, and TCL. Below are some of the some of the teams activities. We are a diverse team needing someone who is not afraid of a challenge. If this is you, come join us today. What you ll be doing: Develop CAD software for high performance chip design and verification. Develop design and verification methodology for VLSI. Work on next generation software infrastructure for scalable development. Deploy AI into our work flows What we need to see: BS or Master degree of Electrical Engineering/Computer Engineering/Computer Science or equivalent experience 2+ years of relevant work experience. Skill of script language, such as Python/Perl/TCL. Software engineering: software design, algorithms, and QA. Familiar with C++ is a plus. Ways to stand out from the crowd: Familiar with Verilog. Experiences in CAD software developments. Knowledge or experience with DFT, DFP is a plus. Familiar with Verilog, VLSI and ASIC design principles, including knowledge of logic cells. Knowledge of GenAI, LLM, AI Code Generation is a plus. NVIDIA is widely considered to be one of the technology world s most desirable employers. We have some of the most forward-thinking and hardworking people in the world working for us. Are you a creative and autonomous engineer who loves a challengeCome join our GPU Verification team and help us build future interconnect architectures that will continue to drive us forward in the fields of High Performance Computing, Graphics and AI. We will ensure that individuals with disabilities are provided reasonable accommodation to participate in the job application or interview process, to perform essential job functions, and to receive other benefits and privileges of employment. Please contact us to request accommodation. #LI-Hybrid

- Lead the architecture, design and development of an Interrupt Controller for a highly virtualized, multi-threaded, many-core and multi-socket SMP (symmetric multi-processor) . - Develop the features, present the proposed architecture in the High level design discussions to hardware and software teams - Develop micro-architecture, Design RTL, Collaborate with the Verification, DFT, Physical design, firmware, software teams to develop the feature - Signoff the Pre-silicon Design that meets all the functional, area and timing goals - Participate in silicon bring-up and validation of the hardware - Lead a team of engineers, guide and mentor team members, represent as Logic Design Lead in global forums. - Estimate the overall effort to develop the feature - Estimate the silicon area required for the feature Required education Bachelor's Degree Preferred education Master's Degree Required technical and professional expertise - 10 to 15 years of relevant experience - At least 1 generation of processor interconnect design delivery leadership (eg UPI, axi, amba, NoC). - Expertise of SMP coherency - Experience in different on-chip interconnect topologies (e.g., mesh, crossbar) - Understanding of various snoop and data network protocols - Understanding of latency & bandwidth requirements and effective means of implementation - Working knowledge of queuing theory - numa/nuca architecture - Proficient in HDLs- VHDL / Verilog - Experience in High speed and Power efficient logic design - Experience in working with verification, validation, physical design teams for design closure including test plan reviews and verification coverage - Good understanding of Physical Design and able to collaborate with physical design team for floor planning, wire layer usage and budgets, placement of blocks for achieving high-performance design - Experience in leading uarch, RTL design teams for feature enhancements. - Follow agile project leadership principles. Work with the team on estimation and execution plan. - Ability to quickly understand issues spanning multiple functional domains, switch context frequently and provide solutions to problems, is necessary. Preferred technical and professional experience Bachelors / Masters in VLSI with demonstrated experience in the micro architecture and design of state of art Processor features to enhance high performance secure system performance.

-Lead the Architecture, Design and development of processor L2 and LLC (Last Level Cache) for high-performance IBM Systems. - Design and architect L2 cache and LLC as driven by capacity, latency, bandwidth, and RAS requirements. - Develop the features, present the proposed architecture in the High level design discussions - Develop micro-architecture, Design RTL, Collaborate with Verification, DFT, Physical design, FW, SW teams to develop the feature - Signoff the Pre-silicon Design that meets all the functional, area and timing goals - Participate in silicon bring-up and validation of the hardware - Lead a team of engineers, guide and mentor team members, represent as Logic Design Lead in global forums. - Estimate the overall effort to develop the feature. - Estimate silicon area and wire usage for the feature Required education Bachelor's Degree Preferred education Master's Degree Required technical and professional expertise -8+ years of relevant experience - At least 1 generation of processor L2 cache or LLC design delivery leadership. - Expertise in cache coherence protocols for symmetric multiprocessors (SMP), covering both chip SMP and multi-socket SMP. - Experience with NuCA / NuMA (Non-uniform Cache / Memory architecture) architectures and implementations. - Working knowledge of memory consistency, store ordering, weakly and strongly ordered memory. - Experience in logical and physical design of caches including directories (tags, set associative memories), data SRAM, design for low latency, multiple parallel finite state machine design, deadlock-free designs.

Siemens EDA is a global technology leader in Electronic Design Automation software. Our software tools enable companies around the world to develop highly innovative electronic products faster and more efficiently. Our customers use our tools to push the boundaries of technology and physics to deliver better products in the increasingly complex world of chip, board, and system design. Position presents an opportunity to join the award winning and market leading Tessent team, India. The focus of the role is advanced design-for-test (DFT) insertion and automatic test pattern generation (ATPG) for semiconductor designs. It will involve understanding and supporting the latest DFT ATPG electronic design automation (EDA) technologies such as Tessent TestKompress and Streaming Scan Network (SSN). Someone in this role will gain a deep understanding of scan design, on-chip clock controls, and IJTAG infrastructure in support of scan testing. They will support the worldwide application engineering team on complex ATPG issues and build testcases for advanced DFT methodologies. This role is based in Noida. But you’ll also get to visit other locations in India and globe, so you’ll need to go where this job takes you. In return, you’ll get the chance to work with teams impacting entire cities, countries, and the shape of things to come. Responsibilities for this role include: Build and deliver in-depth technical presentations, develop training material, white papers, supplied articles, and application notes. Work with customers as well as Siemens stakeholders such as regional application engineers, global support engineers, and marketing. Are you expertized in working through complex technical issues and independently building solutions and new methodologies! Explain complex principles in simple terms to broad audiences. Some travel, domestic and international. Successful deployment of existing and new Tessent DFT products in customer designs by enabling AEs. Working closely with our key customers on deployment challenges. Working with PEs and R&D to ensure new product readiness testcase in form of testcases, documentation and trainings. Architecture reviews of customer designs. Closely working with AEs to gather top issues blocking their engagement's success. Deep learning opportunities for Tessent DFT products including opportunities to present at various conferences worldwide including ITC and Siemens U2U. We don’t need hard workers, just superminds! BS degree (or equivalent) in Electrical Engineering, Computer Science or related field is required with 10 - 15 years of experience. Knowledge of design logic design languages, tool usage, design flow steps required. We are looking for someone that has exposure to DFT or SoC design for complex ASICs / SOCs. ATPG, IEEE 1687 IJTAG, boundary scan (BSCAN), hierarchical DFT implementation. Knowledge of a scripting language like TCL. We need someone self-motivated and dedication to improvement with strong problem-solving skills. Excellent organizational skills, written and verbal English language communication skills. Proficiency in LINUX and Windows environments. The role presents many opportunities to build specialized DFT and ATPG knowledge. Publications and other promotions of methodologies is encouraged. We are Siemens A collection of over 377,000 minds building the future, one day at a time in over 200 countries. We're dedicated to equality, and we encourage applications that reflect the diversity of the communities we work in. All employment decisions at Siemens are based on qualifications, merit and business need. Bring your curiosity and creativity and help us shape tomorrow! We offer a comprehensive reward package which includes a competitive basic salary, variable pay, other benefits, pension, healthcare and actively support working from home. We are an equal opportunity employer and value diversity at our company. We do not discriminate based on race, religion, color, national origin, sex, gender, gender expression, sexual orientation, age, marital status, veteran status, or disability status. Transform the everyday Show more Show less

MTS Software System Design Eng. Bangalore, India Engineering 66058 Job Description WHAT YOU DO AT AMD CHANGES EVERYTHING We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences – the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world’s most important challenges. We strive for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives. AMD together we advance_ THE ROLE: AMD is looking for an experienced engineer for an exciting role in Server CPU software development team. This person will be a member of a core team and will work with the latest hardware and software technology. The person will interact closely with key AMD technical experts to ensure the best possible performance and results on AMD platforms. THE PERSON: The successful candidate for this position will be interacting with software and hardware technologists working across many locations. This is a great opportunity to work as a part of highly regarded team to deliver leading edge solutions. KEY RESPONSIBILITIES: Problem solving across multiple software layers, (user space, kernel, applications, libraries) and hardware. Optimization/development of the CPU performance stack (applications, libraries) for AMD server and workstation processors on Windows platform. Analyze and solve performance, scalability bottlenecks when code is running on multi-core, multi-node deployments. Innovate and publish papers, patents and participate in technical conferences to advance AMD technologies. Continuously learn and grow along with evolving X86 server CPU architecture and application landscape. PREFERRED EXPERIENCE: Image processing skills: Color format conversions, Image Filtering and Enhancement operations, Morphological operations, Image transforms and statistical operations. Good understanding in Image Detection, Segmentation, Recognition, Restoration and Medical Imaging. Knowledge in Signal Processing theory like Sampling, Quantization, DFT and FFT. Multi-threaded FFT computing, Distributed FFT computing Very strong data structure and algorithmic skills. Experience in identifying performance bottlenecks, and designing/implementing optimizations to relieve analyzed bottlenecks. Strong Windows internals with experience in software development using C/C++ and debugging skills on multicore systems (preferably using OpenMP). Experience in performance analysis for data center, HPC (High Performance Computing), MPI (Message passing Interface) applications. Experience in x86 (or other architecture based) optimizations. Understanding of Cache sub-system, Instruction Set Architecture, pipeline (for any CPU). Bonus skills: Experience on Intel MKL libraries, Linear Algebra, x86 assembly programming (vector/SIMD), porting source code from Linux to Windows, development on Windows servers Knowledge of one or more CPU Profiling tools (preferably in Windows). ACADEMIC CREDENTIALS: B.Tech/M.Tech/MS/B.E/M.E in computer science or related fields #LI-NS2 AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

To work as a Frontend engineer and taking care of Synthesis, LEC, CLP and Power Analysis for complex SoC projects. Job Description In your new role you will: Implement high-performance, low-power, and area-efficient digital designs. Write and implement block level and top-level constraints for Synthesis, Static Timing Analysis . Optimize designs for power, performance, and area, and meet PPA goals. Power analysis using PT-PX or equivalent flow. Logic Equivalence Check (LEC) and Low Power Checks (CLP) at block and SoC level designs. Define and evaluate constraints and signoff Test/DFT mode timing requirements. Your Profile You are best equipped for this task if you have: Strong fundamentals and experience in Synthesis and STA domains. Write and implement block level and top-level timing constraints for Synthesis Optimize designs for power, performance, and area, and meet design goals. Knowledge on Power analysis and PT-PX flow. Understanding of DFT flows, including scan insertion. Write and evaluate Test/DFT mode timing constraints. Thorough with Logic Equivalence Check debug capability. Well known about UPF concepts and Low Power Checks at block and full chip level. Defining and verification of STA constraint for Functional and Test/SCAN Modes. Defining PVT’s corners required for covering all desired scenarios for a design Knowledge on OCV/AOCV/POCV derates. Understanding of Prime-Time and TEMPUS tools, which helps in quick debugging of design/timing issues. VASTA timing closure based on chip IR drop. Knowledge on signal SI analysis and PT-PX flow. Contact: swati.gupta@infineon.com #WeAreIn for driving decarbonization and digitalization. As a global leader in semiconductor solutions in power systems and IoT, Infineon enables game-changing solutions for green and efficient energy, clean and safe mobility, as well as smart and secure IoT. Together, we drive innovation and customer success, while caring for our people and empowering them to reach ambitious goals. Be a part of making life easier, safer and greener. Are you in? We are on a journey to create the best Infineon for everyone. This means we embrace diversity and inclusion and welcome everyone for who they are. At Infineon, we offer a working environment characterized by trust, openness, respect and tolerance and are committed to give all applicants and employees equal opportunities. We base our recruiting decisions on the applicant´s experience and skills. Please let your recruiter know if they need to pay special attention to something in order to enable your participation in the interview process. Click here for more information about Diversity & Inclusion at Infineon.

Full Chip Physical Design Engineer Job Summary: We are seeking a highly motivated and skilled engineer to join our SoC implementation team. You will be responsible for the physical design of complex ASICs and SoCs, working on full-chip floorplanning, integration, and signoff activities to meet aggressive PPA (Power, Performance, Area) goals. Key Responsibilities: Drive full chip-level physical design flow from RTL to GDSII. Ownership of chip-level floorplanning, partitioning, and integration. Collaborate with RTL, synthesis, DFT, and STA teams to resolve cross-functional issues. Implement place & route flows including timing closure, IR/EM, and congestion optimization. Perform physical verification (LVS/DRC/ERC) and work with foundries to fix violations. Manage static timing analysis (STA) at top level and work closely with timing owners for signoff. Handle power planning and power domain implementation (UPF/CPF-based). Contribute to methodology improvements and automation. Required Qualifications: Bachelor's or Master’s degree in Electrical/Electronics/Computer Engineering or related field. 3–6 years of experience in physical design with at least one full chip tapeout. Hands-on expertise with industry-standard tools such as Synopsys (ICC2, Fusion Compiler, PrimeTime), Cadence (Innovus), and Mentor (Calibre). Strong knowledge of physical design concepts: floorplanning, CTS, routing, timing closure, IR drop, EM, DRC/LVS. Proficiency in scripting languages like Tcl, Perl, Python, or Shell. Familiarity with hierarchical design and ECO flows. Experience: 3 to 6 Years. Location: Bangalore / Hyderabad . Notice Period: Less than 30 days Show more Show less

Cadence is a pivotal leader in electronic design, building upon more than 30 years of computational software expertise. The company applies its underlying Intelligent System Design strategy to deliver software, hardware and IP that turn design concepts into reality. Cadence customers are the world’s most innovative companies, delivering extraordinary electronic products from chips to boards to systems for the most dynamic market applications including consumer, hyperscale computing, 5G communications, automotive, aerospace industrial and health. The Cadence Advantage The opportunity to work on cutting-edge technology in an environment that encourages you to be creative, innovative, and to make an impact. Cadence’s employee-friendly policies focus on the physical and mental well-being of employees, career development, providing opportunities for learning, and celebrating success in recognition of specific needs of the employees. The unique “One Cadence – One Team” culture promotes collaboration within and across teams to ensure customer success Multiple avenues of learning and development available for employees to explore as per their specific requirement and interests You get to work with a diverse team of passionate, dedicated, and talented individuals who go above and beyond for our customers, our communities, and each other—every day Location: Hyderabad BE/BTECH/ME/METCH or Equivalent Degree This is an opportunity to join a dynamic and growing team of experienced engineers developing high-performance physical IP for industry-standard protocols. The successful candidate will be a highly motivated self-starter who is able to work independently and collaboratively to complete tasks within required project timelines with high quality. The candidate will contribute to digital architecture, digital RTL, low power design, synthesis and timing analysis, and behavioral coding for all IPs in the SerDes physical IP portfolio as well as executing various tool flows for IP quality control. The candidate will be able to work as part of a small and focused team of engineers and will be able to collaborate successfully as needed with design architects, digital verification, project management, and digital and analog design teams in multiple worldwide geographies. This includes but is not limited to: EXP-7-15years Digital architecture that has an understanding of the trade-offs for power, performance, and area Drive architecture to micro-architecture to RTL implementation with the refining of features/requirements throughout the design process Understanding of synthesis, constraint generation, power management and DFT Understanding of low-power designs and features (power islands, state retention, isolation) Work with verification team to specify coverage points, testing strategy, corner conditions and stimulus creation Familiarity with uC Based subsystems and their architecture Qualifications 7+ Years’ experience in working with Digital Design and Architecture. Must have good written and verbal cross-functional communication skills. Proven experience in most of the following: Design Architecture Design implementation Embedded uC Designs Synthesis and SDC Creation Scripting of design automation Debugging verification test cases / SVA’s to cover the design Knowledge of existing Serial standards such as PCIE, USB, Ethernet, etc. Must be comfortable interacting across the IPG development team including the ability to work with Mixed-signal, Verification and Analog teams Knowledge of multiple programming languages. System Verilog, Python, C/C++, etc, are a plus Working knowledge of revision control tools such as Perforce, Git, SVN is a plus Education Level: Bachelor's Degree (MSEE Preferred) Show more Show less

To work as a Frontend engineer and taking care of Synthesis, LEC, CLP and Power Analysis for complex SoC projects. Job Description In your new role you will: Implement high-performance, low-power, and area-efficient digital designs. Write and implement block level and top-level constraints for Synthesis, Static Timing Analysis. Optimize designs for power, performance, and area, and meet PPA goals. Power analysis using PT-PX or equivalent flow. Logic Equivalence Check (LEC) and Low Power Checks (CLP) at block and SoC level designs. Define and evaluate constraints and signoff Test/DFT mode timing requirements. Your Profile You are best equipped for this task if you have: Strong fundamentals and experience in Synthesis and STA domains. Write and implement block level and top-level timing constraints for Synthesis Optimize designs for power, performance, and area, and meet design goals. Knowledge on Power analysis and PT-PX flow. Understanding of DFT flows, including scan insertion. Write and evaluate Test/DFT mode timing constraints. Thorough with Logic Equivalence Check debug capability. Well known about UPF concepts and Low Power Checks at block and full chip level. Defining and verification of STA constraint for Functional and Test/SCAN Modes. Defining PVT’s corners required for covering all desired scenarios for a design Knowledge on OCV/AOCV/POCV derates. Understanding of Prime-Time and TEMPUS tools, which helps in quick debugging of design/timing issues. VASTA timing closure based on chip IR drop. Knowledge on signal SI analysis and PT-PX flow. Contact: swati.gupta@infineon.com #WeAreIn for driving decarbonization and digitalization. As a global leader in semiconductor solutions in power systems and IoT, Infineon enables game-changing solutions for green and efficient energy, clean and safe mobility, as well as smart and secure IoT. Together, we drive innovation and customer success, while caring for our people and empowering them to reach ambitious goals. Be a part of making life easier, safer and greener. Are you in? We are on a journey to create the best Infineon for everyone. This means we embrace diversity and inclusion and welcome everyone for who they are. At Infineon, we offer a working environment characterized by trust, openness, respect and tolerance and are committed to give all applicants and employees equal opportunities. We base our recruiting decisions on the applicant´s experience and skills. Please let your recruiter know if they need to pay special attention to something in order to enable your participation in the interview process. Click here for more information about Diversity & Inclusion at Infineon. Show more Show less

To work as a Frontend Lead and taking care of Synthesis, LEC, CLP and Power Analysis for complex SoC projects. Job Description In your new role you will: Implement high-performance, low-power, and area-efficient digital designs. Write and implement block level and top-level constraints for Synthesis, Static Timing Analysis. Optimize designs for power, performance, and area, and meet PPA goals. Power analysis using PT-PX or equivalent flow. Logic Equivalence Check (LEC) and Low Power Checks (CLP) at block and SoC level designs. Define and evaluate constraints and signoff Test/DFT mode timing requirements. Your Profile You are best equipped for this task if you have: Strong fundamentals and experience in Synthesis and STA domains. Write and implement block level and top-level timing constraints for Synthesis Optimize designs for power, performance, and area, and meet design goals. Knowledge on Power analysis and PT-PX flow. Understanding of DFT flows, including scan insertion. Write and evaluate Test/DFT mode timing constraints. Thorough with Logic Equivalence Check debug capability. Well known about UPF concepts and Low Power Checks at block and full chip level. Defining and verification of STA constraint for Functional and Test/SCAN Modes. Defining PVT’s corners required for covering all desired scenarios for a design Knowledge on OCV/AOCV/POCV derates. Understanding of Prime-Time and TEMPUS tools, which helps in quick debugging of design/timing issues. VASTA timing closure based on chip IR drop. Knowledge on signal SI analysis and PT-PX flow. Contact: swati.gupta@infineon.com #WeAreIn for driving decarbonization and digitalization. As a global leader in semiconductor solutions in power systems and IoT, Infineon enables game-changing solutions for green and efficient energy, clean and safe mobility, as well as smart and secure IoT. Together, we drive innovation and customer success, while caring for our people and empowering them to reach ambitious goals. Be a part of making life easier, safer and greener. Are you in? We are on a journey to create the best Infineon for everyone. This means we embrace diversity and inclusion and welcome everyone for who they are. At Infineon, we offer a working environment characterized by trust, openness, respect and tolerance and are committed to give all applicants and employees equal opportunities. We base our recruiting decisions on the applicant´s experience and skills. Please let your recruiter know if they need to pay special attention to something in order to enable your participation in the interview process. Click here for more information about Diversity & Inclusion at Infineon. Show more Show less

NVIDIA has continuously reinvented itself. Our invention of the GPU sparked the growth of the PC gaming market, redefined modern computer graphics, and revolutionized parallel computing. Today, research in artificial intelligence is booming worldwide, which calls for highly scalable and massively parallel computation horsepower that NVIDIA GPUs excel. NVIDIA is a “learning machine” that constantly evolves by adapting to new opportunities that are hard to solve, that only we can address, and that matter to the world. This is our life’s work , to amplify human creativity and intelligence. As an NVIDIAN, you’ll be immersed in a diverse, supportive environment where everyone is inspired to do their best work. Come join our diverse team and see how you can make a lasting impact on the world! As part of the CAD team our engineers develop and support tools for all of NVIDIA's semiconductor products. In addition, they also develop in-house tools in the area of Design for Test (DFT) and Design for Power (DFP) using C++, Python, and TCL. Below are some of the some of the teams' activities. We are a diverse team needing someone who is not afraid of a challenge. If this is you, come join us today. What you will be doing: Be responsible for architecting highly automated and customizable design flows using software engineering with modular design and object oriented techniques. Work closely with our diverse team members on flows to provide DFT, and DFP methodologies for industry-leading chip designs. Support development of tools using C++/Python/TCL. Work cross functionally with DFT Methodology, Implementation and design teams with important DFT and power tools development tasks. What we need to see: 2+ years of relevant work experience. Smart, diligent and motivated to work in our CAD group. BE or BTech or MTech in Computer Science, or Electronics Engineering, or Electrical Engineering, or equivalent experience. Knowledge or experience with DFT, DFP is a plus. Familiar with Verilog, VLSI and ASIC design principles, including knowledge of logic cells. Software engineering: software design, algorithms, and QA. Strong C++ programming experience. Solid programming and scripting skills in Python or TCL desired. Knowledge of GenAI, LLM, AI Code Generation is a plus. Having strong interpersonal skills will serve you well in this role. NVIDIA is widely considered to be one of the technology world’s most desirable employers. We have some of the most forward-thinking and dedicated people in the world working for us. If you're creative and autonomous, we want to hear from you! #LI-Hybrid

NVIDIA has continuously reinvented itself. Our invention of the GPU sparked the growth of the PC gaming market, redefined modern computer graphics, and revolutionized parallel computing. Today, research in artificial intelligence is booming worldwide, which calls for highly scalable and massively parallel computation horsepower that NVIDIA GPUs excel. NVIDIA is a “learning machine” that constantly evolves by adapting to new opportunities that are hard to solve, that only we can address, and that matter to the world. This is our life’s work , to amplify human creativity and intelligence. As an NVIDIAN, you’ll be immersed in a diverse, supportive environment where everyone is inspired to do their best work. Come join our diverse team and see how you can make a lasting impact on the world! Design-for-Test Engineering at NVIDIA works on groundbreaking innovations involving crafting creative solutions for DFT architecture, verification, and post-silicon validation on some of the industry's most complex semiconductor chips. What you'll be doing: As an integral member in our team, you will work on exploring Applied AI solutions for DFX and VLSI problem statements. Architect end-to-end generative AI solutions with a focus on LLMs, RAGs & Agentic AI workflows. Work on deploying predictive ML models for efficient Silicon Lifecycle Management of NVIDIA's chips. Collaborate closely with various VLSI & DFX teams to understand their language-related engineering challenges and design tailored solutions. Work closely with cross-functional AI teams to provide feedback and contribute to the evolution of generative AI technologies. Work closely with DFX teams to integrate Agentic AI workflows into their applications and systems and stay abreast of the latest developments in language models and generative AI technologies. Define how data will be collected, stored, consumed and managed for next-generation AI use cases. You will also help mentor junior engineers on test designs and trade-offs including cost and quality. What we need to see: BSEE or MSEE from reputed institutions with 2+ years of experience in DFT, VLSI & Applied Machine Learning Experience in Applied ML solutions for chip design problems Significant experience in deploying generative AI solutions for engineering use cases Good understanding of fundamental DFT & VLSI concepts - ATPG, scan, RTL & clocks design, STA, place-n-route and power Experience in application of AI for EDA-related problem-solving is a plus Excellent knowledge in using statistical tools for data analysis & insights Strong programming and scripting skills in Perl, Python, C++ or TCL desired Strong organization and time management skills to work in a fast-pace multi-task environment Self-motivated, independent, ability to work independently with minimal day-to-day direction Outstanding written and oral communication skills with the curiosity to work on rare challenges NVIDIA offers highly competitive salaries and a comprehensive benefits package. We have some of the most brilliant and talented people in the world working for us and, due to unprecedented growth, our world-class engineering teams are growing fast. If you're a creative and autonomous engineer with real passion for technology, we want to hear from you! #LI-Hybrid

Company Qualcomm India Private Limited Job Area Engineering Group, Engineering Group > Hardware Engineering General Summary As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Skills/Experience 2-5 years of strong experience in digital front end ASIC design verification Bachelors or Masters Degree in Engineering in Electronics, VLSI, Communications or related field. We are looking for a highly motivated and talented RTL verification engineer to join our team to work on the next generation complex cores used in High End Modem/Mobile chips. In this role, a successful incumbent would: - Develop verification environment and testbench components such as BFM and checkers. - Develop comprehensive test plan for unit level verification of IP/Module features and implement test cases. - Verify design in unit level environment using directed and constrained random testing, assertion-based verification, formal analysis, and functional verification. - Write functional cover-groups and cover-points for coverage closure. - Perform RTL code coverage, assertion coverage, functional coverage and gate level simulations. - Have expertise in verifying designs at system level and block level using constrained random verification. - Operate at Expert level in System Verilog and UVM based verification. - Expertise in coding SV Testbench, drivers, monitors, scoreboards, checkers - Strong and independent design debugging capability. - Understanding of AHB, AXI and other bus protocols, digital design and system architecture - Understanding of TCP/IP Packet Processing Algorithms like Filtering, Routing, NAT, Decipher, Checksum, Ethernet Bridging, Tunneling is a Plus. Should possess good communication skills to ensure effective interaction with Engineering Management and team members. Should be self-motivated with good teamwork attitude and need to function with minimal guidance or supervision Responsibilities Work in close coordination with Systems, Design, SoC team , SW team, Validation & DFT teams to get the goals completed. Developing the Verification Strategy, Testbench architecture and implementing the design verification plan and tests using SV/UVM/C. HW verification using Cadence and Synopsys simulator tools, SV/UVM based TB development, Regression analysis, bug-triage. Formal Verification using Jasper, VCF etc. Power Aware Verification on RTL and DC/PD Gate lebel Netlist. Conducting High-/Mid-/Low- level verification reviews, coverage closure and sign-off on block and Sub-system testing. Assisting SOC team with IP Integration testing at SOC level. Post-Silicon Debugs in close collaboration with Design, Validation and SW teams. Self-Motivated to Execute the defined tasks almost independently with minimal guidance Minimum Qualifications Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field. Applicants : Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries). Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law. To all Staffing and Recruiting Agencies : Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications. If you would like more information about this role, please contact Qualcomm Careers. 3071061 Show more Show less

Company Qualcomm India Private Limited Job Area Engineering Group, Engineering Group > Hardware Engineering General Summary As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. Minimum of 5+ years’ experience in the area of DFT-, ATPG, Scan Insertion, MBIST, JTAG In depth knowledge of DFT concepts. In depth knowledge and hands on experience in DFT(scan/mbist) insertion, ATPG pattern generation/verification, mbist verification and post silicon bring up/yield analysis Expertise in test mode timing constraints definition, knowledge in providing timing fixes/corrective actions for timing violations. Ability to analyze and devise new tests for new technologies/custom RAM design/RMA etc. Expertise in scripting languages such as perl, shell, etc. Experience in simulating test vectors. Knowledge of equivalence check and RTL lint tool (like spyglass). Ability to work in an international team, dynamic environment Ability to learn and adapt to new tools and methodologies. Ability to do multi-tasking & work on several high priority designs in parallel. Excellent problem-solving skills Applicants : Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries). Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law. To all Staffing and Recruiting Agencies : Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications. If you would like more information about this role, please contact Qualcomm Careers. 3071490 Show more Show less

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. College education in Electronics Engineering or Computer Engineering Working knowledge in RTL design flow steps like RTL coding, Simulation, compilation/testbench validation, Synthesis, Timing, DFT,lint, CDC, LEC etc. Ability to debug existing Verilog/System verilog test cases with little or no help from the designer. Functional simulation using Verilog/System Verilog. Good in Scripting languages(Shell, Perl, TCL, Python) and automation of design database qualification and packaging. Checks and validation of package consistency. Familiarity with Power Flow (UPF/CPF). Able to collaborate with IP-development teams and facilitate high-quality releases. Maintaining package and release timelines for various projects. Time management skills enough to balance multiple high-priority projects. Bug reporting and resolution closure with IP providers Ability to debug synthesis/timing analysis constraints, reports, logs Ability to learn new tools/flows and develop methodology if needed. Ability to build and maintain close relationships with Designers and Application Engineers. Fastidious approach to building automated processes. Strong interpersonal and relationship-building skills. Additional Desirable Qualifications Familiarity with SerDes/DDR/other Design-IP’s & Analog design flows Familiarity with IP release and tracking management systems. We’re doing work that matters. Help us solve what others can’t. Show more Show less

Analyse customer requirements, legal regulations and internal specification to be applied in Testing strategies of products Develop EOLT specifications for new equipments (Hardware & Software) Design and develop complex test programs, process and systems to measure product functionality and integrality in the electrical and programming domains Analyse test cases and failure, providing scenarios and proposing actions based on results Checks product SW and Test Methodology/Coverage during DFT Design Review, with R&D interaction May make himself some functional Tester software development and improvements Checks the Functional Testers development (review of technical issues and planning) Work with the Software Validation Team to ensure complete test coverage of all requirements Analyze the customer specifications, legal requirements and internal specifications towards the development of electronic test plans Support the creation of test equipment specifications and tester hardware specifications used in the development of automated test rack systems Perform validation, capabilities, test coverage and stability performance of testers Monitor testing TLR, analyse defects, and propose action plans to reduce Validate PG RAISE and CdC standards which are created by M/D Standard Owners Validate any change of standard propose by sites in new investments for Testing equipments Validate the assembly line included on each CAA, in concept, cycle time and investment values Contribute to product & process FMEA, assisting Testing technicians in daily activities Support transition of newly developed processes into series production, providing process / equipment specification and qualification Define activities to permit integration of Testing equipments into more complex manufacturing cells Perform survey of equipment in continuous improvement & cost reduction mindset to optimize investments, material & labor costs Develop an industrial cross-project competence Promote the Valeo Industrial standard rules and procedures Ensure the respect of Safety and Environment procedures of Valeo Group PS: if the workload justifies it, the function can be divided in more than one person Show more Show less

Requisition ID 187684 Date posted 04/22/2025 Work Location Model On-site Flex Work Location Bangalore-IN-Bangalore Work Country India Eligibility Criteria Educational qualification: Bachelor of Electrical/Electronics Engineering, MTech is an added advantage. Years of Experience: 4+ years of relevant experience in schematic & PCB design & testing, cable design Primary Responsibility Responsible for executing Electrical Engineering technical disciplines with primary focus on designing and modifying schematic and PCB layout. Board Design, Electronics Circuits including microcontroller/FPGA based designs, sensor interfaces, analog signal conditioning circuits, power supplies, ethernet based communication interfaces, Wireless Interfaces, Wireless Chargers etc. Creation of system interconnects diagram and electrical schematics diagram based on requirements received from cross-disciplinary teams Own the Cable Designs, drafting of cables, creation of harness drawings Work with cross-disciplinary teams (including mechanical, electro-mechanical, software, process, manufacturing engineers) for major projects with multi-national work environment. Creating electrical schematics and PCB layouts based on requirements received from cross-disciplinary teams Creating and releasing engineering drawings & bill of materials using Engineering Change Management process Interacting with PG counterpart in US Studying and recommending corrective solutions for technical issues of varying complexities. Conducting Design review to get buy-in from all cross functional teams Managing in a very dynamic and fast paced work environment with frequent updates, design packages with quick solutions etc. Mandatory Skills required to perform the job: Core PCB Design Expertise with OrCAD Allegro – designed complex boards 10-12 layers with SMD’s, BGA’s, through hole parts, placement, routing, setting up constraints, working with component library teams for PCB footprint Performing Schematic Entry in OrCAD Design Entry and circuit understanding with op-amps, comparators, passive devices, sensor circuitry, semiconductors IC’s – microcontrollers/FPGA, power supplies (DC-DC Converters) Working alongside EE, ME for planning the board, DFT philosophy, working with PCB vendors for design for manufacturability (DFM), mechanical packaging constraints and PCB stack-up Ability to write test plans for PCB testing and ability to perform low level IO testing on sub-controller and devices, debugging board failures/issues Creation of electrical schematic diagram for cables, knowledge of Zuken Semiconductor domain knowledge would be a value addition Our Commitment We believe it is important for every person to feel valued, included, and empowered to achieve their full potential. By bringing unique individuals and viewpoints together, we achieve extraordinary results. Lam Research ("Lam" or the "Company") is an equal opportunity employer. Lam is committed to and reaffirms support of equal opportunity in employment and non-discrimination in employment policies, practices and procedures on the basis of race, religious creed, color, national origin, ancestry, physical disability, mental disability, medical condition, genetic information, marital status, sex (including pregnancy, childbirth and related medical conditions), gender, gender identity, gender expression, age, sexual orientation, or military and veteran status or any other category protected by applicable federal, state, or local laws. It is the Company's intention to comply with all applicable laws and regulations. Company policy prohibits unlawful discrimination against applicants or employees. Lam offers a variety of work location models based on the needs of each role. Our hybrid roles combine the benefits of on-site collaboration with colleagues and the flexibility to work remotely and fall into two categories – On-site Flex and Virtual Flex. ‘On-site Flex’ you’ll work 3+ days per week on-site at a Lam or customer/supplier location, with the opportunity to work remotely for the balance of the week. ‘Virtual Flex’ you’ll work 1-2 days per week on-site at a Lam or customer/supplier location, and remotely the rest of the time.

Company Qualcomm India Private Limited Job Area Interns Group, Interns Group > Interim Engineering Intern - HW Qualcomm Overview Qualcomm is a company of inventors that unlocked 5G ushering in an age of rapid acceleration in connectivity and new possibilities that will transform industries, create jobs, and enrich lives. But this is just the beginning. It takes inventive minds with diverse skills, backgrounds, and cultures to transform 5Gs potential into world-changing technologies and products. This is the Invention Age - and this is where you come in. General Summary We know our employees’ ideas change the world. For more than three decades, we’ve been a global leader in mobile technology, continually pushing the boundaries of what’s possible. Working with customers across industries — from automotive to health care, from smart cities to robotics— we continue to accelerate innovation and unlock new possibilities in a time where everything is connected. By joining the Qualcomm family, you too can bring the future forward faster. SOC & Hard Macro Physical Design SOC Validation & Debug RF & Analog Layout RF/Analog/Mixed Signal/Power IC Design Low Power Design Board and FPGA Design Digital ASIC Design Design/SOC Verification CAD Solution Engineer Design for Test (DFT) CPU Design Must have educational background in one or more of the following areas: Verifying SoC with embedded RISC/DSP processors, communications/ networking ASICs. Verilog or VHDL, C/C++, Tcl/Perl/shell-scripting. RTL design experience and/or strong OO programming knowledge Knowledge of wireless/wired communications and protocols or graphics/video multi-media is a plus. Knowledge in PLL, LNA, OpAmp, CMOS, ADC/DAC, Cadence, SpectreRF, or Layout is required in RF/Analog/Mixed Signal IC Design. Excellent analytical and problem solving skills. Ability to collaborate and work in teams. Good verbal and written communication skill Educational Background Masters, Bachelors: Electrical Engineering , VLSI , Embedded and VLSI , ECE Applicants : Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail myhr.support@qualcomm.com or call Qualcomm's toll-free number found here . Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law. To all Staffing and Recruiting Agencies: Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications. If you would like more information about this role, please contact Qualcomm Careers. 3063801 Show more Show less

Company Qualcomm India Private Limited Job Area Interns Group, Interns Group > Interim Engineering Intern - HW Qualcomm Overview Qualcomm is a company of inventors that unlocked 5G ushering in an age of rapid acceleration in connectivity and new possibilities that will transform industries, create jobs, and enrich lives. But this is just the beginning. It takes inventive minds with diverse skills, backgrounds, and cultures to transform 5Gs potential into world-changing technologies and products. This is the Invention Age - and this is where you come in. General Summary We know our employees’ ideas change the world. For more than three decades, we’ve been a global leader in mobile technology, continually pushing the boundaries of what’s possible. Working with customers across industries — from automotive to health care, from smart cities to robotics— we continue to accelerate innovation and unlock new possibilities in a time where everything is connected. By joining the Qualcomm family, you too can bring the future forward faster. SOC & Hard Macro Physical Design SOC Validation & Debug RF & Analog Layout RF/Analog/Mixed Signal/Power IC Design Low Power Design Board and FPGA Design Digital ASIC Design Design/SOC Verification CAD Solution Engineer Design for Test (DFT) CPU Design Must have educational background in one or more of the following areas: Verifying SoC with embedded RISC/DSP processors, communications/ networking ASICs. Verilog or VHDL, C/C++, Tcl/Perl/shell-scripting. RTL design experience and/or strong OO programming knowledge Knowledge of wireless/wired communications and protocols or graphics/video multi-media is a plus. Knowledge in PLL, LNA, OpAmp, CMOS, ADC/DAC, Cadence, SpectreRF, or Layout is required in RF/Analog/Mixed Signal IC Design. Excellent analytical and problem solving skills. Ability to collaborate and work in teams. Good verbal and written communication skill Educational Background Masters, Bachelors: Electrical Engineering , VLSI , Embedded and VLSI , ECE Applicants : Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail myhr.support@qualcomm.com or call Qualcomm's toll-free number found here . Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law. To all Staffing and Recruiting Agencies: Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications. If you would like more information about this role, please contact Qualcomm Careers. 3063801 Show more Show less

Job Purpose To oversee the complete painting process of pressed steel radiators and transformer tanks, ensuring quality and timely execution as per standards. Additionally, to manage the finished goods dispatch process, ensuring timely and accurate delivery of painted components to internal and external customers. Key Responsibilities Painting Operations • Supervise surface preparation and painting of pressed steel radiators and transformer tanks, including primer and final coat. • Ensure quality of paint application in terms of thickness, finish, and adherence to customer/IS/IEC specifications. • Allocate and monitor work of the painting team (manual/spray painters and helpers). • Oversee surface preparation activities like shot blasting, sanding, and cleaning. • Ensure proper utilization and maintenance of spray guns, paint booths, compressors, and other equipment. • Maintain and track paint material consumption and inventory. • Conduct visual and instrumental inspection (e.g. DFT, gloss, adhesion tests). • Ensure proper drying/curing time and manage painted stock without damage or dust contamination. • Coordinate with the QC department for inspection and approvals. Dispatch Coordination • Plan and manage dispatches of painted radiators, tanks, and fabricated parts as per production and delivery schedules. • Liaise with stores, PPC, and logistics for packaging, loading, and documentation. • Ensure proper tagging, wrapping, and protection of painted items to avoid transit damage. • Maintain dispatch records including challans, gate passes, and transporter logs. • Coordinate with transporters and customers for timely pickups and deliveries. • Track pending dispatches and proactively resolve delays or issues. Qualifications & Experience • ITI / Diploma in Mechanical, Fabrication, or Paint Technology. • 5–8 years of experience in industrial painting & dispatch, preferably in transformer or heavy engineering industry. • Working knowledge of epoxy, PU, and enamel paints and painting tools. • Familiarity with dispatch operations and coordination in a manufacturing unit. Key Skills • Team leadership and manpower handling • Knowledge of industrial painting processes and quality inspection • Dispatch planning, documentation & coordination • Time management and problem-solving • Safety compliance and process discipline • MS Excel and basic ERP knowledge preferred To apply, please send your CV to info@trafopower.com. Show more Show less

Location: Gurugram, India Company: Neolytix Job Summary We are seeking an experienced HL7 Interface Developer or Healthcare Integration Engineer to join our team. This role is focused on designing and implementing healthcare data integration solutions using standards like HL7, FHIR, and other healthcare-specific protocols. The ideal candidate should have a solid understanding of middleware integration, healthcare APIs, and data interoperability in healthcare settings. Key Responsibilities Design, develop, and maintain interfaces to facilitate seamless data exchange between healthcare systems (EHR, LIS, PMS) using HL7, FHIR, and other relevant standards Build and manage APIs (RESTful and SOAP) for data integration between internal and external healthcare systems Implement data exchange solutions using EDI X12 formats (835, 837, 270/271), FHIR resources, and custom data models Work closely with the product manager and development team to understand requirements and translate them into technical specifications Troubleshoot and resolve complex interface issues, ensuring high system availability and data accuracy Document technical specifications, including interface maps, message definitions, and API documentation Stay current with new healthcare interoperability standards and integration technologies, suggesting new approaches to enhance data exchange capabilities Technical Skills Required Programming Languages: Java JavaScript/Node.js SQL C# Middleware Integration: Experience with integration engines like Mirth Connect, Cloverleaf, Ensemble, or Rhapsody Proficiency in mapping, routing, and transforming HL7 messages (ADT, ORM, ORU, DFT) Healthcare Standards: Strong knowledge of HL7 v2/v3, FHIR, CDA, DICOM, and EDI X12 (270/271, 837/835) Familiarity with SMART on FHIR and emerging frameworks like USCDI and TEFCA Soft Skills Excellent communication skills to interact with both technical and non-technical stakeholders Problem-solving abilities and attention to detail Ability to work both independently and as part of a global team Education Bachelor's or master's degree in computer science, Software Engineering, Health Informatics, or a related field Preferred Experience 5+ years of experience in healthcare integration and interoperability Experience in HIPAA compliance and security protocols Familiarity with cloud platforms Azure for healthcare data exchange Why Join Us? Neolytix is focused on building innovative healthcare solutions that empower providers to deliver better patient care. Join a passionate team that values creativity, excellence, and continuous learning. Powered by JazzHR 58Bdeq08BF Show more Show less

As a member of the S3 SoC DFT Team, the successful candidate will own the DFT SCAN ATPG, Coverage analysis and Silicon bringup Position includes test creation/development, characterization, data analysis, and silicon debug of DFT Scan/ATPG test in leading edge process technologies. AMDs environment is fast paced, results oriented and built upon a legion of forward-thinking people with a passion for winning technology! THE PERSON: A successful person in this role would be able to work in a collaborative team environment working with the RTL designers and other Verification Engineers to find creative ways to accelerate the identification of functional defects Strong self-driving ability, Should have excellent communication skills (both written and oral) Strong problem-solving skills KEY RESPONSIBILITIES: Working closely with the DFT Architecture and the various IP Design teams to align on the DFT requirements and successfully implementing the DFT at the SoC level PREFERRED EXPERIENCE: Experience in DFT architecture for complex chips Experience in RTL development using Verilog/System Verilog having worked on RTL for IP and SoC integration Proficient in doing basic unit-level verification using simulations. Experience with RTL quality check tools/methodologies such as Spyglass, CDC, Lint is required. Must have experience with integration of various IPs into complex SOCs. Exposure to Static timing analysis & Timing closure is required. Any prior experience with microprocessor designs is a plus. Scan/ATPG patterns & test flows development, debug, test and characterization Pre-Silicon test planning & validation, Engagement with Design Post Silicon Bring up of test patterns leading to optimization for mass production enablement Characterization and debug of Scan/ATPG test in the new silicon designs and process technologies Optimization of test flows for increased quality and cost improvement Analysis of part failures leading to test coverage and yield improvement Analysis of characterization data across PVT Excellent hands-on debug skills and scripting skills are critical. Must have good communication skills and the ability to work in a worldwide team environment. Knowledge & experience of low power concepts, clock gating, power gating is a plus Experience with post-silicon bring up is a plus ACADEMIC CREDENTIALS: E/B.Tech/M.E/M.Tech in Electrical/Electronics Engineering 8+ years experience in DFT design

Simulation, design and test of DC-DC regulator circuits Lead the overall power design architecture and topology, in conjunction with System Architects and System Engineers, for server and storage products Drive the DC-DC vendor and technology roadmap for server and storage products Lead the selection of off the shelf AC-DC and DC-DC power supplies for server and storage systems Use your technical knowledge and leadership skills to enable state-of-the-art electrical designs while meeting program schedule expectations Drive system modeling to create "right the first time" designs Drive design process improvements. Mentor younger engineers and technicians Create intellectual property that sets Viking apart from other server providers Drive fabrication partners to best-in-class performance. Develop product design requirements and documentation based on product requirements. Work with Program Management to create schedules that meet internal and customer requirements. Develop designs that satisfy costs, schedule, functionality, DFT and DFM requirements Participate as a leader or team member in the complete concept-to-release product development lifecycle Work closely with System Engineering, Software Engineering and Operations teams Provide Engineering-level Support for Customers and Operations for new and existing products Participate in continuous improvements in design process, quality, design and support activities

This position requires to deploy technical knowledge and leadership skills to enable state-of-the-art electrical designs while meeting program schedule expectations Generate engineering specifications and functional block diagrams for storage and server based designs Generate schematics and oversee PCB layout for storage and server based designs Drive system modeling to create "right the first time" designs Drive design process improvements. Mentor younger engineers and technicians Create intellectual property that sets Viking apart from other storage and server providers Drive fabrication partners to best-in-class performance. Develop product design requirements and documentation based on product requirements. Work with Program Management to create schedules that meet internal and customer requirements. Develop designs that satisfy costs, schedule, functionality, DFT and DFM requirements Participate as a leader or team member in the complete concept-to-release product development lifecycle Work closely with System Engineering, Software Engineering and Operations teams Provide Engineering-level Support for Customers and Operations for new and existing products Participate in continuous improvements in design process, quality, design and support activities Design storage and server based products

Experience : (2-5 Years Experience) Location : Bengaluru/Hyderabad Exciting opportunity to work on advanced chip designs in Bengaluru Experience in ATPG, Scan-Insertion, Simulation, BITS & MBIST required. Proficiency in tools like SpyGlass, Verdi, Tessent Fastscan, and TestKompress essential. BTech/MTech graduates (2019-2021)