1121 Dft Jobs - Page 31

NVIDIA has continuously reinvented itself. Our invention of the GPU sparked the growth of the PC gaming market, redefined modern computer graphics, and revolutionized parallel computing. Today, research in artificial intelligence is booming worldwide, which calls for highly scalable and massively parallel computation horsepower that NVIDIA GPUs excel. NVIDIA is a learning machine that constantly evolves by adapting to new opportunities that are hard to solve, that only we can address, and that matter to the world. This is our life s work , to amplify human creativity and intelligence. As an NVIDIAN, you ll be immersed in a diverse, supportive environment where everyone is inspired to do their best work. Come join our diverse team and see how you can make a lasting impact on the world! NVIDIA System-On-Chip (SOC) group is hiring for a Senior SOC Design Engineer! The complexity of the chips we build has increased manifold over the years. We are now packing tens of billions of transistors in a chip to meet the growing computing demand. We are looking for a star candidate with strong inclination in RTL integration and chip level front-end design, including padring, pinmuxing, SOC Assembly process, retiming etc. You must have a real passion for methodologies and automation solutions that enable SOC creation in the most optimized way. In this position, you will get the chance to build sophisticated Tegra SOCs, work closely with chip management to set ASIC execution timelines goals while directly interacting with System Architecture, unit-level ASIC, Physical Design, CAD, Package Design, DFT and other teams. Additionally, you will be involved in defining and crafting methodologies that build more efficient and flexible SOCs in future. What youll be doing: Drive SOC Assembly and design chip level functions for Tegra SOCs. Responsible for front-end design quality/correctness checks, reviews and driving those with multi-functional teams. Drive SOC execution across chip milestones working with all multi-functional teams to help define, track and drive complex dependencies. Define and develop system-level methodologies, tools, and IPs to build SOCs in an efficient and scalable manner. Identify difficulties and inefficiencies in the front-end chip implementation process and propose and implement ideas to solve them. What we need to see: B. Tech or M. Tech in Electronics Engineering. 5+ years of proven experience in chip design, specializing in SOC integration and design automation. Padring and fuse/floorsweep design experience is a bonus. Excellent analytical and problem-solving skills. Experience in RTL design (Verilog), System-On-Chip design/implementation flow. Strong coding skills in Perl, Python, or other industry-standard scripting languages. Exposure to various Chip Design Functions to be able to collaborate and solve complex multi-functional problems. Excellent interpersonal skills to work with multiple teams to drive consensus. Good teamwork spirit and collaboration skills with team members. Background in SOC Verification, Synthesis, Physical design and DFT is a bonus. Experience in RTL Build flows and Makefiles is a plus. #LI-Hybrid

Job Opening: Painting Supervisor – HMEL Bathinda Site (Punjab) Location: HMEL Refinery, Bathinda, Punjab Duty Cycle: 28 days work + 2 days off (Includes all bonuses & leave) Position: Painting Supervisor Qualification Required: Minimum 12th Pass Experience: Strong knowledge of industrial painting & blasting work Experience with Asian Paints Industrial Coatings Should be familiar with site protocols and safety practices Key Skills Required: Surface preparation & paint system application Understanding of blasting grades (Sa 2.5, Sa 3) Paint thickness checking using DFT gauges Knowledge of confined space work and tanking area safety Manpower handling & job allocation Basic understanding of paint data sheets and MSDS Coordination with QC & safety departments Report preparation for daily progress and paint consumption Work Includes: Supervising painting & blasting teams Ensuring work quality and adherence to safety standards Managing material and tool requirements on site Accommodation Provided Contact Now to Apply (Include your mobile number or email here) Job Types: Full-time, Permanent Pay: ₹21,500.00 - ₹35,000.00 per month Benefits: Flexible schedule Provident Fund Schedule: Day shift Fixed shift Night shift Work Location: In person

WHAT YOU DO AT AMD CHANGES EVERYTHING We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences - the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world’s most important challenges. We strive for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives. AMD together we advance_ Sr SILICON DESIGN ENGINEER The Role As a Silicon Design Engineer, you will work with formal experts and designers to verify formal properties and drive convergence. The Person You have a passion for modern, complex processor architecture, digital design, and verification in general. You are a team player who has excellent communication skills. You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems. Job Deliverables Setup ASIC QA flows for RTL design quality checks. Understand the design: top level interfaces, clock structure, reset structure, RAMs, CDC boundaries, power domains. Running Lint, Synthesis, LEC, Static timing analysis, CDC, RDC, DFT, CLP steps. Come up with clock constraints, false paths, multi-cycle paths, IO delays, exceptions and waivers. Checking the flow errors, design errors & violations and reviewing the reports. Debugging CDC, RDC issues and come up with the RTL fixes. Supporting DFX team for DFX controller integration, Scan insertion, MBIST insertion and DFT DRC & MBIST checks. Handling multiple PNR blocks, building wrappers and propagating constraints, waivers, etc. Flows or Design porting to different technology libraries. Generating RAMs based on targeted memory compilers and integrating with the RTL. Running functional verification simulations as needed. Job Requirements B.E/M.E/M.Tech or B.S/M.S in EE/CE with 5+ years of relevant experience ASIC design flow and direct experience with ASIC design in sub-20nm technology nodes Digital design and experience with RTL design in Verilog/SystemVerilog Modern SOC tools including Spyglass, Questa CDC, Cadence Conformal, VCS simulation Preferred experience in AXI4 or NOC protocols or DRAM memory interfaces. TCL, Perl, Python scripting Preferred Experience Project level experience with design concepts and RTL implementation for same Experience or familiarity with formal tools and/or functional verification tools by VCS, Cadence, Mentor Graphics Good understanding of computer organization/architecture Academic Credentials Bachelors or Masters degree in computer engineering/Electrical Engineering Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process. Show more Show less

Job Title: Electronics Engineer Experience: 3 to 5 Years Location: Gayatri Building, Technopark, Thiruvananthapuram (Work from Office) Overview: NilaSoft is seeking a skilled and motivated Electronics Engineer to join our growing engineering division. The selected candidate will be part of a collaborative team responsible for delivering high-quality electrical designs and technical documentation. You will contribute across the full product lifecycle—from PCB layout to documentation and design release—ensuring that all outputs align with best practices and industry standards. Key Responsibilities: Take ownership of Altium Designer tool usage and ensure all PCBAs conform to design standards and project requirements. Maintain a cloud-based component footprint library, ensuring complete accuracy and consistency across all NilaSoft PCB designs. Work with PCBA vendors to define design rules (DRC), manufacturing/test guidelines (DFM/DFT), and review protocols. Collaborate with design engineers to perform and review PCB layouts in accordance with project timelines. Standardize PCBA output formats and improve design release processes using version control systems. Create and manage technical documentation including wiring diagrams, cable designs, test protocols, procedures, and reports. Ensure timely document release through the Engineering Change Order (ECO) process, upholding version control and documentation standards. Required Qualifications: Bachelor’s or Master’s degree or a related field. Minimum 3 years of professional experience, particularly in PCB design. Proven ability to work proactively and collaboratively in engineering environments. Strong interpersonal and vendor coordination skills. Experience in developing and maintaining accurate component footprint libraries. Solid understanding of PCB manufacturing and assembly processes. Proficient in Altium Designer for schematic design, layout, and multi-layer board development. Track record of delivering reliable, rework-minimized PCBA designs. Skilled in ECO documentation and managing design release processes. Competent in technical drawing tools (e.g., Microsoft Visio) and committed to producing well-structured engineering documents. Why Join Us? Work on cutting-edge projects in a Semiconductor industry. Collaborative and innovative work environment. Opportunities for professional growth and development. If you're driven by engineering and thrive on innovation in the engineering space, we want to hear from you. Apply now and join our team! Please send your resume to hr@nila-soft.com and take the next step in your career! Show more Show less

Job Summary: We are looking for a highly experienced RTL Design Lead to drive the architecture, micro-architecture, and RTL development of digital IP/SoC blocks. The ideal candidate should have a solid background in RTL design using Verilog/SystemVerilog, along with experience in leading teams and interfacing with verification, DFT, and physical design teams. Key Responsibilities: Lead RTL design activities for complex IPs or SoC sub-systems. Work closely with architects to translate high-level specifications into micro-architecture and RTL. Drive design reviews, coding standards, and technical quality. Define and implement RTL design methodologies and flows. Collaborate with verification, DFT, synthesis, and backend teams to ensure successful integration and tapeout. Guide and mentor junior designers in the team. Support silicon bring-up and debug as needed. Required Skills: Proven track record of delivering IP or SoC designs from spec to GDSII. Experience in micro-architecture development , pipelining, and clock-domain crossing. Good understanding of ASIC design flow , including synthesis, STA, and linting. Hands-on experience with AMBA protocols (AXI/APB/AHB) and other standard interfaces. Strong debugging and problem-solving skills. Familiarity with low-power design techniques is a plus. Preferred Skills: Exposure to high-speed protocols (PCIe, USB, Ethernet, etc.). Familiarity with scripting languages (Python, Perl, TCL) to automate design tasks. Experience with tools like Synopsys DC, Spyglass, Verdi, VCS, etc. Prior experience in leading and mentoring a small team. Educational Qualification: Bachelor’s or Master’s degree in Electronics/Electrical Engineering or related field. Show more Show less

Overview QSC thrives where innovative technology and compelling audio-visual experiences intersect. For over 50 years, QSC has pioneered the technology and solutions that enable digital collaboration and meeting experiences, live performance audio, themed entertainment, and immersive cinema for our customers and partners around the world. A globally recognized innovator in the design, engineering, and manufacture of category-leading high-performance loudspeakers, digital mixers, power amplifiers, audio processors, digital cinema solutions, video, and control products. The PCB Design Engineer will be responsible for the layout of complex printed circuit boards including Digital, Analog & Mixed Signal technology. Candidate must have well-developed competency in PCB design & manufacturing and should have designed 2- 8 layers with flat & hierarchical schematics. By joining the QSC team, you will own the PCB layout, work with Electrical, Mechanical, Manufacturing Engineers, and Project leaders to ensure designs are on schedule with high quality and reliability in our Bangalore Design Center. You will be exposed to a challenging, collaborative, fun, and innovative environment. We encourage employees to take ownership, to color outside the lines, and to imagine possibilities. Our culture is casual but dynamic, with cross-functional teams collaborating to create memorable audio-visual experiences that bring joy to people, wherever they are. At QSC, fun and hard work go hand in hand. Join us and make a difference in the way people experience movies, meetings, presentations, live performances, and much more. This position is based in Bengaluru, India. Responsibilities Design PCB layout from a range of products within the audio, video & control industry Manage all activities associated with components life cycle longevity, ECAD library management, and PCB layout design. Work collaboratively with the design engineering team in multiple US locations Work with the NPI team in USA and China/Mexico to ensure PCB release documentation is complete and improves products manufacturability both at QSC manufacturing and CM sites. Provide engineering support for EOL/LTB for components and materials. Define technical and program direction, priority, and processes necessary to support the manufacture of products and improvement of manufacturing processes. Work with the Manager and Senior Engineer of Hardware Engineering to develop, track, and communicate tasks to meet timing and feature/quality objectives for new product development and sustaining engineering projects. Work closely with New Product Development, Manufacturing, Quality, and Test Participates in design reviews and provides design feedback to peers and design partners. Performs other duties as assigned. Qualifications B.E in Electrical Engineering or equivalent 5+ years of work experience designing, building, testing analog and digital circuits and related subsystems, ideally in commercial or professional video or audio/video markets is preferable. Must have good experience with Schematic design, Footprint/library creation (both SMT & thru-hole components) using IPC Standards, PCB layout using manual and auto routing, good knowledge of SMT packages, generation of design files, involved in complete documentation package including BOMs, fabrication and assembly drawing. Experience working with Altium, Cadence tool and Hyperlynx for Signal Integrity should be an added advantage. Independently handled PCB Design for Multilayer, Flex and HDI boards Good understanding of PCB stack up requirements to finalize the same based on design complexity and design requirements. Experience in Power supply layout design i.e., AC/DC, DC/DC converter and Audio amplifier and well versed in blind, buried laser micro via and technologies. Experience in High-speed design like DDRx, PCIe, MIPI, LVDS interfaces, Audio and Video Design i.e., Cameras, LCD, HDMI and familiar with transmission line concepts. Worked on High-Speed signal routing for 28Ghz or more, different routing topologies for BGA packages, high speed bus routing, differential pairs, and impedance control routing to meet signal integrity. Experience in DFA, DFM, DFT and EMI - EMC standards as well as processes and design implementation Candidate will also work directly with PCB fabricators on technical questions and fabrication issues and responsible for mentoring junior designers, if needed. Excellent communication and problem-solving skills: issue identification, resolution, providing mentorship and guidance to team members. Ability to work in an environment where process and standards are often not well defined and to develop and work to standards where standards do not exist. Experience implementing hardware-software & embedded concepts (FPGAs, SoCs, device drivers, soft-core processors, microcontrollers, micro-code) Results-driven, self-motivated, and enthusiastic Show more Show less

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. BE/BTECH---1-4 yrs Very good knowledge on SCAN/ATPG/JTAG/MBIST Experience with one or more chip tape out that includes chip ATE bring up. Experience on gate level simulation with no timing and timing (SDF) simulations (ATPG/MBIST/JTAG) Experience in Test structures for DFT, IP integration, ATPG fault models, test point insertion, coverage improvement techniques. Experience in scan insertion techniques at block level and chip top level. Experience on Memory BIST generation, insertion, verification on RTL/Netlist level. Good knowledge and understanding in Analog PHY and Analog Macro tests. Good knowledge and understanding on JTAG for IEEE 1149.1/IEEE1149.6 standards. Good knowledge on test mode timing constraints Good knowledge about running block level and chip STA flows. Cross domain knowledge to resolve DFT issues with design, synthesis, physical design, STA team. Proficiency in industry standard tools for scan insertion, ATPG, MBIST and JTAG (preferable Cadence/Tessent tools) Experience with post-silicon bring up and debug on ATE. Good knowledge on Perl/Tcl scription skills Very good team player capabilities and excellent communication skills to work with a variety of teams across the global organization. High sense of responsibility and ownership within the team for successful tape out and post-silicon bring up of project. We’re doing work that matters. Help us solve what others can’t. Show more Show less

Company: Qualcomm India Private Limited Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. Experience : Minimum 2 to 6 years of hands on experience in Synthesis and LEC Job Role Should have strong understanding and in-depth knowledge of Physical Synthesis and Synthesis methodologies with leading industry standard tools. Experience with writing timing constraints for synthesis, STA, timing closure and pipelining at different levels for performance optimization and timing closure. Experience in all aspects of timing closure for multi-clock domain designs. Should be familiar with MCMM synthesis and optimization. Should have good understanding of low-power design implementation using UPF. Experience with scripting language such as Perl/ Python, TCL. Experience with different power optimization flows or technique such as clock gating. Should be able to work independently with design, DFT and PD team for netlist delivery, timing constraints validation Should be able to handle ECOs and formal verification and maintain high quality matrix Skill Set Proficiency in Python/Tcl Familiar with Synthesis tools (Fusion Compiler/Genus) , Fair knowledge in LEC, LP signoff tools Proficient in VLSI front end design steps- Verilog/VHDL, Synthesis, QoR optimization & Equivalence Checking Familiarity with standard software engineering practices like Version Control, Configuration Management, Regression is a plus Should be sincere, dedicated and willing to take up new challenges Applicants : Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries). Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law. To all Staffing and Recruiting Agencies : Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications. If you would like more information about this role, please contact Qualcomm Careers.

Siemens EDA is a global technology leader in Electronic Design Automation software. Our software tools enable companies around the world to develop highly innovative electronic products faster and more efficiently. Our customers use our tools to push the boundaries of technology and physics to deliver better products in the increasingly complex world of chip, board, and system design. Position presents an opportunity to join the award winning and market leading Tessent team, India. The focus of the role is advanced design-for-test (DFT) insertion and automatic test pattern generation (ATPG) for semiconductor designs. It will involve understanding and supporting the latest DFT ATPG electronic design automation (EDA) technologies such as Tessent TestKompress and Streaming Scan Network (SSN). Someone in this role will gain a deep understanding of scan design, on-chip clock controls, and IJTAG infrastructure in support of scan testing. They will support the worldwide application engineering team on complex ATPG issues and build testcases for advanced DFT methodologies. This role is based in Noida. But you’ll also get to visit other locations in India and globe, so you’ll need to go where this job takes you. In return, you’ll get the chance to work with teams impacting entire cities, countries, and the shape of things to come. Responsibilities for this role include: Build and deliver in-depth technical presentations, develop training material, white papers, supplied articles, and application notes. Work with customers as well as Siemens stakeholders such as regional application engineers, global support engineers, and marketing. Are you expertized in working through complex technical issues and independently building solutions and new methodologies! Explain complex principles in simple terms to broad audiences. Some travel, domestic and international. Successful deployment of existing and new Tessent DFT products in customer designs by enabling AEs. Working closely with our key customers on deployment challenges. Working with PEs and R&D to ensure new product readiness testcase in form of testcases, documentation and trainings. Architecture reviews of customer designs. Closely working with AEs to gather top issues blocking their engagement's success. Deep learning opportunities for Tessent DFT products including opportunities to present at various conferences worldwide including ITC and Siemens U2U. We don’t need hard workers, just superminds! BS degree (or equivalent) in Electrical Engineering, Computer Science or related field is required with 10 - 15 years of experience. Knowledge of design logic design languages, tool usage, design flow steps required. We are looking for someone that has exposure to DFT or SoC design for complex ASICs / SOCs. ATPG, IEEE 1687 IJTAG, boundary scan (BSCAN), hierarchical DFT implementation. Knowledge of a scripting language like TCL. We need someone self-motivated and dedication to improvement with strong problem-solving skills. Excellent organizational skills, written and verbal English language communication skills. Proficiency in LINUX and Windows environments. The role presents many opportunities to build specialized DFT and ATPG knowledge. Publications and other promotions of methodologies is encouraged. We are Siemens A collection of over 377,000 minds building the future, one day at a time in over 200 countries. We're dedicated to equality, and we encourage applications that reflect the diversity of the communities we work in. All employment decisions at Siemens are based on qualifications, merit and business need. Bring your curiosity and creativity and help us shape tomorrow! We offer a comprehensive reward package which includes a competitive basic salary, variable pay, other benefits, pension, healthcare and actively support working from home. We are an equal opportunity employer and value diversity at our company. We do not discriminate based on race, religion, color, national origin, sex, gender, gender expression, sexual orientation, age, marital status, veteran status, or disability status. Transform the everyday #LI-EDA #LI-HYBRID

Role Description Role Proficiency: Execute any internal project or small tasks of customer project in any field of VLSI Frontend Backend or Analog design under minimal supervison from the Lead Outcomes As an Individual contributor work on any one task of RTL Design/Module in Verification/PD/DFT/Circuit Design/Analog Layout/STA/Synthesis/Design Checks/Signoff etc. Analyse and complete the assigned task in the defined domain(s) successfully on-time with minimal support from senior engineers Ensure quality delivery as approved by the senior engineer or project lead Measures Of Outcomes Quality –verified using relevant metrics by Lead/Manager Timely delivery - verified using relevant metrics by Lead/Manager Reduction in cycle time and cost using innovative approaches Number of trainings attended Outputs Expected Quality of the deliverables: Clean delivery of the module in-terms of ease in integration at the top level Ensure functional spec / design guidelines are met 100% of the time without deviation or limitation Documentation of the tasks and work performed Timely Delivery Meet project timelines as given by the team lead/program manager Help with intermediate tasks delivery by other team members to ensure progress Teamwork Teamwork participation; supporting team members in the time of need Able to perform additional tasks in case of any team member(s) is not available Innovation & Creativity Pro-actively plan approach towards repeated work by automating tasks to save design cycle time Participation in technical discussion training forum Skill Examples Languages and Programming skills:a. System Verilog Verilog VHDL UVM C C++ Assembly Perl TCL/TK Makefile Spice (any one) EDA Tools: a. Cadence Synopsys Mentor tool sets (one or more)b. Simulators Lint CDC/RDC DC/RTL-C ICC/Innovus/Olympus ETS/TK/FS PT/Tempus Calibre etc. (any one) Technical Knowledge: (any one)a. Understands IP Spec Architecture Design Micro Architecture Functional Spec Test Plan Verificationb. Knows Bus Protocol AHB/AXI/PCIe/USB/Ethernet/SPI/I2C Microprocessor architecturec. Good knowledge of Physical Design / Circuit Design / Analog Layout d. Good understanding of Synthesis DFT Floorplan Clocks P&R STA Extraction Physical Verificatione. Knowledge in Soft / Hard / Mixed Signal IP Design Processor Hardening FPGA Design Technology: CMOS FinFet FDSOI - 28nm / 22nm / 16ff / 10nm and below Required technical skills and prior design knowledge to execute assigned tasks Ability to learn new skills in case required technical skills are not present to a level needed to execute the project Able to deliver tasks with quality and 100% on-time per quality guidelines and GANTT Strong communication skills Good analytical reasoning and problem-solving skills with attention to detail Knowledge Examples Previous project experience in any of the design by executing any one of the following RTL Design / Verification / DFT / Physical Design / STA / PV / Circuit Design / Analog Layout etc. Good Understanding of the design flow and methodologies used in designing Understand the assigned tasks and have sufficient knowledge to execute the project tasks assigned by the client / manager per skill set Additional Comments Working knowledge of C-language. Coding C-tests. Debugged any CPU, Cluster env, ownership Worked on GIC setup and working. Other is BUS ,AMBA bus protocol, AHB,AXI,CHI,ACE deep understanding NoC properties verification. Skills Design verification,AMBA bus protocol,C- Language Show more Show less

RTL Design Engineers at Hyderabad We need experienced engineers to work on cutting edge technology and with complex functionality. Skills: Overall 3+ years industry experience with 2+ years in RTL Design and SoC Integration. Proven hands-on experience with RTL design for IP, the subsystem for ASIC. Hands-on experience with SoC integration issues like clocking, reset, memory map, hierarchical bus interconnect Knowledge of IP and SoC design flows and methodologies (Lint, CDC, Synthesis, power). Ability to work with local and remote teams (Architecture, DV, DFT, and Physical Design) Proficient in EDA tools used (e.g. Cadence/Mentor/Synopsys) Working knowledge of Unix, Linux and SKILL, Shell/Python Script ability. Quick learner with excellent interpersonal, verbal/written communications, problem solving and decision-making skills Traits: Adaptable, Flexible, Global Approach/Synthesis, creative and capable of working independently as well as a team player. Should have a strong sense of urgency. Solutions orientation; Quality driven; Execution minded Show more Show less

Senior Digital Design Manager We Are: At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation. You Are: We are seeking a highly motivated and experienced Digital Design Manager to lead a team of seasoned digital design engineers. You possess a deep understanding of the ASIC digital design flow, along with hands-on experience in HDL coding, RTL2GDSII flow, and scripting languages. You excel in managing project execution from defining specifications to silicon validation and characterization. Your leadership skills foster a collaborative environment, driving your team to meet stringent project requirements and deliver superior quality designs. With a minimum of 10 years in digital design and at least 3 years in a managerial role, you bring a wealth of knowledge and a proven track record of successful project completions. What You’ll Be Doing: Work closely with 3DIO Phy Architects to define specifications and micro-architecture, supporting early evaluations and feasibility studies to meet customer and system requirements. Lead the execution of digital design solutions for 3DIO Phy projects, ensuring robust and high-performance designs. Own the implementation of RTL in Verilog and sign-off using Spyglass CDC/RDC/Lint tools. Verify the RTL to test desired functionality, coverage, and corner cases using state-of-the-art verification methods. Oversee the full execution of RTL2GDSII, including timing constraints, DFT insertion, test coverage, formal verification, physical implementation, timing closure, physical verification, EMIR, and reliability sign-off. Support silicon validation and characterization through test chip implementation. Manage team members and operations, including career development and planning. The Impact You Will Have: Drive innovation in digital design solutions for 3DIO Phy projects, enhancing Synopsys' product offerings. Ensure high-quality and robust designs that meet customer requirements and improve system performance. Streamline the digital design process from specification to silicon validation, reducing time-to-market. Lead a team of talented engineers, fostering a collaborative and productive work environment. Contribute to the continuous improvement of design methodologies and best practices. Support Synopsys' position as a leader in the semiconductor industry through successful project deliveries. What You’ll Need: Excellent understanding of ASIC digital design flow with hands-on experience in HDL coding. Proficiency in writing synthesis constraints and basics of STA. Knowledge of Lint/CDC/RDC and RTL2GDSII flow. Working knowledge of scripting languages like Perl, Shell, Python, and Tcl. Experience in leading a small team of digital design engineers to execute projects. Knowledge of high-speed/DDR PHY Layer with lane redundancy implementation is highly desirable. Exposure to FIFO, test (ATE and characterization bench), silicon validation, and debugging. Familiarity with Synopsys toolset is highly desirable. Minimum 10 years of relevant digital design experience with at least 3 years as a people manager. B.E/B.Tech/M.Tech in ECE/EE. Who You Are: Strong leadership skills with a proven track record of managing and developing teams. Excellent problem-solving abilities and attention to detail. Effective communication skills, both written and verbal. Ability to work collaboratively in a fast-paced, dynamic environment. Innovative and proactive mindset with a passion for continuous improvement. The Team You’ll Be A Part Of: You will be part of a highly skilled and dynamic team focused on digital design for 3DIO Phy solutions. The team collaborates closely with architects, verification engineers, and other stakeholders to deliver high-quality and innovative design solutions. Together, you will drive the success of Synopsys' cutting-edge technology projects. Rewards and Benefits: We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process. Show more Show less

5+ years relevant experience Lead with experience in SoC Physical design across multiple technology nodes including 5nm for TSMC & Other foundries. Excellent hands-on P&R skills with expert knowledge in ICC/Innovus Expert knowledge in all aspects of PD from Synthesis to GDSII, Strong background in Floorplanning, Placement, CTS, Routing, P&R, Extraction, IR Drop Analysis, Timing, and Signal Integrity closure Experience at taping out multiple chips, strong experience at the top level at the latest technology nodes. CAD, Methodology & IP team collaboration is very essential for PD implementation, must conduct regular sync-ups for deliveries. Significant knowledge and preferably hands on experience on SoC STA, Power, Physical Verification and other sign-off. Good problem-solving capabilities, proactive, hardworking with strong interpersonal skills. Bachelor's Degree in Electrical, Electronics or Computer Engineering About Compan y: 7Rays Semiconductor Private Ltd. is a provider of end to end custom SoC design solutions ranging from SoC Architecture, RTL design, Design verification, DFT, Physical Design & Analog design. We are focused on providing services to top semiconductor and system companies to help them with the design of their complex SoCs .We work closely with our clients, building effective partnerships to deliver high-quality solutions tailored to their needs. With a strong engineering team and a proven track record of successful project executions, we are committed to excellence and innovation in SoC Design, Development and deployment of customers’ products . Show more Show less

Required Technical and Professional Expertise in DFT Minimum 5 to 12 years of relevant experience . Proficient in DFT architectures & methodologies that includes Scan, ATPG, MBIST, JTAG, etc. Sound knowledge of DFT tools/methodology from cadence /Synopsys/Mentor tools Good Experience in Python/Perl/TCL scripting Proven Communications skills and the ability to effectively work with cross functional teams across geographies are required Looking for a smart and enthusiastic Engineer to develop Design for Testability . Primary Skills : ATPG /SCAN /MBIST/JTAG and Tessent/Tetramax /Modus/Genus/DFTmax/SSN/SMS Notice : Immediate to 30 days

 Job Title: Electrical Engineer Experience: 3 to 5 Years Location: Gayatri Building, Technopark, Thiruvananthapuram (Work from Office) Overview: NilaSoft is seeking a skilled and motivated Electrical Engineer to join our growing engineering division. The selected candidate will be part of a collaborative team responsible for delivering high-quality electrical designs and technical documentation. You will contribute across the full product lifecycle—from PCB layout to documentation and design release—ensuring that all outputs align with best practices and industry standards. Key Responsibilities: Take ownership of Altium Designer tool usage and ensure all PCBAs conform to design standards and project requirements. Maintain a cloud-based component footprint library, ensuring complete accuracy and consistency across all NilaSoft PCB designs. Work with PCBA vendors to define design rules (DRC), manufacturing/test guidelines (DFM/DFT), and review protocols. Collaborate with design engineers to perform and review PCB layouts in accordance with project timelines. Standardize PCBA output formats and improve design release processes using version control systems. Create and manage technical documentation including wiring diagrams, cable designs, test protocols, procedures, and reports. Ensure timely document release through the Engineering Change Order (ECO) process, upholding version control and documentation standards. Required Qualifications: Bachelor’s or Master’s degree in Electrical Engineering or a related field. Minimum 3 years of professional experience, particularly in PCB design. Proven ability to work proactively and collaboratively in engineering environments. Strong interpersonal and vendor coordination skills. Experience in developing and maintaining accurate component footprint libraries. Solid understanding of PCB manufacturing and assembly processes. Proficient in Altium Designer for schematic design, layout, and multi-layer board development. Track record of delivering reliable, rework-minimized PCBA designs. Skilled in ECO documentation and managing design release processes. Competent in technical drawing tools (e.g., Microsoft Visio) and committed to producing well-structured engineering documents. Why Join Us? Be part of cutting-edge semiconductor automation projects. Work in a dynamic and growth-focused environment. Competitive compensation and career development opportunities. If you are passionate about creating engineering solutions and want to work in a high-tech industry, we would love to hear from you! Join our team! Rush your resume to hr@nila-soft.com Show more Show less

You will be part of the Multi Scale modelling team based in India. This is bps core team for advanced scientific modelling capabilities - computational fluid dynamics, finite-element structural analysis, and general multi-physics modelling - supporting all bps current and future businesses. The team solves complex problems through science-based modelling from molecular level to system scale for accelerating technology development, improving component reliability and lowering cost. Molecular modelling and computational simulations are indispensable tools for gaining a deeper understanding of the underlying mechanisms, predicting chemical behaviour, and accelerating the discovery of new materials and processes. Techniques, ranging from quantum mechanics to molecular dynamics simulations, allow us to investigate the structural, electronic, and kinetic aspects of reactions. Accountabilities: Work with multi-functional teams to understand scientific problems, and develop and implement computational models and algorithms to solve them. Analyze and interpret large-scale data sets. Stay updated with the latest advancements in computational science and related subject areas. Structure optimization: Determining the most stable arrangement of atoms in a molecule or complex system, considering factors such as bond lengths, angles, and dihedral angles. Methods: QM (e.g., DFT), MM, MD. Free energy calculations: Evaluating the free energy profiles of chemical reactions involved in electrochemical processes, such as oxidation-reduction reactions or electrode-electrolyte interactions. Methods: QM, thermodynamic integration, enhanced sampling (umbrella sampling, meta-dynamics). Electron transfer: Investigating the mechanisms and rates of electron transfer reactions, including electron transfer pathways, transition states, and activation energies. Methods: Time-dependent DFT, transition state theory. Solvation effects: Studying the influence of solvents on electrochemical reactions by considering solvent molecules interactions with the solute species and their impact on reaction kinetics and thermodynamics. Methods: Implicit, explicit solvent models, MD, QM/MM Redox properties: Predicting and analysing the redox potentials and electron affinities of molecules, ions, or complexes, which are crucial for understanding their electrochemical behaviour. Methods: QM Adsorption and surface phenomena: Simulating the adsorption of molecules or ions on electrode surfaces, examining the structure and stability of adsorbates, and evaluating their impact on electrochemical processes. Methods: QM, MD, Monte-Carlo. Design of electrochemical materials: Guiding the development of new materials for electrochemical applications by screening and optimizing molecular structures or complexes with desired electrochemical properties. Methods: high-throughput screening, machine learning, QSPR. Experience / Capabilities: PhD or equivalent experience in computational science, physics, mathematics, computer science or related field, or MS/BS/MEng/BEng with sufficient experience. Proven experience as a computational scientist or similar role. Knowledge of high-performance computing, data analysis, and scientific programming. Strong understanding of mathematical and statistical models.

To work as a Frontend engineer and taking care of Synthesis, LEC, CLP and Power Analysis for complex SoC projects. Job Description Implement high-performance, low-power, and area-efficient digital designs. Write and implement block level and top-level constraints for Synthesis, Static Timing Analysis . Optimize designs for power, performance, and area, and meet PPA goals. Power analysis using PT-PX or equivalent flow. Logic Equivalence Check (LEC) and Low Power Checks (CLP) at block and SoC level designs. Define and evaluate constraints and signoff Test/DFT mode timing requirements. Your Profile Strong fundamentals and experience in Synthesis and STA domains. Write and implement block level and top-level timing constraints for Synthesis Optimize designs for power, performance, and area, and meet design goals. Knowledge on Power analysis and PT-PX flow. Understanding of DFT flows, including scan insertion. Write and evaluate Test/DFT mode timing constraints. Thorough with Logic Equivalence Check debug capability. we'll known about UPF concepts and Low Power Checks at block and full chip level. Defining and verification of STA constraint for Functional and Test/SCAN Modes. Defining PVT s corners required for covering all desired scenarios for a design Knowledge on OCV/AOCV/POCV derates. Understanding of Prime-Time and TEMPUS tools, which helps in quick debugging of design/timing issues. VASTA timing closure based on chip IR drop. Knowledge on signal SI analysis and PT-PX flow

1. Graduate in Electronic Engineering or equivalent Minimum 3-5 years working experience in a similar industry Self-driven individual with hands-on skills. 2. Experience of embedded electronic Digital, Analog, Power electronic design. 3. Familiarity with ECAD tools for schematic capture, simulation, component selection, PCB design. 4. Experience of design for EMI/EMC. 5. Create manufacturing deliverables for prototypes and production. 6. Application of Design for Manufacturability (DFM) and Design for Testability (DFT) techniques. 7. Experience of debugging and fault finding in new and existing designs. 8. Experience of failure analysis and design review. 9. Experience with tools like Cadence or ORCad. 10. Creation of RFQ package for EMS provider and qualification of offers. 11. Experience of project/task planning. 12. Knowledge of project management tools. 13. Well versed with usage of test equipment like Multimeter, Oscilloscope and maintenance of laboratory equipment. 15. Familiarity with EMI, EMC, Environmental, Mechanical standards and type tests.

Nature of Assignment / Roles & Responsibilities Supporting in development of new product, re-design and value engineering of existing products. Execute VAVE study and identify the cost out opportunities which are quality neutral. Design schematic of digital, mix signal & power electronics circuits to meet the requirement. PCBA prototyping, board bring-up and test, debug. Create the design documents, validation and test plan mapping to the requirements. Provide detailed requirement for FCT of PCBA to make sure meet design requirement. Essential Skills: AnalogPrecision amplifiers, Thermocouples and RTD, Pressure and flow sensors, High speed ADC and DAC. PowerLDOs, Switching regulators, High voltage circuits and AC-DC converters. Communication/Data interfaceSPI, I2C, LVDS, USB, Ethernet ProcessorARM processor family, FPGA and CPLD Component EngineeringComponent life cycle and RoHS, Reach compliance. Full time experience in digital and analog hardware design with advanced microcontroller, FPGA/CPLD, high speed ADC and DAC. Good experience with PCBA process and board bringup. Strong knowledge in alternate design analysis/part substitute for cost out ideas including design analysis for functional, quality and reliability. Experience in practices for Design for Test (DFT) and Design for Manufacturing (DFM). Proficient in test and debugging instruments like DSO, logic analyzer, spectrum analyzer and EMI/EMC test simulators. Hands on experience on EDA Tools like Altium, OrCAD and Mentor Graphics etc.

-Lead the Architecture, Design and development of processor L2 and LLC (Last Level Cache) for high-performance IBM Systems. - Design and architect L2 cache and LLC as driven by capacity, latency, bandwidth, and RAS requirements. - Develop the features, present the proposed architecture in the High level design discussions - Develop micro-architecture, Design RTL, Collaborate with Verification, DFT, Physical design, FW, SW teams to develop the feature - Signoff the Pre-silicon Design that meets all the functional, area and timing goals - Participate in silicon bring-up and validation of the hardware - Lead a team of engineers, guide and mentor team members, represent as Logic Design Lead in global forums. - Estimate the overall effort to develop the feature. - Estimate silicon area and wire usage for the feature Required education Bachelor's Degree Preferred education Master's Degree Required technical and professional expertise -4+ years of relevant experience - At least 1 generation of processor L2 cache or LLC design delivery leadership. - Expertise in cache coherence protocols for symmetric multiprocessors (SMP), covering both chip SMP and multi-socket SMP. - Experience with NuCA / NuMA (Non-uniform Cache / Memory architecture) architectures and implementations. - Working knowledge of memory consistency, store ordering, weakly and strongly ordered memory. - Experience in logical and physical design of caches including directories (tags, set associative memories), data SRAM, design for low latency, multiple parallel finite state machine design, deadlock-free designs.

As Logic deisgn engineer for Power Management, you will be responsible for design and development of power management and sustainability features for high performance Processors chips. 1. Lead the Development of features - propose enhancements to existing features, new features, architecture in High level design discussions 2. Develop micro-architecture, Design RTL, Collaborate with the Verification, DFT, Physical design, FW, SW, Research teams to develop the feature 3. Guide junior engineers. Represent as Power engineer in various forums. 4. Signoff the Pre-silicon Design that meets all the functional, area and timing goals 5. Participate in silicon bring-up and validation of the hardwar 6. Estimate the overall effort to develop the feature and close design Required education Bachelor's Degree Preferred education Master's Degree Required technical and professional expertise 3-8 years of work experience of one or more areas Power management Architecture/ microarchitecture/ Logic design – Deep technical understanding of dynamic power saving, power capping, droop mitigation techniques. 1. Experience of working on Power Management designs handling Power/Performance States, Stop states of Core and Cache, Chip and System thermal management and power supply current over-limit management 2. Experience in working with research, architecture/ FW/ OS teams 3. Experience in low power logic design 4. Experience in working with verification, validation for design closure including test plan reviews, verification coverage 5. Good understanding of Physical Design, and able to collaborate with physical design team for floor-planning, placement of blocks for achieving high- performance design and timing closure of high frequency designs 6. Experience in silicon bring-up

As a Functional verification engineer, you will be working on IBM server processors/SOC or ASICs used in IBM servers. Understand the design specification , Memory and Memory BIST engine connections Develop the verification environment and test bench and creating testcases. Debug fails using waveform, trace tools and debug RTL code Develop skills in IBM Functional verification tools and methodologies. Work with design as well as other key stakeholders in resolving/debugging logic design issues and deliver a quality design Required education Bachelor's Degree Preferred education Master's Degree Required technical and professional expertise 5 + years of experience in Design Verification - demonstrated execution experience of verification of logic blocks Strong in DFT Verification - Demonstrated execution experience of verification of Memory BIST Knowledge of verification (any) methodology, Knowledge of HDLs (Verilog, VHDL) Good object-oriented programming skills in C/C++, and any of scripting languages like Python/Perl Development experience on Linux/Unix environments and in GIT repositories and basic understanding of Continues Integration and DevOps workflow Exposure in developing testbench environment, write complex test scenario, debugging and triaging fails Experience in verification coverage closure Hardware debug skills backed by relevant experience on projects Preferred technical and professional experience Knowledge of Chip-Initialisation , SCAN , etc Scripting Expertise backed up relevant experience in the same Writing Verification test plans Functional and code coverage analysis and debug

Analog and Connectivity Business Unit (AC) is looking for a Staff Product Engineer to join our team to drive the product development of state-of-the-art Sensor Signal Conditioning products. This is a unique and exciting opportunity to work with a cross-functional team to bring a product to volume production starting from product conception to production release. The job scope includes but is not limited to, development of the test plan to ensure datasheet specifications are met. Own the qualification plan and the execution to comply with various JEDEC/AEC quality standards. Own product quality assessment through reliability tests. Collaborate with multi-functional teams such as Design, Test, Applications and Failure Analysis teams during first silicon debug and to root cause field failures. Creation and maintenance of product BOM. Monitor production data to address yield and quality deficiencies using statistical analysis. KEY RESPONSIBILITIES Full PE product lifecycle ownership from concept to end of life with a focus on ensuring the delivery of the highest quality products to our end customers Definition of ATE test, qualification and manufacturing plans Product release into manufacturing with adherence to stringent tier 1-customer requirements Datasheet and automotive compliance reports Real time customer support for design, product and quality related issues Temperature/Voltage/Process characterization and production limit setting Product new product introduction and yield ownership Product BOM release and maintenance Excursion management for both suppliers and customers Use commercially available yield tools for yield improvement and monitoring, generate weekly reports and review with PE teams KPI achievement in product related deliverables including NPI execution and velocity, product cost (Gross margin improvements), product quality performance and failure analysis cycle times PAT, SYL, SBL, SPC limit and disposition optimizations to protect quality without excessive waste Qualifications 12+ years experience in product engineering. A strong analog circuit background is a must. Familiarity with ATE tester platforms (eg. Advantest 93K) Knowledge of analog and mix-signal circuitry and the common building blocks, device physics, test methodology and DFT knowledge Experience with common lab test equipment (DC power supply, oscilloscope, multi-meters etc). Bench characterization experience is a plus Familiarity with JEDEC/AEC qualification standards and stress test conditions. Experience with qual hardware/software development would be preferred Experience in yield management tools such as Spotfire, JMP. Apply statistical analysis to isolate the issue and make data-driven decisions Ability to managing supplier excursions and customer escalations through problem solving Knowledge of Semiconductor Failure Analysis is preferable Strong verbal and written communication skills A good team player. Effective in fast paced, dynamic work environment EDUCATION: BS in Electrical/Electronic Engineering MS in Electrical/Electronic Engineering is preferred Company Description Renesas is a global semiconductor company providing hardware and software solutions for a range of cutting-edge technologies including self-driving cars, robots, automated factory equipment, and smart home applications. We are a key supplier to the world s leading manufacturers of electronics you rely on every day; you may not see our products, but they are all around you. Renesas is a global, multi-billion dollar, publicly traded company headquartered in Japan, and has subsidiaries in 20 countries worldwide. Renesas is a dynamic, multi-cultural technology company where employees learn, mentor, innovate and thrive. Renesas is extending our share in fast-growing data economy-related markets such as infrastructure and data center and strengthening our presence in the industrial/IOT and automotive segments. Our solutions drive products developed by major innovators around the world. Join us and build your future by being part of what s next in electronics.

NVIDIA has continuously reinvented itself. Our invention of the GPU sparked the growth of the PC gaming market, redefined modern computer graphics, and revolutionized parallel computing. Today, research in artificial intelligence is booming worldwide, which calls for highly scalable and massively parallel computation horsepower that NVIDIA GPUs excel. NVIDIA is a learning machine that constantly evolves by adapting to new opportunities that are hard to solve, that only we can address, and that matter to the world. This is our life s work , to amplify human creativity and intelligence. As an NVIDIAN, you ll be immersed in a diverse, supportive environment where everyone is inspired to do their best work. Come join our diverse team and see how you can make a lasting impact on the world! Design-for-Test Engineering at NVIDIA works on groundbreaking innovations involving crafting creative solutions for DFT architecture, verification, and post-silicon validation on some of the industrys most complex semiconductor chips. What youll be doing: As an integral member in our team, you will work on exploring Applied AI solutions for DFX and VLSI problem statements. Architect end-to-end generative AI solutions with a focus on LLMs, RAGs Agentic AI workflows. Work on deploying predictive ML models for efficient Silicon Lifecycle Management of NVIDIAs chips. Collaborate closely with various VLSI DFX teams to understand their language-related engineering challenges and design tailored solutions. Partner closely with cross-functional AI teams to provide feedback and contribute to the evolution of generative AI technologies. Work closely with DFX teams to integrate Agentic AI workflows into their applications and systems and stay abreast of the latest developments in language models and generative AI technologies. Define how data will be collected, stored, consumed and managed for next-generation AI use cases. You will also help mentor junior engineers on test designs and trade-offs including cost and quality. What we need to see: BSEE or MSEE from reputed institutions with 2+ years of experience in DFT, VLSI Applied Machine Learning Experience in Applied ML solutions for chip design problems Significant experience in deploying generative AI solutions for engineering use cases Good understanding of fundamental DFT VLSI concepts - ATPG, scan, RTL clocks design, STA, place-n-route and power Experience in application of AI for EDA-related problem-solving is a plus Excellent knowledge in using statistical tools for data analysis insights Strong programming and scripting skills in Perl, Python, C++ or TCL desired Strong organization and time management skills to work in a fast-pace multi-task environment Self-motivated, independent, ability to work independently with minimal day-to-day direction Outstanding written and oral communication skills with the curiosity to work on rare challenges NVIDIA offers highly competitive salaries and a comprehensive benefits package. We have some of the most brilliant and talented people in the world working for us and, due to unprecedented growth, our world-class engineering teams are growing fast. If youre a creative and autonomous engineer with real passion for technology, we want to hear from you! #LI-Hybrid

NVIDIA has continuously reinvented itself. Our invention of the GPU sparked the growth of the PC gaming market, redefined modern computer graphics, and revolutionized parallel computing. Today, research in artificial intelligence is booming worldwide, which calls for highly scalable and massively parallel computation horsepower that NVIDIA GPUs excel. NVIDIA is a learning machine that constantly evolves by adapting to new opportunities that are hard to solve, that only we can address, and that matter to the world. This is our life s work , to amplify human creativity and intelligence. As an NVIDIAN, you ll be immersed in a diverse, supportive environment where everyone is inspired to do their best work. Come join our diverse team and see how you can make a lasting impact on the world! As part of the CAD team our engineers develop and support tools for all of NVIDIAs semiconductor products. In addition, they also develop in-house tools in the area of Design for Test (DFT) and Design for Power (DFP) using C++, Python, and TCL. Below are some of the some of the teams activities. We are a diverse team needing someone who is not afraid of a challenge. If this is you, come join us today. What you will be doing: Be responsible for architecting highly automated and customizable design flows using software engineering with modular design and object oriented techniques. Work closely with our diverse team members on flows to provide DFT, and DFP methodologies for industry-leading chip designs. Support development of tools using C++/Python/TCL. Work cross functionally with DFT Methodology, Implementation and design teams with important DFT and power tools development tasks. What we need to see: 2+ years of relevant work experience. Smart, diligent and motivated to work in our CAD group. BE or BTech or MTech in Computer Science, or Electronics Engineering, or Electrical Engineering, or equivalent experience. Knowledge or experience with DFT, DFP is a plus. Familiar with Verilog, VLSI and ASIC design principles, including knowledge of logic cells. Software engineering: software design, algorithms, and QA. Strong C++ programming experience. Solid programming and scripting skills in Python or TCL desired. Knowledge of GenAI, LLM, AI Code Generation is a plus. Having strong interpersonal skills will serve you well in this role. NVIDIA is widely considered to be one of the technology world s most desirable employers. We have some of the most forward-thinking and dedicated people in the world working for us. If youre creative and autonomous, we want to hear from you! #LI-Hybrid