1121 Dft Jobs - Page 29

Job Description Change the world. Love your job. The Validation Engineers at Texas Instruments are powered by a passion for continual improvement. Our solutions make a real difference and yours will, too. We make the semiconductor product design process easier and faster, which helps our customers succeed in today's fast-paced marketplace. Job Description: We are seeking a skilled and experienced Validation Engineer to take ownership of the validation function for our IC projects. The successful candidate will be responsible for designing and implementing comprehensive validation plans, developing validation hardware and software, automating test setups, and ensuring the overall quality of silicon sign-off for production release. Key Responsibilities: Lead Validation Efforts: Design and execute hands-on validation plans for automotive IC projects, including hardware and software development for validation and automation setups. Silicon Debugging: Perform silicon debugging to identify and resolve issues, ensuring production-grade quality for silicon sign-off. EMI/EMC Testing: Conduct in-house EMI/EMC tests and coordinate with external certification bodies for testing and approval. Cross-Functional Collaboration: Work closely with the Design and DV (Design Verification) teams pre- and post-PG to ensure closure on DFT (Design for Test), validation plans, and specifications. Collaborate with the Test team to correlate validation and test results, ensuring optimal fault coverage (FT) and a high-quality, cost-effective build. Partner with the Product Engineering team to execute all IC qualification requirements and oversee release to production. Project Management Support: Collaborate with Program Managers to ensure the project remains on track with respect to budget and schedule commitments. Participating in APPIT: actively plan and contribute to continues improvement of Automation Process Package IP and Test. Mentoring Junior Engineers : Mentor and guide new college graduate engineers (>2 NCGs), helping them develop skills in validation and ensuring their successful integration to the team QUALIFICATIONS Job Qualifications: Proven experience in silicon validation, including hands-on development of validation hardware, software, and test automation. Strong understanding of EMI/EMC testing and debugging, including experience coordinating with external certification houses. Experience working in cross-functional teams, including Design, DV, Test, and Product Engineering teams. Proven ability to mentor and guide junior engineers. Experience in contributing to APPIT and paper presentation skills Solid knowledge of DFT principles, silicon debug methodologies, and IC qualification processes. ABOUT US Why TI? Engineer your future. We empower our employees to truly own their career and development. Come collaborate with some of the smartest people in the world to shape the future of electronics. We're different by design. Diverse backgrounds and perspectives are what push innovation forward and what make TI stronger. We value each and every voice, and look forward to hearing yours. Meet the people of TI Benefits that benefit you. We offer competitive pay and benefits designed to help you and your family live your best life. Your well-being is important to us. About Texas Instruments Texas Instruments Incorporated (Nasdaq: TXN) is a global semiconductor company that designs, manufactures and sells analog and embedded processing chips for markets such as industrial, automotive, personal electronics, communications equipment and enterprise systems. At our core, we have a passion to create a better world by making electronics more affordable through semiconductors. This passion is alive today as each generation of innovation builds upon the last to make our technology more reliable, more affordable and lower power, making it possible for semiconductors to go into electronics everywhere. Learn more at TI.com . Texas Instruments is an equal opportunity employer and supports a diverse, inclusive work environment. If you are interested in this position, please apply to this requisition. ABOUT THE TEAM TI does not make recruiting or hiring decisions based on citizenship, immigration status or national origin. However, if TI determines that information access or export control restrictions based upon applicable laws and regulations would prohibit you from working in this position without first obtaining an export license, TI expressly reserves the right not to seek such a license for you and either offer you a different position that does not require an export license or decline to move forward with your employment. Show more Show less

Company Description Renesas is one of the top global semiconductor companies in the world. We strive to develop a safer, healthier, greener, and smarter world, and our goal is to make every endpoint intelligent by offering product solutions in the automotive, industrial, infrastructure and IoT markets. Our robust product portfolio includes world leading MCUs, SoCs, Analog and power products, plus Winning Combination solutions that curate these complementary products. We are a key supplier to the world’s leading manufacturers of electronics you rely on every day; you may not see our products, but they are all around you. Renesas employs roughly 21,000 people in more than 30 countries worldwide. As a global team, our employees actively embody the Renesas Culture, our guiding principles based on five key elements: Transparent, Agile, Global, Innovative, and Entrepreneurial. Renesas believes in, and has a commitment to, diversity and inclusion, with initiatives and a leadership team dedicated to its resources and values. At Renesas, we want to build a sustainable future where technology helps make our lives easier. Join us and build your future by being part of what’s next in electronics and the world. Job Description Design and implementation of Interconnect for next gen SoC design. Work with System architects and IP design owners to understand requirements for optimal implementation of interconnect. Prior experience with Arteris Flexnoc/NIC/NoC will be an added advantage. RTL development including tool flows like lint, CDC and synthesis. Knowledge of standard bus protocols mandatory for efficient interconnect design. Understand timing constraints, run synthesis and deliver synthesized netlist to PD team and provide constraints support for PD teams. Provide support to SoC integration and chip level pre/post-silicon debug. Work closely with Functional verification, performance verification and emulation teams to ensure all requirements are verified in pre Silicon environments. Provide post Silicon support related to device performance to validation and SW teams. Qualifications MTech/BTech in EE/CS with hardware engineering experience of 12+ years. Experience in micro-architecture development, RTL design, front-end flows (Lint, CDC, low-power checks, etc.), synthesis/DFT/FV/STA. Ability to understand IP needs and translate to optimal Interconnect design needs. Experience with post-silicon bring-up and debug is a plus. Able to work with teams across the globe and possess good communication skills Additional Information Renesas is an embedded semiconductor solution provider driven by its Purpose ‘ To Make Our Lives Easier .’ As the industry’s leading expert in embedded processing with unmatched quality and system-level know-how, we have evolved to provide scalable and comprehensive semiconductor solutions for automotive, industrial, infrastructure, and IoT industries based on the broadest product portfolio, including High Performance Computing, Embedded Processing, Analog & Connectivity, and Power. With a diverse team of over 21,000 professionals in more than 30 countries, we continue to expand our boundaries to offer enhanced user experiences through digitalization and usher into a new era of innovation. We design and develop sustainable, power-efficient solutions today that help people and communities thrive tomorrow, ‘ To Make Our Lives Easier .’ At Renesas, You Can Launch and advance your career in technical and business roles across four Product Groups and various corporate functions. You will have the opportunities to explore our hardware and software capabilities and try new things. Make a real impact by developing innovative products and solutions to meet our global customers' evolving needs and help make people’s lives easier, safe and secure. Maximize your performance and wellbeing in our flexible and inclusive work environment. Our people-first culture and global support system, including the remote work option and Employee Resource Groups, will help you excel from the first day. Are you ready to own your success and make your mark? Join Renesas. Let’s Shape the Future together. Renesas Electronics is an equal opportunity and affirmative action employer, committed to supporting diversity and fostering a work environment free of discrimination on the basis of sex, race, religion, national origin, gender, gender identity, gender expression, age, sexual orientation, military status, veteran status, or any other basis protected by law. For more information, please read our Diversity & Inclusion Statement. Show more Show less

Experience: 3 to 5 Years Location: Gayatri Building, Technopark, Thiruvananthapuram (Work from Office) Overview: NilaSoft is seeking a skilled and motivated PCB Design Engineer to join our growing engineering division. The selected candidate will be part of a collaborative team responsible for delivering high-quality electrical designs and technical documentation. You will contribute across the full product lifecycle—from PCB layout to documentation and design release—ensuring that all outputs align with best practices and industry standards. Key Responsibilities: Take ownership of Altium Designer tool usage and ensure all PCBAs conform to design standards and project requirements. Maintain a cloud-based component footprint library, ensuring complete accuracy and consistency across all NilaSoft PCB designs. Work with PCBA vendors to define design rules (DRC), manufacturing/test guidelines (DFM/DFT), and review protocols. Collaborate with design engineers to perform and review PCB layouts in accordance with project timelines. Standardize PCBA output formats and improve design release processes using version control systems. Create and manage technical documentation including wiring diagrams, cable designs, test protocols, procedures, and reports. Ensure timely document release through the Engineering Change Order (ECO) process , upholding version control and documentation standards. Required Qualifications: Bachelor’s or Master’s degree or a related field. Minimum 3 years of professional experience, particularly in PCB design. Proven ability to work proactively and collaboratively in engineering environments. Strong interpersonal and vendor coordination skills. Experience in developing and maintaining accurate component footprint libraries. Solid understanding of PCB manufacturing and assembly processes. Proficient in Altium Designer for schematic design, layout, and multi-layer board development. Track record of delivering reliable, rework-minimized PCBA designs. Skilled in ECO documentation and managing design release processes. Competent in technical drawing tools (e.g., Microsoft Visio) and committed to producing well-structured engineering documents. Why Join Us? Work on cutting-edge projects in a Semiconductor industry. Collaborative and innovative work environment. Opportunities for professional growth and development. If you're driven by engineering and thrive on innovation in the engineering space, we want to hear from you. Apply now and join our team! Please send your resume to hr@nila-soft.com and take the next step in your career! Show more Show less

About Elecbits: Elecbits is India’s leading full stack, vertically integrated Electronics engineering and manufacturing company, enabling customers like Panasonic, Yamaha, Maruti Suzuki, OLA, Valeo and more than 200 others to go from idea to mass production in a simpler, faster and scalable manner. We are on a mission to build the digital and physical infrastructure for every electronics enterprise on the planet. About the role: Roles and Responsibilities- Strategic Leadership & Planning: Lead the strategic planning and execution of all electronics engineering initiatives, encompassing both hardware and firmware, along with key mechanical considerations. Act as a solution architect, providing technical guidance and defining robust system architectures for new and existing products. Drive the planning and development lifecycle from conception through to mass production, ensuring alignment with business objectives. Oversee the continuous improvement and automation of engineering processes to enhance efficiency and quality. Team Building & Management: Build, mentor, and lead a high-performing team of Electronics engineers across various electronics engineering disciplines (hardware, firmware, mechanical, testing, etc.). Foster a collaborative and innovative team environment, promoting professional growth and knowledge sharing. Develop and implement strategies for talent acquisition and retention within the electronics engineering department. Maintain strong connections and networks within the industry to facilitate team growth and access to expertise. Product Development & Execution: Oversee the end-to-end development of complex electronics products, ensuring adherence to quality, cost, and timeline targets. Ensure a deep understanding of the product roadmap and technical requirements across the team. Drive the development of production-level hardware and firmware, ensuring reliability, scalability, and manufacturability. Establish and enforce rigorous development processes and best practices (e.g., design reviews, testing protocols, documentation). Technology & Infrastructure: Stay abreast of emerging technologies and industry trends, evaluating their potential impact and applicability to our products. Maintain strong connections with leading semiconductor companies such as STM, Qualcomm, NXP, Renesas, etc., to leverage their technologies and support. Oversee the development and maintenance of robust engineering infrastructure, including labs, tools, and test environments. Implement process automation initiatives to streamline workflows and improve development efficiency. Industry Influence & Presence: Cultivate a strong social presence and influence within the electronics engineering community. Represent the company at industry events, conferences, and technical forums. Leverage "Tech connections" to foster collaborations and partnerships that benefit product development and innovation. Skills Required- Bachelor's or Master's degree in Electrical Engineering, Electronics Engineering, Computer Engineering, or a related field. 10-14 years of progressive experience in electronics engineering, with a significant portion in a leadership role. Proven experience in managing a team of 50 - 100 engineers in various categories (hardware, firmware, embedded systems, etc.). Exceptional solution architecture skills with the ability to define robust and scalable system designs. Deep understanding and hands-on experience in complex product development across multiple domains (e.g., IoT, consumer electronics, automotive, industrial). Demonstrable experience in bringing products from concept to production at scale, including DFM/DFT considerations. Strong knowledge and experience in both hardware design (schematic capture, PCB layout, component selection) and embedded firmware development (C/C++, RTOS, microcontroller programming). Strong existing connections and relationships with key semiconductor companies (e.g., STM, Qualcomm, NXP, Renesas). Excellent communication, interpersonal, and leadership skills, with the ability to inspire and motivate large teams. A strong social presence and influence within the broader electronics engineering community. Show more Show less

NVIDIA has continuously reinvented itself over two decades. Our invention of the GPU in 1999 sparked the growth of the PC gaming market, redefined modern computer graphics, and revolutionized parallel computing. More recently, GPU deep learning ignited modern AI — the next era of computing. NVIDIA is a “learning machine” that constantly evolves by adapting to new opportunities that are hard to solve, that only we can tackle, and that matter to the world. This is our life’s work, to amplify human imagination and intelligence. Make the choice to join us today. NVIDIA is an equal opportunity employer. We are now looking for a DFT Verification Engineer. Design-for-Test (DFT) Engineering at NVIDIA works on groundbreaking innovations every day involving crafting creative solutions for DFT architecture, implementation, verification and post-silicon validation on some of the industry's most complex semiconductor chips. We use the best industry tools and go beyond with internal methodologies to address some of NVIDIA's unique challenges. We are looking for you to implement the best verification methodologies for DFT IP at unit and system levels. You will bring in expertise in SystemVerilog, UVM, FPGA and Emulation application in DFT domain. What You'll Be Doing As a member of our team, You will build "state of the art" verification test benches and methodologies to verify DFT features in complex IP's/Sub-systems/SOC's. Develop and own verification environment using UVM or equivalent. Your responsibility will include to build reusable bus functional models, monitors, checkers and scoreboards. Own functional coverage driven verification closure and own design verification sign-offs at multiple levels. Collaborate closely with multi-functional teams like chip architecture, ASIC design, functional verification, and post silicon teams. Will be part of innovation to strive to improve the quality of DFT methods What We Need To See BSEE with 3+ or MSEE with 2+ years of experience in IP verification or related domains Expertise in System Verilog and verification methodologies like UVM/VMM. Expertise in prototyping, verification and debug tools (Emulation, FPGA, VCS, Debussy, Formality, PrimeTime etc). Good exposure to ASIC design methodologies: RTL design, clocking, timing and low-power architectures. Strong programming/scripting skills in C++, Perl, Python or Tcl Excellent written and oral communication skills Excitement to work on rare challenges Strong analytical and problem solving skills Ways To Stand Out From The Crowd Strong experience or interest in both DFT and RTL Verification domains Knowledge in Formal verification methodologies and tools for IP and SoC level verification Hands-on experience in post silicon debug on ATE and/or system labs. JR1998780 Show more Show less

Arcadis is the world's leading company delivering sustainable design, engineering, and consultancy solutions for natural and built assets. We are more than 36,000 people, in over 70 countries, dedicated to improving quality of life. Everyone has an important role to play. With the power of many curious minds, together we can solve the world’s most complex challenges and deliver more impact together. Role Description: You will support a wide range of transport planning services, including but not limited to: Multimodal transport strategy development Future mobility planning (EVs, MaaS, alternative fuels) Business case and funding bid support Multimodal and junction modelling Pedestrian and active travel planning Feasibility studies and concept design Transport inputs to masterplanning and planning applications Behaviour change and sustainable travel strategies Local operational modelling and transport assessments Role Accountabilities: Experience in transport modelling (e.g. highways, public transport, multimodal) Knowledge of strategic model development and application Proficiency in tools such as VISUM, VISSIM, SATURN, CUBE or Experience with operational modelling (e.g. LINSIG, SYNCHRO, AIMSUN) Strong skills in data analysis, spreadsheet modelling, and GIS Ability to contribute to technical reports and client communication Good problem-solving, organisation, and communication skills A proactive, motivated approach with a willingness to learn and collaborate Nice to have : Familiarity with DfT’s Transport Appraisal Guidance (TAG) Exposure to working with public sector clients (e.g. HS2, National Highways, DfT) or developers Interest or experience in Python coding or data analysis Qualifications and Experience: Degree in a relevant field (e.g. Transport Planning, Civil Engineering, Geography, Economics, Mathematics, or Data Science) Working towards or interested in professional qualification (CIHT, ICE, RTPI) Why Arcadis? We can only achieve our goals when everyone is empowered to be their best. We believe everyone's contribution matters. It’s why we are pioneering a skills-based approach, where you can harness your unique experience and expertise to carve your career path and maximize the impact we can make together. You’ll do meaningful work, and no matter what role, you’ll be helping to deliver sustainable solutions for a more prosperous planet. Make your mark, on your career, your colleagues, your clients, your life and the world around you. Together, we can create a lasting legacy. Join Arcadis. Create a Legacy. Our Commitment to Equality, Diversity, Inclusion & Belonging We want you to be able to bring your best self to work every day which is why equality and inclusion is at the forefront of all our activities. Our ambition is to be an employer of choice and provide a great place to work for all our people. We are an equal opportunity employer; women, minorities, and people with disabilities are strongly encouraged to apply. We are dedicated to a policy of non-discrimination in employment on any basis including race, caste, creed, colour, religion, sex, age, disability, marital status, sexual orientation, and gender identity. #JoinArcadis #CreateALegacy #Hybrid Show more Show less

Job Description Summary Perform the daily operations of plants to ensure reliability and consistency on the production line. Includes Service Shops. Accountable for the quality of own work. Subject to direct operations supervision/prescribed work instructions/systems checking. Executes within a well-defined operations framework. There is generally a step by step sequence of standard operational tasks which need to be followed to achieve an end result. Job Description Company Overview : Working at GE Aerospace means you are bringing your unique perspective, innovative spirit, drive, and curiosity to a collaborative and diverse team working to advance aerospace for future generations. If you have ideas, we will listen. Join us and see your ideas take flight! Site Overview Our Multi-modal Manufacturing Facility (MMF) in Pune plays a crucial role in manufacturing key aerospace components, supporting not only India’s defense and commercial sectors but also global aviation supply chains. Our relationships with Indian suppliers, combined with our world-class local facilities and global reach, continue to shape India’s aerospace ecosystem. Role Overview Manufacturing Test Engineer will be the primary interface between manufacturing, program management, Requisition engineering & quality for all manufacturing test process development, conducting Electrical Testing and trouble shooting. Essential Responsibilities Design, develop and implement cost-effective methods of testing and troubleshooting systems and equipment Serve as an active member of new product development teams and has the lead responsibility for ensuring design for testability (DFT) Define the software and hardware requirements for production level tests Justify and procures test hardware and other capital expenditures needed for production test Setup and deploys test hardware, software, stations, etc. in production Train test technicians in the use of test equipment, test process and coach the testing team Communicate and implement Engineering Change Order (ECO) driven changes to test process and fixtures for all levels of testing Work with cross-functional teams to plan test development schedules and allocate resources Benchmark and investigate new test technologies and test equipment for current and future products Lead and drive continuous improvement projects Other duties as required Qualifications / Requirements Bachelor’s Degree in Electrical/Electronic Engineering Minimum of 5-8 years related working experience in testing Power cabinets, control panels, converters, inverters, DCS, switch gears etc. Preferred Qualifications Experience with automated test equipment ( functional testing, Load test , Hydro test ,etc) Experience developing hardware/software test processes Experience with LabVIEW , Toolbox ST Whether we are manufacturing components for our engines, driving innovation in fuel and noise reduction, or unlocking new opportunities to grow and deliver more productivity, our GE Aerospace teams are dedicated and making a global impact. Join us and help move the aerospace industry forward. Additional Information Relocation Assistance Provided: Yes Show more Show less

Education: BE/BS/Mtech/M.E degree in Electrical/Electronics/Computer science from a reputed institute Responsibilities: Translate requirements to design specification by working closely with system architects Translate the design specification to optimal digital micro-architecture RTL coding using Verilog and System Verilog Building reusable sub-systems and systems, and drive automation with hands-on contribution during the integration of IP Manage the complexity of Safety, Security and Low-power as overlays on vanilla sub-system architectures Continuously improve the development and support model employed on Digital Processing sub-systems to ensure a high level of scalability and efficiency in product engagements Support simulation, DFT and silicon verification and validation of sub-systems, test and evaluation of ASIC products and FPGA development systems Meet power, performance and area goals by micro-architecture optimization Work closely with DV team to develop test-plans Front end implementation - Lint/CDC , synthesis, Timing constraint development Work closely with DFT and PD teams for signoff Support Silicon validation Mentor junior design engineers Minimum Qualifications: BE/BS/Mtech/M.E degree in Electrical/Electronics/Computer science from a reputed institute 10 years of relevant experience Strong engineering background in embedded system design, including ASIC microarchitecture, computer architecture, SoC architecture, and custom or standard DSP or hardware accelerator microarchitecture Strong hands-on RTL coding experience and debugging skills Digital Subsystem, clocking and full chip integration experience Expertise in timing constraints development and critical path timing closure Experience with silicon and software product development and understanding the product development lifecycle Knowledge of industry standard bus protocols such as AHB, APB, AXI Experience in digital signal processing and Matlab modeling is highly desirable Excellent verbal and written communication skills to work effectively with teams spread geographically Experience in mentoring junior engineers

Education: BTech/MTech degree in Electrical/Electronics/Computer science from a reputed institute Job Responsibilities: Translate requirements to design specification by working closely with system architects Translate the design specification to optimal digital micro-architecture RTL coding using Verilog and System Verilog Continuously improve the development and support model employed on Digital Processing sub-systems to ensure a high level of scalability and efficiency in product engagements Support simulation, DFT and silicon verification and validation of sub-systems, test and evaluation of ASIC products and FPGA development systems Meet power, performance and area goals by micro-architecture optimization Work closely with DV team to develop test-plans Front end implementation - Lint/CDC , synthesis, Timing constraint development Support Silicon validation Job Requirements: BTech/MTech degree in Electrical/Electronics/VLSI with 3-6 years of experience from reputed institutes Strong hands-on RTL coding experience and debugging skills Expertise in timing constraints development and critical path timing closure Coding up in C tests on M3 Series Cortex based products. Expertise in automation and scripting languages like Perl, Python, and shell scripting Proficient in Version control systems, such as Perforce, SVN, SOS Proficient in Verilog, System Verilog and UVM Ability to manage multiple tasks and work effectively in a fast-paced environment Able to communicate effectively

We are seeking a highly skilled and experienced DFT Engineer to join our dynamic team of engineers to develop the next-generation Flash Controllers. As an SoC DFT Engineer, you will be responsible for defining and implementing industry leading DFT solutions, with emphasis on SCAN, MBIST, BSDL etc. The ideal candidate will have a deep understanding of DFT Architecture, Implementation flow, MBIST, SCAN ATPG & Simulation expertise. ESSENTIAL DUTIES AND RESPONSIBILITIES: DFT Architecture definitions for SoC development Leading complex activities and providing solutions for complex DFT problems. Collaborate with cross-functional teams to define and refine SoC DFT requirements, ensuring alignment with industry standards and customer needs. Working closely with the Design, Verification, Physical Design & Test Engineering teams while guiding them on the test requirements and methodologies. Work closely with the Product Engineering team and understand the test requirements, get involved in complex silicon debugs. Evaluate all aspects of the SoC DFT flow from requirements, through detailed definitions, and work closely with the CAD to continuously improve the DFT methodology. Qualifications B.Tech / M,Tech / Phd in Electronics, Computer science or Electrical Engineering Minimum 15+ years of experience in DFT Strong understanding of DFT Architecture

Are you looking for a unique opportunity to be a part of something greatWant to join a 20,000-member team that works on the technology that powers the world around usLooking for an atmosphere of trust, empowerment, respect, diversity, and communicationHow about an opportunity to own a piece of a multi-billion dollar (with a B!) global organizationWe offer all that and more at Microchip Technology, Inc. People come to work at Microchip because we help design the technology that runs the world. They stay because our culture supports their growth and stability. They are challenged and driven by an incredible array of products and solutions with unlimited career potential. Microchip s nationally-recognized Leadership Passage Programs support career growth where we proudly enroll over a thousand people annually. We take pride in our commitment to employee development, values-based decision making, and strong sense of community, driven by our Vision, Mission, and 11 Guiding Values ; we affectionately refer to it as the Aggregate System and it s won us countless awards for diversity and workplace excellence. Our company is built by dedicated team players who love to challenge the status quo; we did not achieve record revenue and over 30 years of quarterly profitability without a great team dedicated to empowering innovation. People like you. Visit our careers page to see what exciting opportunities and company perks await! Job Description: Microchip AES Design team in Bangalore is looking for an experienced and motivated Design-For-Test Senior Engineer to provide test hardware solution for various microchip B usiness units. As a member of test development team, you will be responsible for understanding the existing DFT test structures and clock strategy used across multiple business units and provide architectural improvements to improve test coverage . The candidate should have experience with ATPG and MBIST. The candidate should have in depth knowledge of Tessent /Modus tool execution. Requirements/Qualifications: Qualified applicants will possess the following skills / experience: Hands on expertise on handling DFT on hierarchical designs. Hands on expertise on Tessent /Modus ATPG tool for DFT setup and pattern generations. Hands on expertise on Tessent /Modus MBIST tool for MBIST hardware generation. Hands on expertise on Tessent /Modus diagnosis tool for on-silicon debug. Hands on expertise SCAN pattern simulations and debug. ATPG with the pattern delivery to the test engineering team . Sound knowledge of Scan Stitching, Scan Compression, MBIST JTAG Techniques . Should have good post silicon DFT bring-up and debug experience . Should have a good knowledge in simulation debug and prior experience at SoC level . Excellent written and verbal communication skills. Self-motivated team player with strong problem-solving skills to collaborate with various teams to achieve desired goals. Experience: Bachelors/Masters in Electronics or equivalent degree with 7 + years of experience Travel Time: 0% - 25% To all recruitment agencies : Microchip Technology Inc. does not accept unsolicited agency resumes. Please do not forward resumes to our recruiting team or other Microchip employees. Microchip is not responsible for any fees related to unsolicited resumes.

NVIDIA has continuously reinvented itself. Our invention of the GPU sparked the growth of the PC gaming market, redefined modern computer graphics, and revolutionized parallel computing. Today, research in artificial intelligence is booming worldwide, which calls for highly scalable and massively parallel computation horsepower that NVIDIA GPUs excel. NVIDIA is a “learning machine” that constantly evolves by adapting to new opportunities that are hard to solve, that only we can address, and that matter to the world. This is our life’s work , to amplify human creativity and intelligence. As an NVIDIAN, you’ll be immersed in a diverse, supportive environment where everyone is inspired to do their best work. Come join our diverse team and see how you can make a lasting impact on the world! We are now looking for highly driven and innovative ASIC / Hardware Engineers. We are looking for bright engineers across our hardware engineering groups to help us Architect, Design and verify our next generation GPUs, CPU and SoCs meant to accelerate the performance of Data Center, Machine Learning, Autonomous Driving, Ray Tracing and many more exciting applications. You will get to work on high performance GPU / SOC/ CPU across Memory sub-systems, Graphic processing units, NOC based Interconnect Fabric, High speed IO's etc. What You'll Be Doing Work on hardware models of different levels of extraction, including performance models, RTL test benches and emulators to find performance bottlenecks in the system. Work closely with the architecture and design teams to explore architecture trade-offs related to system performance, area, and power consumption. Understand key performance use cases or the product. Develop workloads and test suites targeting graphics, machine learning, automotive, video, compute vision applications running on our products. You will be responsible to make architectural trade-offs based on feature/performance/power requirements, analyse system implications, come up with the micro-architecture, implement RTL, drive the verification, close timing, and support silicon validation. Developing test plans, tests and verification infrastructure for complex IP's/sub-system/SOC's. Creating verification environment using UVM methodology and reusable bus functional models, monitors, checkers and scoreboards. Driving functional coverage driven verification closure. Develop and enhance timing analysis/signoff work-flow from frontend (pre-layout) to backend (post-layout) at both chip and block level. Develop custom timing scripts using tcl/primetime for clock skew analysis, special circuits such as clock dividers, core logic IO macros interfaces such as PCI-E, Frame-Buffer/Memory, HDMI, etc. Chip level Integration, physically partitioning and floor planning along with Physical Verification and EM IR Drop You will be responsible for the design and implementation of state-of-the-art designs in test access mechanisms, IO BIST, memory BIST and scan compression. In addition, you will help develop and deploy DFT methodologies for our next generation products. Be apart of innovation to strive improve the quality of DFT methods. Work with architects, designers and post-silicon teams. What We Need To See BTech/MTech with 2+ years of experience in micro-architecture, RTL development of complex designs. Possess strong digital design fundamentals. Preferably have a deep understanding of ASIC design flow including RTL design, verification, logic synthesis, prototyping, DFT, timing analysis, floor planning, ECO, bring up and lab debug is a prerequisite for this role. If you have experience in at least a few of the following skills, we will have an excellent match for our needs: GPU / CPU / SOC Performance verification and analysis. CPU, Memory controller, Bus Interconnect, Cache coherency IP / SOC Design, Micro-architecture across High Speed IO controller (UFS/PCIE/ XUSB), Network on Chip / 10G Ethernet MAC and (or) Switch IP / SOC Graphics Processing Unit (GPU Design & Verification) BOOT and Power management features for complex SOC’s FPGA Prototype with prior experience in HAP Good debugging and analytical skills. Good interpersonal skills and ability to work as an excellent teammate Excellent communication skills to collaborate with cross-cultural teams and work in a matrix organization With highly competitive salaries and a comprehensive benefits package, NVIDIA is widely considered to be one of the technology world’s most desirable employers. We have some of the most brilliant and talented people in the world working for us. If you're creative and independent, with a genuine real passion for technology, we want to hear from you. JR1978791 Show more Show less

Eligibility Criteria Educational qualification: Bachelor of Electrical/Electronics Engineering, MTech is an added advantage. Years of Experience: 4+ years of relevant experience in schematic & PCB design & testing, cable design Primary Responsibility Responsible for executing Electrical Engineering technical disciplines with primary focus on designing and modifying schematic and PCB layout. Board Design, Electronics Circuits including microcontroller/FPGA based designs, sensor interfaces, analog signal conditioning circuits, power supplies, ethernet based communication interfaces, Wireless Interfaces, Wireless Chargers etc. Creation of system interconnects diagram and electrical schematics diagram based on requirements received from cross-disciplinary teams Own the Cable Designs, drafting of cables, creation of harness drawings Work with cross-disciplinary teams (including mechanical, electro-mechanical, software, process, manufacturing engineers) for major projects with multi-national work environment. Creating electrical schematics and PCB layouts based on requirements received from cross-disciplinary teams Creating and releasing engineering drawings & bill of materials using Engineering Change Management process Interacting with PG counterpart in US Studying and recommending corrective solutions for technical issues of varying complexities. Conducting Design review to get buy-in from all cross functional teams Managing in a very dynamic and fast paced work environment with frequent updates, design packages with quick solutions etc. Mandatory Skills required to perform the job: Core PCB Design Expertise with OrCAD Allegro - designed complex boards 10-12 layers with SMD s, BGA s, through hole parts, placement, routing, setting up constraints, working with component library teams for PCB footprint Performing Schematic Entry in OrCAD Design Entry and circuit understanding with op-amps, comparators, passive devices, sensor circuitry, semiconductors IC s - microcontrollers/FPGA, power supplies (DC-DC Converters) Working alongside EE, ME for planning the board, DFT philosophy, working with PCB vendors for design for manufacturability (DFM), mechanical packaging constraints and PCB stack-up Ability to write test plans for PCB testing and ability to perform low level IO testing on sub-controller and devices, debugging board failures/issues Creation of electrical schematic diagram for cables, knowledge of Zuken Semiconductor domain knowledge would be a value addition Our Commitment We believe it is important for every person to feel valued, included, and empowered to achieve their full potential. By bringing unique individuals and viewpoints together, we achieve extraordinary results. Lam Research ("Lam" or the "Company") is an equal opportunity employer. Lam is committed to and reaffirms support of equal opportunity in employment and non-discrimination in employment policies, practices and procedures on the basis of race, religious creed, color, national origin, ancestry, physical disability, mental disability, medical condition, genetic information, marital status, sex (including pregnancy, childbirth and related medical conditions), gender, gender identity, gender expression, age, sexual orientation, or military and veteran status or any other category protected by applicable federal, state, or local laws. It is the Companys intention to comply with all applicable laws and regulations. Company policy prohibits unlawful discrimination against applicants or employees. Lam offers a variety of work location models based on the needs of each role. Our hybrid roles combine the benefits of on-site collaboration with colleagues and the flexibility to work remotely and fall into two categories - On-site Flex and Virtual Flex. On-site Flex you ll work 3+ days per week on-site at a Lam or customer/supplier location, with the opportunity to work remotely for the balance of the week. Virtual Flex you ll work 1-2 days per week on-site at a Lam or customer/supplier location, and remotely the rest of the time.

The Group You ll Be A Part Of In the Global Products Group, we are dedicated to excellence in the design and engineering of Lams etch and deposition products. We drive innovation to ensure our cutting-edge solutions are helping to solve the biggest challenges in the semiconductor industry. The Impact You ll Make As a Mechanical Engineer at Lam, youre designing and defining cutting-edge mechanical and electro-mechanical systems. Your role involves feasibility studies, testing, and guiding teams in detailed design and fabrication. You provide the crucial design information needed to shape our technologys packaging. In this role, you will directly contribute to ___. What You ll Do Primary Responsibilities: Conceptualizing, Designing, developing and implementing cost-effective design solution for power distribution systems and power boxes Reviewing, validating and selecting OEM components - Circuit Breakers, Interlocks, Mechanical Hardware, Busbars (rigid and flexible), Door Hinges and latches, cable tracks, cooling fans, door gaskets, weldment studs, structural fasteners, conduits, clips, eye bolts etc. Designing sheet metal enclosures and materials for power boxes Reviewing and approving engineering drawings & bill of materials using Engineering Change Management process Leading Interactions with PG counterpart in US Studying and recommending corrective solutions for Problem Reports of varying complexities on power boxes from suppliers and customers. Provide immediate response and timely resolution to design related production issues encountered during the first build process Peer Reviewing Power Box designs, conducting design review to get buy-in from all cross functional teams (primarily Electrical Engineering Team) Developing Processes, Best Practices for Mechanical Engineering for Power Box Designs Focusing on Quality Improvements for ME Power Box Designs (Implementation of DMADV or any such methods) Driving DFMEA, DFR, DFT, DFS, DFM, DFC Driving Continuous Improvement and Innovation Projects Experience with harness routing & documentation for Power Boxes Managing in a very dynamic and fast paced work environment with frequent updates, design packages with quick solutions etc. Who We re Looking For Mandatory Skills required to perform the job: Educational Qualification : B.E/B.Tech or M.E/M.Tech (Mechanical) Years of experience : 12+ years of relevant experience Proficiency in design of Power box / control panels /electro mechanical boxes Proficiency in designing complex sheet metal structures and release of manufacturing drawings Proficiency in Thermal hand calculations and basic simulations (Conduction, Convection, Heat dissipation and increase in temperature) to facilitate selection of heat sinks, Cooling systems like Fans, Component Layouts, Louvers etc. Proficient in 3D Modelling, Assembly and Detailing using Nx or CREO & PLM, PDM Advanced structural calculation s & simulations - consideration of serviceability and facia design (outer panels) - Door, Access Panel, LOTO, Door Hinge design with Interlock, Busbar Strong knowledge of GD&T application Strong knowhow of welding Proficiency on SEMI standards - implementation experience Structured PS&DM experience - PB level issues. Proficient in Designing for cost targets, optimization of design footprints etc. Experience on coatings and finishes Experience with plastic components, elastomers and viewports, associated flammability standards Detailed knowledge of typical Power box issues in the field Exposure to Value Engineering would be an advantage Independently managing with projects/tasks and ability to prepare documents with MS Office Preferred Qualifications Desirable Skill: Detailed knowledge on analysis software s like Nx-Nastran to validate the design Exposure to knowledge on schematics and electrical components (CB, Contactors, SSRs, switching power supply etc. ) and 480V AC/208 V AC electrical components Knowledge in Engineering Change Management Process Exposure to Value Engineering would be an advantage Awareness on EMC & EMI requirements Exposure to Seismic Analysis, Vibration Analysis Functional testing experience

Bachelors or Masters degree in Electrical, Electronics or VLSI Engineering Expertise in DFX Verification preferred Expertise in DFT / ASIC Verification Expertise in System Verilog Expertise in UVM Expertise in python or perl scripting Expertise in verifying JTAG, scan chains, MBIST, LBIST, boundary scan and related test logic for large complex SoCs. Expertise in simulation tools like VCS, Questa, XSIM Excellent knowledge on RTL and DFT concepts Prior experience in Post-silicon validation is an added advantage Prior experience on automotive or AI SoCs is an added advantage Preferred resources with valid regional work permit.

This role is for one of Weekday's clients Min Experience: 8 years JobType: full-time Requirements About the Role: We are looking for a seasoned Logic Design Engineer with expertise in microarchitecture , RISC-V , VLSI , and VHDL , to lead the design and development of the L2 and Last Level Cache (LLC) for high-performance processor systems. This role is critical in delivering industry-leading CPU performance and efficiency by owning the complete lifecycle of cache architecture — from concept to pre-silicon signoff. As a technical leader in the team, you will be responsible for developing the microarchitecture of the cache subsystem, defining the RTL design, and collaborating across cross-functional teams including verification, DFT, physical design, and software/firmware groups to deliver world-class silicon. Key Responsibilities: Architect and design the L2 and LLC blocks for next-generation high-performance RISC-V processor systems. Translate system-level performance requirements — including capacity, latency, bandwidth, and RAS — into efficient, scalable cache architecture and microarchitecture solutions. Drive high-level feature definition and propose architectural enhancements in high-level design discussions. Develop detailed microarchitecture specifications and implement robust RTL designs in VHDL, ensuring performance, area, and power efficiency. Collaborate with the verification team to define verification plans, support testbench development, and debug RTL issues. Interface with DFT and physical design teams to integrate and optimize the cache subsystem for manufacturability and silicon readiness. Engage with firmware and software teams to support system bring-up and low-level programming interface development. Own pre-silicon signoff of the cache subsystem, meeting all functional, timing, and quality goals before tape-out. Continuously analyze performance metrics and identify areas of microarchitecture and logic improvements. Mentor junior engineers, contribute to design reviews, and participate in architecture working groups. Required Skills and Qualifications: 8+ years of experience in logic design and microarchitecture in high-performance CPU or SoC development. Deep expertise in microarchitecture and design of cache systems, memory hierarchies, or complex compute subsystems. Proven experience with RISC-V or RISC-based processor architectures and SoC integration. Proficient in RTL design using VHDL (Verilog/SystemVerilog is a plus). Solid knowledge of VLSI design principles, synthesis, STA, linting, and clock-domain crossing. Strong understanding of SoC design workflows and cache coherency, ECC/parity, and performance optimization techniques. Familiarity with performance modeling, cache hierarchy tradeoffs, and CPU-SoC system design. Excellent communication and collaboration skills to effectively interface with architecture, verification, physical design, and software teams. Preferred Qualifications: Experience with RISC-V core or cache subsystem development in commercial or open-source environments. Familiarity with scripting tools like Python, Perl, or Tcl for design automation and verification. Exposure to tools like Synopsys Design Compiler, VCS, or Cadence Genus and Innovus. Show more Show less

Company: Qualcomm India Private Limited Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: Physical Implementation activities for Sub systems which includes Floor-planning, Place and Route, CTS, Formal verification, Physical Verification (DRC/LVS), PDN, Timing Closure and power optimization. Should have good exposure to PD implementation of PPA critical Cores and making right PPA trade-off decisions. Knowledge in timing convergence of high frequency data-path intensive Cores and advanced STA concepts Knowledge in Block level PnR convergence with Synopsys ICC2/ Cadence Innovus and timing convergence in PTSI/Tempus Good understanding of clocking architecture. Should be able work in close collaboration with design, DFT and PNR teams and resolve issues wrt constraints validation, verification, STA, Physical design, etc. Good knowledge of Tcl/Perl Scripting Strong problem-solving skills and good communication skills. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field. 1-3 yrs years of experience in Physical Design/Implementation Applicants : Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries). Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law. To all Staffing and Recruiting Agencies : Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications. If you would like more information about this role, please contact Qualcomm Careers.

Job Summary: We are looking for a detail-oriented and experienced Electrical Engineer – PCB Design to join our hardware team. You will be responsible for the schematic design, PCB layout, and testing of high-performance and safety-critical electronic circuits. Key Responsibilities: Design and develop schematics and multi-layer PCB layouts. Select and validate electronic components based on electrical, thermal, and mechanical requirements. Collaborate with firmware, mechanical, and system engineers for complete product development. Ensure designs meet relevant safety, EMI/EMC, and thermal compliance standards (e.g., IEC, UL, ISO 15118). Work on high-voltage power electronics, control boards, communication modules, and protection circuits. Perform board bring-up, debugging, and testing using lab equipment (oscilloscopes, multimeters, analyzers). Coordinate with fabrication and assembly vendors to ensure manufacturability and DFM/DFT compliance. Maintain design documentation including schematics, BOMs, Gerber files, and test reports. Support failure analysis and continuous improvement for released products. Required Qualifications: Bachelor's or Master’s degree in Electrical/Electronics Engineering or a related field. 2–5+ years of experience in PCB design for power electronics or embedded hardware. Proficiency with PCB CAD tools such as Altium Designer, Eagle, KiCAD, or OrCAD. Strong knowledge of analog and digital circuit design principles. Hands-on experience with high-voltage power circuits and safety-compliant layouts. Preferred Skills: Familiarity with thermal management and simulation tools. Experience in EMC mitigation and testing techniques. Understanding of firmware-hardware integration for control systems. Job Types: Full-time, Permanent, Freelance Pay: ₹25,000.00 - ₹30,000.00 per month Benefits: Health insurance Schedule: Day shift Work Location: In person

Job Description Summary As Hardware Electronics Engineer you will be part of a highly motivated, dynamic team of engineers working on the delivery and application engineering of existing and new electronic applications, particularly for HVDC converters and the forthcoming “HVDC Grid”. This is a very exciting and dynamic field of power engineering in which GE Vernova's leading contribution has worldwide recognition. This role gives an excellent opportunity to innovate, expand their design skill and personal development within an internationally recognised company in this exciting field. A degree of judgment will be required at this level but can be supplemented by guidance where required. Job Description Roles and Responsibilities Hardware electronics engineering – Analog and digital electronic circuit design as per requirement Engage in the delivery and application engineering of electronic applications for HVDC converters and the HVDC Grid Engage in verification of electronic components like bench testing, etc. Innovate and expand design skills within the field of power engineering May require travel to collaborate with teams, test laboratories, strategic suppliers, and contract customers Required Qualifications Bachelor's degree in Electronics and Communications, Electrical Engineering, Computer Science, or a related field. At least 2 years of practical experience in digital and analog electronic circuit design and development. Proficiency in electronic component selection, analysis, and qualification testing. Experience in component-level design error testing and analysis. Skilled in product verification (bench testing) and validation (integration testing). Knowledge of design for manufacturing (DFM), design for testing (DFT), industrialization, and cost-effective design. Experience in FPGA component selection. Expertise in electronic design for electromagnetic compatibility (EMC). Hands-on experience with electronic bench testing. Understanding of Environmental Health and Safety (EHS) compliance in design and engineering. Familiarity with schematic capture supervision. Proficiency in PCB layout supervision, including adherence to rules and constraints. Desired Skills knowledge of Controllership and ROHS/REACH compliance knowledge of industrial networks like Profibus, Ethernet, Passive Optical Networks (PON) Experience of type testing - EMC, Environmental, Halt. Experience of PCB interactions within power electronics systems Use of processes, systems, methodologies and tools to manage product lifecycle challenges such as obsolescence and component lead time. Experience of maintaining legacy products including updates and improvements to extend product life span. Good Communication, interpersonal and responsive skills Strong team player & supportive – collaborates well with others to solve problems, Additional Information Relocation Assistance Provided: Yes Show more Show less

Job Title: Quality Checker – PEB Industry Location: Indore Experience: Minimum 1 year in quality inspection, preferably in the PEB or structural steel industry Job Description: We are looking for a skilled and detail-oriented Quality Checker to ensure that our PEB (Pre-Engineered Building) components meet the highest quality and safety standards. The ideal candidate should have hands-on experience in various NDT (Non-Destructive Testing) methods and a good understanding of fabrication processes. Key Responsibilities:  Perform quality inspections of raw materials, in-process work, and finished products  Conduct and interpret results from various QC tests  Inspect welding quality and perform visual and dimensional checks  Ensure compliance with quality standards and project specifications  Operate or inspect processes involving SAW (Submerged Arc Welding) machines  Identify and report non-conformities, follow up on corrective actions  Maintain accurate quality documentation and inspection records  Coordinate with production and project teams to resolve quality issues  Support internal and third-party audits Requirements:  Minimum 1 year of experience in Quality Control/Inspection in PEB or fabrication industry  Good knowledge of NDT methods (DP, DFT, MPT, UT, RT)  Understanding of welding processes, symbols, and quality standards  Familiarity with SAW machine operation or inspection  Ability to use inspection tools (Vernier calipers, micrometers, welding gauges, etc.)  Strong documentation and report-writing skills  Attention to detail and problem-solving mindset  Willing to travel to project sites if needed Show more Show less

Wipro Limited (NYSE: WIT, BSE: 507685, NSE: WIPRO) is a leading technology services and consulting company focused on building innovative solutions that address clients most complex digital transformation needs. Leveraging our holistic portfolio of capabilities in consulting, design, engineering, and operations, we help clients realize their boldest ambitions and build future-ready, sustainable businesses. With over 230,000 employees and business partners across 65 countries, we deliver on the promise of helping our customers, colleagues, and communities thrive in an ever-changing world. For additional information, visit us at www.wipro.com. Job Description Role Purpose The purpose of the role is to design, and architect VLSI and Hardware based products and enable delivery teams to provide exceptional client engagement and satisfaction. Do Define product requirements, design and implement VLSI and HARDWARE Devices. Constant upgrade and updates of design tools, frameworks and understand the analysis of toolset chain for development of hardware products. Ability to analyse right components and hardware elements to choose for product engineering or development. Ability to conduct cost-benefit analysis and choose the best fit design. Knowledge on end to end flow of VLSI including design, DFT and Verification and Hardware product development from design, selection of materials, low level system software development and verification. Needs by displaying complete understanding of product vision and business requirements Develop architectural designs for the new and existing products Part Implementation of derived solution Debug and Solve critical problems during implementation Evangelize Architecture to the Project and Customer teams to achieve the final solution. Constant analysis and monitoring of the product solution Continuously improve and simplify the design, optimize cost and performance Understand market- driven business needs and objectives technology trends and requirements to define architecture requirements and strategy Create a product-wide architectural design that ensures systems are scalable, reliable, and compatible with different deployment options Develop theme-based Proof of Concepts (POCs) in order to demonstrate the feasibility of the product idea and realise it as a viable one Analyse, propose and implement the core technology strategy for product development Conduct impact analyses of changes and new requirements on the product development effort Provide solutioning of RFPs received from clients and ensure overall product design assurance as per business needs Collaborate with sales, development, consulting teams to reconcile solutions to architecture Analyse technology environment, enterprise specifics, client requirements to set a product solution design framework/ architecture Provide technical leadership to the design, development and implementation of custom solutions through thoughtful use of modern technology Define and understand current state product features and identify improvements, options & tradeoffs to define target state solutions Clearly articulate, document and sell architectural targets, recommendations and reusable patterns and accordingly propose investment roadmaps Validate the solution/ prototype from technology, cost structure and customer differentiation point of view Identify problem areas and perform root cause analysis of architectural design and solutions and provide relevant solutions to the problem Tracks industry and application trends and relates these to planning current and future IT needs Provides technical and strategic input during the product deployment and deployment Support Delivery team during the product deployment process and resolve complex issues Collaborate with delivery team to develop a product validation and performance testing plan as per the business requirements and specifications. Identifies implementation risks and potential impacts. Maintain product roadmap and provide timely inputs for product upgrades as per the market needs Competency Building and Branding Ensure completion of necessary trainings and certifications Develop Proof of Concepts (POCs), case studies, demos etc. for new growth areas based on market and customer research Develop and present a point of view of Wipro on product design and architect by writing white papers, blogs etc. Attain market referencsability and recognition through highest analyst rankings, client testimonials and partner credits Be the voice of Wipros Thought Leadership by speaking in forums (internal and external) Mentor developers, designers and Junior architects for their further career development and enhancement Contribute to the architecture practice by conducting selection interviews etc Deliver No. Performance Parameter Measure 1. Product design, engineering and implementation CSAT, quality of design/ architecture, FTR, delivery as per cost, quality and timeline, POC review and standards 2. Capability development % trainings and certifications completed, mentor technical teams, Thought leadership content developed (white papers, Wipro PoVs) Mandatory Skills: Analog Layout . Experience: 8-10 Years . Reinvent your world. We are building a modern Wipro. We are an end-to-end digital transformation partner with the boldest ambitions. To realize them, we need people inspired by reinvention. Of yourself, your career, and your skills. We want to see the constant evolution of our business and our industry. It has always been in our DNA - as the world around us changes, so do we. Join a business powered by purpose and a place that empowers you to design your own reinvention. Come to Wipro. Realize your ambitions. Applications from people with disabilities are explicitly welcome.

Company Qualcomm India Private Limited Job Area Engineering Group, Engineering Group > Hardware Engineering General Summary Physical Implementation activities for Sub systems which includes Floor-planning, Place and Route, CTS, Formal verification, Physical Verification (DRC/LVS), PDN, Timing Closure and power optimization. Should have good exposure to PD implementation of PPA critical Cores and making right PPA trade-off decisions. Knowledge in timing convergence of high frequency data-path intensive Cores and advanced STA concepts Well versed with the Block level PnR convergence with Synopsys ICC2/ Cadence Innovus and timing convergence in PTSI/Tempus in latest technology nodes Good understanding of clocking architecture. Should be able work in close collaboration with design, DFT and PNR teams and resolve issues wrt constraints validation, verification, STA, Physical design, etc. Well versed with Tcl/Perl Scripting Strong problem-solving skills and good communication skills. Minimum Qualifications Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field. 3- 6yrs years of experience in Physical Design/Implementation Applicants : Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries). Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law. To all Staffing and Recruiting Agencies : Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications. If you would like more information about this role, please contact Qualcomm Careers. 3076513 Show more Show less

Astera Labs is a global leader in purpose-built connectivity solutions that unlock the full potential of AI and cloud infrastructure. Our Intelligent Connectivity Platform integrates PCIe , CXL , and Ethernet semiconductor-based solutions and the COSMOS software suite of system management and optimization tools to deliver a software-defined architecture that is both scalable and customizable. Inspired by trusted relationships with hyperscalers and the data center ecosystem, we are an innovation leader delivering products that are flexible and interoperable. Discover how we are transforming modern data-driven applications at www.asteralabs.com . As an Astera Labs Principal DFT (Design for Test) Engineer, you will be part of the DFT Design team that develops the next generation of Astera Labs connectivity products that support the world s leading cloud service providers and server and networking OEMs. In this role, you have exposure and be responsible for the full product life cycle, from definition to mass production to end of life of the products. You will be working closely with all engineering teams, physical design and functions like back-end testing, manufacturing, defect, and reliability analysis. This employee must be team oriented with a focus on solving problems in a collaborative manner between multiple engineering teams. Basic qualifications: Minimum of bachelor s degree in computer engineering/ electrical engineering, Masters preferred. Minimum 8+ years of experience in a semiconductor company as a DFT engineer Must be local or willing to relocate Required experience : Chip design, Verilog and System Verilog Verification, UVM methodology ATPG tools Scan insertion tools Gate-level simulations Static timing analysis Scripting (Perl/Tcl) Familiarity with ATE Hands-on expertise with commercial test generation tools for large complex designs Strong fundamental knowledge of DFT techniques include JTAG, ATPG, test pattern translation, yield learning, logic diagnosis, scan compression Experience running test compression software Experience using the Mentor Tessent or synopsys DFT Max and Tetramax tools Preferred experience: Experience with defining and implementing SOC level verification on large designs. Working with 93k Tester Experience with IEEE 1500 Standard or IEEE 1687 standard and MBIST, LBIST Your base salary will be determined based on your location, experience, and the pay of employees in similar positions. We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.

The Opportunity Were looking for the Wavemakers of tomorrow. What youll need: Good understanding of overall design Flow RTL to GDS. Must have 14+ years of experience on signing off the full chip synthesis/STA for tape outs Hands on Experience on Both Block level and Full chip timing Constraints Development and Management for hierarchical designs. Deep Understanding of DFT Constraints. Hand on Synthesis & STA Experience on Lower node Technologies with Synopsys/Cadence Tools. good understanding of overall ASIC Physical Design/DFT, Tools and implication on Timing Convergence Must have in-depth understanding of relevant areas of Library / Memory / Other collaterals and dependencies on STA Must understand Ultra Submicron issues, Variation aware/Aging Aware Design Sign-off Must understand CTS/Other clock Distribution methodologies well. Good knowledge on Timing Budgets. Knowledge on Perl / TCL / Python scripting language Experience on multi voltage designs using CPF/UPF. Good understanding on timing/area/power/complexity tradeoffs on complex interface design Hands on experience on power analysis using PTPX Good understanding of VHDL / Verilog Constructs. Familiarity with IP level verification and strong RTL debugging capabilities is an added bonus A, enthusiastic team player who enjoys working with others Experience troubleshooting issues with users Experience communicating updates and resolutions to customers and other partners complex technical concepts to other design peers in verbal and written form What Youll Do: We are looking for experienced STA engineer to lead the timing convergence of the SoCs.Responsibilities include STA setup, convergence, reviews and sign-off for Multi-Mode and Multi-corner Multi voltage domain designs. Constraint Generation & Maintenance for Block / SOC for complex hierarchical Designs for all the Modes Timing analysis, and timing closure at Full chip level while supporting the PD team on Block/SS level timing convergence. Interaction with Design, DFT, IP&PD teams for Timing Convergence & Resolving Constraint Conflicts. Support Verification team to enable GLS. Guide the CTS strategies and provide feedback to Implementation Team. Manage the timing ECO generation and strategize the implementation methodology. Develop Automation scripts with-in STA tools for Methodology development. You will be reporting to Director - ASIC engineering. We have a flexible work environment to support and help employees thrive in personal and professional capacities" As part of our commitment to the well-being and satisfaction of our employees, we have designed a comprehensive benefits package that includes: Competitive Compensation Package Restricted Stock Units (RSUs) Provisions to pursue advanced education from Premium Institute, eLearning content providers Medical Insurance and a cohort of Wellness Benefits Educational Assistance Advance Loan Assistance Office lunch & Snacks Facility Equal Employment Opportunity Statement Alphawave Semi is an equal opportunity employer, welcoming all applicants regardless of age, gender, race, disability, or other protected characteristics. We value diversity and provide accommodations during the recruitment process.

Company Qualcomm India Private Limited Job Area Engineering Group, Engineering Group > Hardware Engineering General Summary Job Description Be a member of the team that plays a significant role in ensuring the quality of Connectivity SoCs through structured DFT, Automatic Test Pattern Generation (ATPG) and Memory Built-In Self-Test (MBIST) techniques. Primary Responsibilities Will Include, ▪ Interface with design team to ensure DFT design rules and coverages are met. ▪ Generating high quality manufacturing ATPG test patterns for stuck-at (SAF), transition fault (TDF) models through the use of on-chip test compression techniques. ▪ MBIST verification (including repair), test pattern generation through Mentor tool. ▪ ATPG (SAF, TDF) and MBIST verification using unit delay and min/max timing corner simulations. ▪ Work with the Product/Test engineering teams on the delivery of manufacturing test patterns for ATE. ▪ Responsible for supporting post silicon debug effort, issue resolution. ▪ Responsible for Diagnostic Tool generation for ATPG, MBIST and bring-up on ATE. ▪ Developing, enhancing and maintaining scripts as necessary Minimum Qualifications Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field. Minimum Of 2-6 Years’ Experience In ASIC/DFT – simulation and Silicon validation ▪ Detailed knowledge on DFT concepts, pattern simulation, Silicon debug and yield enhancement ▪ In depth knowledge and hands-on experience in ATPG - coverage analysis. ▪ In depth knowledge of Memory verification, repair and failure root-cause analysis. ▪ Experience With Any Of These Tools Is Required ▪ ATPG - TestKompress ▪ MBIST - Mentor ETVerify ▪ Simulation - VCS (preferred), modelsim. ▪ Expertise in scripting languages such as Perl, shell, etc. is an added advantage ▪ Ability to work in an international team, dynamic environment with good communication skills ▪ Ability to learn and adapt to new tools, methodologies. Applicants : Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries). Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law. To all Staffing and Recruiting Agencies : Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications. If you would like more information about this role, please contact Qualcomm Careers. 3076519 Show more Show less