1092 Dft Jobs - Page 10

Job Summary Understand requirement, prepare and execute tests and adhere to all test controls Good experience in integration testing, system testing, API & Regression testing. The senior automated test facilitator will work across several application team(s) to coach team members, embed processes and facilitate change. They will ensure that teams can validate the quality of the product delivered to the stakeholders as per group standards. Experience in Web Based application testing, api automation preferred. Strategy Understand BDD and expert in functional test automation Familiar with non-functional requirements of software development and have a grasp of 12 factor app methodology Have demonstrable programming knowledge in one OOP language, preferably Java Familiar with Performance Testing (e.g. volume testing) is a plus Ability to coach, and guide junior test engineers Full understanding of the SDLC, especially Agile methodologies Familiar with test management process ISTQB or Agile Test Certified Banking domain knowledge is an added advantage Some understanding of Big Data and warehousing technologies such as Hadoop, Kafka, Teradata would be nice to have Previous coaching or consultancy experience Understanding of continuous integration and deployment processes, or have the desire to learn Key Responsibilities Identify and analyse issues in requirements, design specifications, application architecture as well as product documentation. Develop test specifications based on various requirement documents within schedule constraints. Develop test bed and/or test data and verify test environments (based on project requirements). Develop regression packs to ensure that requirements from previous scope are still functioning as before. Perform functional and technical test execution activities (automated testing, where applicable) as per project engagement. Perform non-functional test execution activities (performance testing, where applicable) as per project engagement. Identify and is familiar with negative testing, to be included in the developed test specifications. Constant communication and follow up with various stakeholders during test planning and execution phases. Report and update test status promptly and accurately. Enable project meetings to provide feedback and statistics of the project in relation to the test quality. Conduct reviews and inspections of project deliverables (for small size projects). Able to contribute to multiple projects, whilst still ensuring process compliance and deliverables are adhere to. Able to work independently as well as a team in providing out-of-the box solution if required. To collaborate/troubleshoot with the development and delivery team for technical issues that requires result analysis and feedback. Skills And Experience Processes Good understanding and able to apply test processes laid down within the test team, and/or standards as defined by project and SCB. Ability to work in a highly compliant landscape and work within the boundaries of globally defined software quality management practices and policies Understand that traceability and reporting are extremely important in highly compliant environments and be prepared to engrain these practices in team’s ways of working Regulatory & Business Conduct Display exemplary conduct and live by the Group’s Values and Code of Conduct. Take personal responsibility for embedding the highest standards of ethics, including regulatory and business conduct, across Standard Chartered Bank. This includes understanding and ensuring compliance with, in letter and spirit, all applicable laws, regulations, guidelines and the Group Code of Conduct. Qualifications Minimum 9+ years of experience in Testing which includes both Manual and Automation Automation -Selenium with JAVA Good understanding of BDD framework Experience in Banking Domain ISTQB Certified Skills And Competencies Functional testing Automation Testing (Selenium with Java, Cucumber, Genie) About Standard Chartered We're an international bank, nimble enough to act, big enough for impact. For more than 170 years, we've worked to make a positive difference for our clients, communities, and each other. We question the status quo, love a challenge and enjoy finding new opportunities to grow and do better than before. If you're looking for a career with purpose and you want to work for a bank making a difference, we want to hear from you. You can count on us to celebrate your unique talents and we can't wait to see the talents you can bring us. Our purpose, to drive commerce and prosperity through our unique diversity, together with our brand promise, to be here for good are achieved by how we each live our valued behaviours. When you work with us, you'll see how we value difference and advocate inclusion. Together We Do the right thing and are assertive, challenge one another, and live with integrity, while putting the client at the heart of what we do Never settle, continuously striving to improve and innovate, keeping things simple and learning from doing well, and not so well Are better together, we can be ourselves, be inclusive, see more good in others, and work collectively to build for the long term What We Offer In line with our Fair Pay Charter, we offer a competitive salary and benefits to support your mental, physical, financial and social wellbeing. Core bank funding for retirement savings, medical and life insurance, with flexible and voluntary benefits available in some locations. Time-off including annual leave, parental/maternity (20 weeks), sabbatical (12 months maximum) and volunteering leave (3 days), along with minimum global standards for annual and public holiday, which is combined to 30 days minimum. Flexible working options based around home and office locations, with flexible working patterns. Proactive wellbeing support through Unmind, a market-leading digital wellbeing platform, development courses for resilience and other human skills, global Employee Assistance Programme, sick leave, mental health first-aiders and all sorts of self-help toolkits A continuous learning culture to support your growth, with opportunities to reskill and upskill and access to physical, virtual and digital learning. Being part of an inclusive and values driven organisation, one that embraces and celebrates our unique diversity, across our teams, business functions and geographies - everyone feels respected and can realise their full potential.

Company Description Renesas is one of the top global semiconductor companies in the world. We strive to develop a safer, healthier, greener, and smarter world, and our goal is to make every endpoint intelligent by offering product solutions in the automotive, industrial, infrastructure and IoT markets. Our robust product portfolio includes world leading MCUs, SoCs, Analog and power products, plus Winning Combination solutions that curate these complementary products. We are a key supplier to the world’s leading manufacturers of electronics you rely on every day; you may not see our products, but they are all around you. Renesas employs roughly 21,000 people in more than 30 countries worldwide. As a global team, our employees actively embody the Renesas Culture, our guiding principles based on five key elements: Transparent, Agile, Global, Innovative, and Entrepreneurial. Renesas believes in, and has a commitment to, diversity and inclusion, with initiatives and a leadership team dedicated to its resources and values. At Renesas, we want to build a sustainable future where technology helps make our lives easier. Join us and build your future by being part of what’s next in electronics and the world. Job Description Key Responsibilities Lead physical design activities for SoC or large subsystems, including floorplanning, placement, CTS, routing, and signoff closure. Define and drive physical design strategies to meet aggressive performance, power, and area goals. Collaborate cross-functionally with architecture, RTL design, STA, power, verification, and backend teams to ensure seamless integration and closure. Develop and maintain physical design methodologies, design guidelines, and automation scripts to enhance productivity and quality. Manage congestion, timing, power integrity, and manufacturability challenges during physical implementation. Communicate design status, risks, and mitigation plans effectively to senior management and stakeholders. Qualifications 14+ years of experience in SoC physical design with expertise in physical implementation flows (floorplanning, placement, CTS, routing) at advanced nodes (7nm, 5nm, or below). Proven track record leading complex SoC or subsystem physical design projects, balancing power, performance, and area while managing congestion and timing closure. Strong proficiency with industry-standard EDA tools (Synopsys ICC2, Cadence Innovus, PrimeTime) and scripting skills (Tcl, Python, Perl) for automation and methodology development. Deep understanding of SoC design flows with demonstrated ability to collaborate effectively across timing closure, power integrity, clocking, verification, and backend teams, including experience in developing physical design methodologies. Knowledge of power delivery network (PDN) design and integration. Familiarity with low-power design techniques including power gating and clock gating. Understanding of design for test (DFT) and its influence on physical design. Excellent leadership, communication, and collaboration skills to drive cross-team success. Additional Information Renesas is an embedded semiconductor solution provider driven by its Purpose ‘ To Make Our Lives Easier .’ As the industry’s leading expert in embedded processing with unmatched quality and system-level know-how, we have evolved to provide scalable and comprehensive semiconductor solutions for automotive, industrial, infrastructure, and IoT industries based on the broadest product portfolio, including High Performance Computing, Embedded Processing, Analog & Connectivity, and Power. With a diverse team of over 21,000 professionals in more than 30 countries, we continue to expand our boundaries to offer enhanced user experiences through digitalization and usher into a new era of innovation. We design and develop sustainable, power-efficient solutions today that help people and communities thrive tomorrow, ‘ To Make Our Lives Easier .’ At Renesas, you can: Launch and advance your career in technical and business roles across four Product Groups and various corporate functions. You will have the opportunities to explore our hardware and software capabilities and try new things. Make a real impact by developing innovative products and solutions to meet our global customers' evolving needs and help make people’s lives easier, safe and secure. Maximize your performance and wellbeing in our flexible and inclusive work environment. Our people-first culture and global support system, including the remote work option and Employee Resource Groups, will help you excel from the first day. Are you ready to own your success and make your mark? Join Renesas. Let’s Shape the Future together. Renesas Electronics is an equal opportunity and affirmative action employer, committed to supporting diversity and fostering a work environment free of discrimination on the basis of sex, race, religion, national origin, gender, gender identity, gender expression, age, sexual orientation, military status, veteran status, or any other basis protected by law. For more information, please read our Diversity & Inclusion Statement. I'm interested Renesas is an embedded semiconductor solution provider driven by its Purpose ‘ To Make Our Lives Easier .’ As the industry’s leading expert in embedded processing with unmatched quality and system-level know-how, we have evolved to provide scalable and comprehensive semiconductor solutions for automotive, industrial, infrastructure, and IoT industries based on the broadest product portfolio, including High Performance Computing, Embedded Processing, Analog & Connectivity, and Power. With a diverse team of over 21,000 professionals in more than 30 countries, we continue to expand our boundaries to offer enhanced user experiences through digitalization and usher into a new era of innovation. We design and develop sustainable, power-efficient solutions today that help people and communities thrive tomorrow, ‘ To Make Our Lives Easier .’ At Renesas, you can: Launch and advance your career in technical and business roles across four Product Groups and various corporate functions. You will have the opportunities to explore our hardware and software capabilities and try new things. Make a real impact by developing innovative products and solutions to meet our global customers' evolving needs and help make people’s lives easier, safe and secure. Maximize your performance and wellbeing in our flexible and inclusive work environment. Our people-first culture and global support system, including the remote work option and Employee Resource Groups, will help you excel from the first day. Are you ready to own your success and make your mark? Join Renesas. Let’s Shape the Future together. Renesas Electronics is an equal opportunity and affirmative action employer, committed to supporting diversity and fostering a work environment free of discrimination on the basis of sex, race, religion, national origin, gender, gender identity, gender expression, age, sexual orientation, military status, veteran status, or any other basis protected by law. For more information, please read our Diversity & Inclusion Statement. Renesas is an embedded semiconductor solution provider driven by its Purpose ‘ To Make Our Lives Easier .’ As the industry’s leading expert in embedded processing with unmatched quality and system-level know-how, we have evolved to provide scalable and comprehensive semiconductor solutions for automotive, industrial, infrastructure, and IoT industries based on the broadest product portfolio, including High Performance Computing, Embedded Processing, Analog & Connectivity, and Power. With a diverse team of over 21,000 professionals in more than 30 countries, we continue to expand our boundaries to offer enhanced user experiences through digitalization and usher into a new era of innovation. We design and develop sustainable, power-efficient solutions today that help people and communities thrive tomorrow, ‘ To Make Our Lives Easier .’ At Renesas, you can: Launch and advance your career in technical and business roles across four Product Groups and various corporate functions. You will have the opportunities to explore our hardware and software capabilities and try new things. Make a real impact by developing innovative products and solutions to meet our global customers' evolving needs and help make people’s lives easier, safe and secure. Maximize your performance and wellbeing in our flexible and inclusive work environment. Our people-first culture and global support system, including the remote work option and Employee Resource Groups, will help you excel from the first day. Are you ready to own your success and make your mark? Join Renesas. Let’s Shape the Future together. Renesas Electronics is an equal opportunity and affirmative action employer, committed to supporting diversity and fostering a work environment free of discrimination on the basis of sex, race, religion, national origin, gender, gender identity, gender expression, age, sexual orientation, military status, veteran status, or any other basis protected by law. For more information, please read our Diversity & Inclusion Statement.

Role Purpose The purpose of this role is to perform the development of VLSI system by defining the various functionalities, architecture, layout and implementation for a client Do 1. Conduct verification of the module/ IP functionality and provide customer support a. Understand the architecture of the module or the IP and create verification environment and the development plan as per Universal Verification Methodology b. Create test bench development and test case coding of the one or multiple module c. Write the codes or check the code as required d. Execute the test cases and debug the test cases if required e. Conduct functional coverage analysis and document the test cases including failures and debugging procedures on SharePoint/ JIRA or any other platform as directed f. Test the entire IP functionality under regression testing and complete the documentation to publish to client g. Troubleshoot, debug and upgrade existing systems on time & with minimum latency and maximum efficiency h. Write scripts for the IP i. Comply with project plans and industry standards 2. Ensure reporting & documentation for the client a. Ensure weekly, monthly status reports for the clients as per requirements b. Maintain documents and create a repository of all design changes, recommendations etc c. Maintain time-sheets for the clients d. Providing written knowledge transfer/ history of the project Mandatory Skills: VLSI Design For Testability - DFT.: Experience: 3-5 Years.

Job ID 2025-14539 Date posted Jul. 14, 2025 Location Bengaluru, India Category Verification Job Description: As part of the methodology team, you will be responsible for developing and leading sophisticated power estimation and optimization methodologies at the netlist (gate-level) stage across SoC and IP designs. You will drive correlation strategies, automation flows, and accuracy improvements to ensure power estimates are tightly aligned with final silicon behavior. This role requires deep technical expertise in power analysis tools, a strong understanding of low-power design techniques, and collaboration with multi-functional teams across the design and verification cycle. Responsibilities: Define and drive netlist-level power estimation methodologies using industry-leading tools (e.g., Synopsys PrimeTime PX, Cadence Voltus). Establish and maintain correlation frameworks between RTL and gate-level power, and between estimated and silicon power. Develop automated flows for toggling activity generation, vector-based and vectorless power estimation, and regression reporting. Analyze power consumption trends and identify hotspots; provide recommendations for low-power design optimization. Collaborate with RTL design, physical design, DFT, and architecture teams to ensure early and accurate power signoff. Lead methodology development for corner analysis, dynamic/static power separation, and voltage scaling assessments. Support signoff reviews, audits, and compliance to power specifications and constraints. Provide mentorship and technical leadership within the team and across global sites. Required Skills and Experience : 10+ years of proven experience in power estimation, optimization, and methodology development at the gate-level/netlist stage. Hands-on expertise with tools such as Synopsys PrimeTime PX, Cadence Voltus, and related signoff flows. Strong understanding of digital design principles, low-power architecture techniques, clock gating, and multi-voltage domains. Proficient in scripting (Python, Perl, TCL) to develop scalable and automated power analysis flows. Demonstrated experience in analyzing switching activity data (SAIF/VCD/FSDB) and correlating to real application workloads. Confirmed ability to handle large SoC designs and deliver accurate power metrics under tight schedules. Excellent problem-solving skills, attention to detail, and ability to drive technical discussions and decisions. “Nice To Have” Skills and Experience : Experience with UPF/CPF power intent validation and integration. Exposure to thermal and IR-drop analysis in relation to power consumption. Familiarity with AI/ML-based power modeling or anomaly detection. Previous contributions to methodology deployment in domains such as mobile, automotive, or server-grade SoCs. Participation in EDA tool evaluations, benchmarking, and vendor teamwork. Publications or presentations in technical forums (e.g., SNUG, DVCon, DAC) related to power estimation or optimization. In Return: We are proud to have a set of behaviors that reflects who we are and guides our decisions, defining how we work together to surpass ordinary and shape outstanding! Partner and dedication towards or customers Collaborate and communication Originality and resourcefulness Team and personal development Impact and influence Deliver on your promises Accommodations at Arm At Arm, we want to build extraordinary teams. If you need an adjustment or an accommodation during the recruitment process, please email accommodations@arm.com. To note, by sending us the requested information, you consent to its use by Arm to arrange for appropriate accommodations. All accommodation or adjustment requests will be treated with confidentiality, and information concerning these requests will only be disclosed as necessary to provide the accommodation. Although this is not an exhaustive list, examples of support include breaks between interviews, having documents read aloud, or office accessibility. Please email us about anything we can do to accommodate you during the recruitment process. Equal Opportunities at Arm Arm is an equal opportunity employer, committed to providing an environment of mutual respect where equal opportunities are available to all applicants and colleagues. We are a diverse organization of dedicated and innovative individuals, and don’t discriminate on the basis of race, color, religion, sex, sexual orientation, gender identity, national origin, disability, or status as a protected veteran. Hybrid Working at Arm Arm’s hybrid approach to working is centred around flexibility, where we split our time between the office and other locations to get our work done. Within that framework, we empower groups and teams to determine their own particular hybrid working pattern, depending on the work and the team’s needs. Details of what this means for each role will be shared upon application. In some cases, the flexibility we can offer is limited by local legal, regulatory, tax, or other considerations, and where this is the case, we will collaborate with you to find the best solution. Please talk to us to find out more about what this could look like for you. Accommodations at Arm At Arm, we want to build extraordinary teams. If you need an adjustment or an accommodation during the recruitment process, please email accommodations@arm.com. To note, by sending us the requested information, you consent to its use by Arm to arrange for appropriate accommodations. All accommodation or adjustment requests will be treated with confidentiality, and information concerning these requests will only be disclosed as necessary to provide the accommodation. Although this is not an exhaustive list, examples of support include breaks between interviews, having documents read aloud, or office accessibility. Please email us about anything we can do to accommodate you during the recruitment process. Hybrid Working at Arm Arm’s approach to hybrid working is designed to create a working environment that supports both high performance and personal wellbeing. We believe in bringing people together face to face to enable us to work at pace, whilst recognizing the value of flexibility. Within that framework, we empower groups/teams to determine their own hybrid working patterns, depending on the work and the team’s needs. Details of what this means for each role will be shared upon application. In some cases, the flexibility we can offer is limited by local legal, regulatory, tax, or other considerations, and where this is the case, we will collaborate with you to find the best solution. Please talk to us to find out more about what this could look like for you. Equal Opportunities at Arm Arm is an equal opportunity employer, committed to providing an environment of mutual respect where equal opportunities are available to all applicants and colleagues. We are a diverse organization of dedicated and innovative individuals, and don’t discriminate on the basis of race, color, religion, sex, sexual orientation, gender identity, national origin, disability, or status as a protected veteran.

Roles and Responsibilities 1. Sample Inspection Reports 2. Sampling inspection report 3. Should have hands-on experience in handling Instruments like Vernier, Micrometer, Depth Gauge, Bore Gauge, Surface finish Measurements, Hardness Testing machines, BHN, RC, Vickers, DFT Measurements, etc 4. Should have experience in Inspection of Fabrication Parts, Machining Parts, Rubber Parts, Plastics parts, Gears, and Shafts 5. Should have knowledge in Material Specs Ferrous and Non- Ferrous Desired Candidate 1. Should have 4-5 years of experience working in QC 2. Should have basic knowledge of Tally and Excel Job Type: Full-time Pay: ₹30,000.00 - ₹35,000.00 per month Benefits: Health insurance Leave encashment Provident Fund Schedule: Day shift Work Location: In person

At STEMbotix, we believe in the transformative power of learning through play. Our mission is to make STEM education engaging and accessible for all children, empowering them to become the innovators and problem-solvers of tomorrow. As we continue to develop exciting educational products in robotics, AI, IoT, and more, we’re looking for a passionate PCB Design Engineer to join our dynamic team. Key Responsibilities Design, develop, and optimize Printed Circuit Boards (PCBs) for STEM educational products, including robotics kits, IoT devices, and learning tools. Create schematic diagrams, PCB layouts, and detailed documentation using industry-standard tools (e.g., Altium Designer, Eagle, KiCad, OrCAD). Collaborate closely with embedded systems engineers, mechanical designers, and software developers to integrate hardware seamlessly into our products. Perform component selection and ensure designs meet cost, performance, and manufacturability requirements. Conduct signal integrity, thermal, and EMI/EMC analyses to ensure robust and reliable designs. Support prototyping, testing, debugging, and iteration of PCB designs. Work with manufacturers to create production-ready designs, including generating Gerber files, BOMs, and assembly drawings. Participate in design reviews and contribute to continuous improvement of design standards and processes. Requirements Bachelor’s degree in Electronics Engineering, Electrical Engineering, or related field. 1-3 years of experience in PCB design and development (more experienced candidates also welcome). Proficiency in PCB CAD tools (e.g., Altium Designer, Eagle, KiCad, OrCAD). Solid understanding of electronic components, circuits, and design principles. Knowledge of manufacturing processes and DFM/DFT considerations. Experience working with microcontrollers, sensors, communication interfaces (UART, SPI, I2C), and power supply design is a plus. Ability to read and interpret datasheets and technical documentation. Strong problem-solving skills and attention to detail. Passion for STEM education and a desire to create impactful products for learners. Preferred Skills Experience designing PCBs for robotics, IoT, or educational products. Familiarity with regulatory compliance requirements (e.g., CE, FCC). Experience in prototyping and hands-on soldering/rework. Understanding of mechanical considerations in PCB design (e.g., enclosure constraints). At STEMbotix, you’ll work on innovative products that spark curiosity and transform learning for children worldwide. Join us in shaping the future of STEM education! Apply Today! Job Types: Full-time, Permanent, Fresher Pay: ₹20,000.00 - ₹30,000.00 per month Benefits: Health insurance Paid sick time Education: Bachelor's (Required) Experience: total work: 1 year (Required) Work Location: In person

The purpose of this role is to perform the development of VLSI system by defining the various functionalities, architecture, layout and implementation for a client Do 1. Conduct verification of the module/ IP functionality and provide customer support a. Understand the architecture of the module or the IP and create verification environment and the development plan as per Universal Verification Methodology b. Create test bench development and test case coding of the one or multiple module c. Write the codes or check the code as required d. Execute the test cases and debug the test cases if required e. Conduct functional coverage analysis and document the test cases including failures and debugging procedures on SharePoint/ JIRA or any other platform as directed f. Test the entire IP functionality under regression testing and complete the documentation to publish to client g. Troubleshoot, debug and upgrade existing systems on time & with minimum latency and maximum efficiency h. Write scripts for the IP i. Comply with project plans and industry standards 2. Ensure reporting & documentation for the client a. Ensure weekly, monthly status reports for the clients as per requirements b. Maintain documents and create a repository of all design changes, recommendations etc c. Maintain time-sheets for the clients d. Providing written knowledge transfer/ history of the project Mandatory Skills: VLSI Design For Testability - DFT. Experience: 3-5 Years.

Location: Coimbatore, India | Type: Full‑time (On‑site) About Carbelim ( Linkedin ) Carbelim is a climate‑tech startup pioneering nature‑based carbon capture and utilisation (CCU) solutions powered by advanced microalgae biotechnology. We develop AI‑driven systems that purify polluted air, capture CO₂, and transform emissions into valuable bio‑based products. Incubated by IIT‑Madras and accelerated by IIM‑Lucknow, we unite biotechnology, sustainable engineering, and urban design to build a cleaner, climate‑positive future. Why Join Us  Mission‑driven hardware: build products that directly improve planetary health.  End‑to‑end ownership: take ideas from concept to certified, field‑ready devices.  Small, expert team: collaborate with scientists, designers, and entrepreneurs who value curiosity and initiative. What You'll Do  Own the complete lifecycle of IoT hardware products, from system architecture and component selection through prototyping, testing, certification, and pilot production.  Design electronics: create schematics, multilayer PCBs, and low‑power circuits; run DFM/DFT and bring‑up.  Develop embedded firmware (C/C++ or similar), including drivers, OTA updates, bootloaders, and power‑management features.  Interface sensors and connectivity, wiring up serial buses (I²C, SPI, UART) and wireless stacks (BLE, Wi‑Fi, LoRa, Zigbee, MQTT).  Prototype, test, and certify hardware, ensuring it meets functional, EMI, safety, and regulatory requirements before field deployment.  Collaborate on mechanics: work with industrial designers on enclosures, waterproofing, and ergonomic wearables.  Document & transfer: maintain BOMs, Gerbers, test procedures, and production hand‑off packages.  (Optional) Cloud linkage: hook devices to AWS IoT / Azure IoT Hub / custom back‑ends nice to have, not mandatory. Requirements (Must Haves)  B.E./B‑Tech in ECE, CSE, EE or related branch  3+ years delivering commercial embedded products  Hands‑on with MCUs such as ESP32, STM32, nRF52  Strong analog/digital design & PCB CAD (Altium/KiCad/Eagle)  Wireless protocol know‑how (BLE, Wi‑Fi, LoRa, Zigbee)  Power‑budgeting & battery‑powered design chops  Ability to showcase prior IoT hardware you built (demo units, photos, or repo links  (Nice to have) Cloud dashboards, Grafana, Node‑RED, etc.  (Nice to have) AWS IoT/Azure IoT Core integration Skills  Ownership mindset; able to drive schedules and unblock issues independently  Clear communicator who can document designs and mentor interns/juniors  Passion for sustainability and real‑world impact Compensation *Competitive; commensurate with experience.* How to Apply Apply with a cover letter including your résumé/CV, and links or photos of relevant projects. email us hr@carbelim.io

Hands-on Test Development experience (DFT, EDA tools, etc..) Solid knowledge & experience in defining test solutions for multi-million gate SOC (Scan & MBIST) with Mixed Signal IPs (PLL, High Speed SERDES, DDR) Knowledgeable in full SOC design and manufacturing cycle with specialized/direct experience in multiple areas; RTL/Custom Logic design, Synthesis, P&R, STA, Integration, Verification, Characterization and ATE test Strong understanding of relationships between Hardware, Firmware and Software in FPGA and/or multi-processors SOC. Past experience in leading the team to successful silicon bring-up and problem solving in a complex system Strong planning, project, and people management skills required. Must have experience developing managers and individual contributors Experienced hands-on technical manager not afraid to dig into details to provide technical direction • Proven track record of delivering results and meeting quality, cost, and time-to-market objectives Ability to collaborate with overseas colleagues to define strategy, plan, and execute across the larger, global organization Stakeholder influencing and people skills must be excellent. Needs to be able to set aggressive goals and manage risks effectively Must have a thorough understanding of tool development methodology. Ability to manage software development tasks associated with specifying, developing, scheduling, and debugging according to current and future tool requirements. MS or Ph.D. Engineering degree (EE or equivalent) with 4 to 8 years semiconductor industry experience.

RTL Design Engineers at Hyderabad We need experienced engineers to work on cutting edge technology and with complex functionality. Skills: Overall 3+ years industry experience with 2+ years in RTL Design and SoC Integration. Proven hands-on experience with RTL design for IP, the subsystem for ASIC. Hands-on experience with SoC integration issues like clocking, reset, memory map, hierarchical bus interconnect Knowledge of IP and SoC design flows and methodologies (Lint, CDC, Synthesis, power). Ability to work with local and remote teams (Architecture, DV, DFT, and Physical Design) Proficient in EDA tools used (e.g. Cadence/Mentor/Synopsys) Working knowledge of Unix, Linux and SKILL, Shell/Python Script ability. Quick learner with excellent interpersonal, verbal/written communications, problem solving and decision-making skills Traits: Adaptable, Flexible, Global Approach/Synthesis, creative and capable of working independently as well as a team player. Should have a strong sense of urgency. Solutions orientation; Quality driven; Execution minded

Company Description Renesas is one of the top global semiconductor companies in the world. We strive to develop a safer, healthier, greener, and smarter world, and our goal is to make every endpoint intelligent by offering product solutions in the automotive, industrial, infrastructure and IoT markets. Our robust product portfolio includes world leading MCUs, SoCs, Analog and power products, plus Winning Combination solutions that curate these complementary products. We are a key supplier to the world’s leading manufacturers of electronics you rely on every day; you may not see our products, but they are all around you. Renesas employs roughly 21,000 people in more than 30 countries worldwide. As a global team, our employees actively embody the Renesas Culture, our guiding principles based on five key elements: Transparent, Agile, Global, Innovative, and Entrepreneurial. Renesas believes in, and has a commitment to, diversity and inclusion, with initiatives and a leadership team dedicated to its resources and values. At Renesas, we want to build a sustainable future where technology helps make our lives easier. Join us and build your future by being part of what’s next in electronics and the world. Job Description Key Responsibilities Lead physical design activities for SoC or large subsystems, including floorplanning, placement, CTS, routing, and signoff closure. Define and drive physical design strategies to meet aggressive performance, power, and area goals. Collaborate cross-functionally with architecture, RTL design, STA, power, verification, and backend teams to ensure seamless integration and closure. Develop and maintain physical design methodologies, design guidelines, and automation scripts to enhance productivity and quality. Manage congestion, timing, power integrity, and manufacturability challenges during physical implementation. Communicate design status, risks, and mitigation plans effectively to senior management and stakeholders. Qualifications 14+ years of experience in SoC physical design with expertise in physical implementation flows (floorplanning, placement, CTS, routing) at advanced nodes (7nm, 5nm, or below). Proven track record leading complex SoC or subsystem physical design projects, balancing power, performance, and area while managing congestion and timing closure. Strong proficiency with industry-standard EDA tools (Synopsys ICC2, Cadence Innovus, PrimeTime) and scripting skills (Tcl, Python, Perl) for automation and methodology development. Deep understanding of SoC design flows with demonstrated ability to collaborate effectively across timing closure, power integrity, clocking, verification, and backend teams, including experience in developing physical design methodologies. Knowledge of power delivery network (PDN) design and integration. Familiarity with low-power design techniques including power gating and clock gating. Understanding of design for test (DFT) and its influence on physical design. Excellent leadership, communication, and collaboration skills to drive cross-team success. Additional Information Renesas is an embedded semiconductor solution provider driven by its Purpose ‘ To Make Our Lives Easier .’ As the industry’s leading expert in embedded processing with unmatched quality and system-level know-how, we have evolved to provide scalable and comprehensive semiconductor solutions for automotive, industrial, infrastructure, and IoT industries based on the broadest product portfolio, including High Performance Computing, Embedded Processing, Analog & Connectivity, and Power. With a diverse team of over 21,000 professionals in more than 30 countries, we continue to expand our boundaries to offer enhanced user experiences through digitalization and usher into a new era of innovation. We design and develop sustainable, power-efficient solutions today that help people and communities thrive tomorrow, ‘ To Make Our Lives Easier .’ At Renesas, You Can: Launch and advance your career in technical and business roles across four Product Groups and various corporate functions. You will have the opportunities to explore our hardware and software capabilities and try new things. Make a real impact by developing innovative products and solutions to meet our global customers' evolving needs and help make people’s lives easier, safe and secure. Maximize your performance and wellbeing in our flexible and inclusive work environment. Our people-first culture and global support system, including the remote work option and Employee Resource Groups, will help you excel from the first day. Are you ready to own your success and make your mark? Join Renesas. Let’s Shape the Future together. Renesas Electronics is an equal opportunity and affirmative action employer, committed to supporting diversity and fostering a work environment free of discrimination on the basis of sex, race, religion, national origin, gender, gender identity, gender expression, age, sexual orientation, military status, veteran status, or any other basis protected by law. For more information, please read our Diversity & Inclusion Statement. I'm interested Renesas is an embedded semiconductor solution provider driven by its Purpose ‘ To Make Our Lives Easier .’ As the industry’s leading expert in embedded processing with unmatched quality and system-level know-how, we have evolved to provide scalable and comprehensive semiconductor solutions for automotive, industrial, infrastructure, and IoT industries based on the broadest product portfolio, including High Performance Computing, Embedded Processing, Analog & Connectivity, and Power. With a diverse team of over 21,000 professionals in more than 30 countries, we continue to expand our boundaries to offer enhanced user experiences through digitalization and usher into a new era of innovation. We design and develop sustainable, power-efficient solutions today that help people and communities thrive tomorrow, ‘ To Make Our Lives Easier .’ At Renesas, You Can: Launch and advance your career in technical and business roles across four Product Groups and various corporate functions. You will have the opportunities to explore our hardware and software capabilities and try new things. Make a real impact by developing innovative products and solutions to meet our global customers' evolving needs and help make people’s lives easier, safe and secure. Maximize your performance and wellbeing in our flexible and inclusive work environment. Our people-first culture and global support system, including the remote work option and Employee Resource Groups, will help you excel from the first day. Are you ready to own your success and make your mark? Join Renesas. Let’s Shape the Future together. Renesas Electronics is an equal opportunity and affirmative action employer, committed to supporting diversity and fostering a work environment free of discrimination on the basis of sex, race, religion, national origin, gender, gender identity, gender expression, age, sexual orientation, military status, veteran status, or any other basis protected by law. For more information, please read our Diversity & Inclusion Statement. Renesas is an embedded semiconductor solution provider driven by its Purpose ‘ To Make Our Lives Easier .’ As the industry’s leading expert in embedded processing with unmatched quality and system-level know-how, we have evolved to provide scalable and comprehensive semiconductor solutions for automotive, industrial, infrastructure, and IoT industries based on the broadest product portfolio, including High Performance Computing, Embedded Processing, Analog & Connectivity, and Power. With a diverse team of over 21,000 professionals in more than 30 countries, we continue to expand our boundaries to offer enhanced user experiences through digitalization and usher into a new era of innovation. We design and develop sustainable, power-efficient solutions today that help people and communities thrive tomorrow, ‘ To Make Our Lives Easier .’ At Renesas, You Can: Launch and advance your career in technical and business roles across four Product Groups and various corporate functions. You will have the opportunities to explore our hardware and software capabilities and try new things. Make a real impact by developing innovative products and solutions to meet our global customers' evolving needs and help make people’s lives easier, safe and secure. Maximize your performance and wellbeing in our flexible and inclusive work environment. Our people-first culture and global support system, including the remote work option and Employee Resource Groups, will help you excel from the first day. Are you ready to own your success and make your mark? Join Renesas. Let’s Shape the Future together. Renesas Electronics is an equal opportunity and affirmative action employer, committed to supporting diversity and fostering a work environment free of discrimination on the basis of sex, race, religion, national origin, gender, gender identity, gender expression, age, sexual orientation, military status, veteran status, or any other basis protected by law. For more information, please read our Diversity & Inclusion Statement.

Company: Qualcomm India Private Limited Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: Job Description Qualcomm is a company of inventors that unlocked 5G ushering in an age of rapid acceleration in connectivity and new possibilities that will transform industries, create jobs, and enrich lives. But this is just the beginning. It takes inventive minds with diverse skills, backgrounds, and cultures to transform 5Gs potential into world-changing technologies and products. This is the Invention Age and this is where you come in. You will be joining a successful engineering team whose deliveries can be found in billions of mobile, compute and IoT products worldwide. Based out of Qualcomm's Bangalore office, this role offers a position in Low Power controller IP cores and subsystem digital design targeted for variety of industry leading Snapdragon SoCs for mobile, compute, IoT and Automotive markets. Key Responsibilities Micro-architecture and RTL design for Cores / subsystems. Work in close coordination with Systems, Verification, SoC, SW, PD & DFT teams for design convergence. Enable SW teams to use HW blocks. Qualify designs using static tool checks including Lint, CDC, LEC and CLP. Synthesis, LEC and Netlist CLP Report status and communicate progress against expectations. Preferred Qualifications 5 to 10 years of strong experience in digital front end design (RTL design) for ASICs Expertise in RTL coding in Verilog/SV/VHDL of complex designs with multiple clock domains and multiple power domains Familiar with UPF and power domain crossing Experience in Synthesis, Logical Equivalence checks, RTL and Netlist CLP Familiarity with various bus protocols like AHB, AXI, SPMI, I2C, SPI Experience in low power design methodology and clock domain crossing designs Experience in Spyglass Lint/CDC checks and waiver creation Experience in formal verification with Cadence LEC Understanding of full RTL to GDS flow to interact with DFT and PD teams Expertise in Perl/TCL/Python language Experienced in database management flows with Clearcase/Clearquest. Expertise in post-Si debug is a plus Excellent oral and written communications skills to ensure effective interaction with Engineering Management and team members. Team player, self-motivated, should be able to work with minimal supervision. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. Applicants : Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries). Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law. To all Staffing and Recruiting Agencies : Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications. If you would like more information about this role, please contact Qualcomm Careers.

Create the future of e-health together with us by becoming an Interface Analyst As a pioneer in digital health our heart beats for the development and implementation of new technologies. Become part of a cooperative Agile Team working in the latest technologies Angular and .Net developing PC base, cloud base and mobile base solutions. For the next level of e-health evolution we are looking for creative minds who enjoy working with a variety of technologies, their own design freedom and professional development. Empowering employees to solve challenging problems with full support of your peers. What you can expect from us - An extensive group health and accidental insurance program. A safe digital application and a structured and streamlined onboarding process. Our progressive transportation model allows you to choose: You can either receive a self-transport allowance, or we can pick you up and drop you off on your way from or to the office. Subsidized meal facility. Fun at Work: tons of engagement activities and entertaining games for everyone to participate. Various career growth opportunities as well as a lucrative merit increment policy in a work environment where we promote Diversity, Equity, and Inclusion. Best HR practices along with an open-door policy to ensure a very employee friendly environment. A recession proof and secured workplace for our entire workforce. What you can do for us: You are responsible for building the next physician office experience and help build an amazing application used by healthcare providers and patients across the country If you want to make a difference for physicians, nurses and patients with the code you write, and not just work on the next chat app, this opportunity is for you. Your main duties will include working with vendors and customers to implement important interfaces in the realm of labs (ORM, ORU), PM (ADT, SIU and DFT) and completely custom ones depending on need You and the team will participate in all phases of design and development; from high level design, to defining the REST APIs; to writing the code and tests. The application is built with most of the UI implemented using Angular. There is a messaging layer between the Angular and C# code. The backend is a REST API implemented using ASP.NET Web API. As a member of the team, you will work with all these technologies. Your Qualifications: 2+ years developing software with any OOP language knowledge. For example, C#, Microsoft .NET, or .NET Core. SQL knowledge is a strong plus. Experience designing or working with REST APIs is a strong plus Good knowledge of HL7 standard (ADT, SIU, DFT, ORM, ORU and others) as well as working with an HL7 interface engine - (C#, Mirth, Core point) Flexible to work shift per client requirement. ConvincedSubmit your persuasive application now (including desired salary and earliest possible starting date). We create the future of e-health. Become part of a significant mission.

Job Requirements Engineer must possess 3+ Years of exp at SoC Verification. C/C++ understanding is must. DFT-DV understanding is mandatory.

As an experienced professional with 7-9 years of experience, you will be responsible for executing customer projects independently with minimal supervision in the field of VLSI Frontend Backend or Analog design. Your role will involve guiding team members technically and taking ownership of specific tasks/modules related to RTL Design, Module Verification, PD, DFT, Circuit Design, Analog Layout, STA, Synthesis, Design Checks, and Signoff. You will lead the team to achieve results, complete assigned tasks successfully and on-time, and anticipate, diagnose, and resolve problems as necessary. Your responsibilities will also include ensuring on-time quality delivery approved by the project manager and client, automating design tasks flows, writing scripts to generate reports, and coming up with innovative ideas to reduce design cycle time and cost. Additionally, you will be expected to write papers, file patents, and devise new design approaches. To measure the outcomes of your work, quality will be verified using relevant metrics by UST Manager/Client Manager, timely delivery will be assessed based on relevant metrics, and the reduction in cycle time and cost using innovative approaches will be monitored. The number of papers published, patents filed, and trainings presented to the team will also be considered. Your outputs are expected to demonstrate high quality deliverables with zero bugs in the design/circuit design, clean delivery of the design/module, meeting functional specs/design guidelines without deviation, and thorough documentation of tasks and work performed. Timely delivery, teamwork, innovation, and creativity will be key aspects of your role, along with participation in technical discussions and training forums. Your skills should include proficiency in languages and programming skills such as System Verilog, Verilog, VHDL, UVM, C, C++, Assembly, Perl, TCL/TK, and Makefile. You should have experience with EDA tools like Cadence, Synopsys, and Mentor tool sets, as well as technical knowledge in IP spec architecture design, bus protocols, physical design, circuit design, analog layout, synthesis, DFT, floorplan, clocks, P&R, STA, extraction, physical verification, and more. Strong communication skills, analytical reasoning, problem-solving abilities, attention to detail, and the ability to interact with team members and clients effectively are essential. You should also be well-versed in using available EDA tools, delivering tasks on time per quality guidelines, understanding standard specs and functional documents, and continuously learning new skills as needed. If you have led and executed projects in RTL Design, Verification, DFT, Physical Design, STA, PV, Circuit Design, Analog Layout, and possess a good understanding of design flow and methodologies, this role could be a great fit for you. Additionally, experience in analog circuit design and verifications, knowledge of TSMC FinFet technologies, and familiarity with Cadence Virtuoso circuit design suite would be beneficial. In this role, you will be responsible for circuit design and verification of analog modules like Voltage regulator, LDOs, developing circuit architecture, optimizing designs, guiding layout engineers, problem-solving, and effective communication skills. Desired skills include solid CMOS Analog design fundamentals, hands-on experience with Cadence Virtuoso, technical knowledge of power-performance trade-offs, understanding device parameter variation, and being a good team player in a multi-site work environment. Join us at UST, a global digital transformation solutions provider, where you will work alongside the world's best companies to make a real impact through transformation. With deep domain expertise, innovation, and agility, UST partners with clients to embed innovation and create boundless impact, touching billions of lives in the process.,

Company Qualcomm India Private Limited Job Area Engineering Group, Engineering Group > Hardware Engineering General Summary Job Description Qualcomm is a company of inventors that unlocked 5G ushering in an age of rapid acceleration in connectivity and new possibilities that will transform industries, create jobs, and enrich lives. But this is just the beginning. It takes inventive minds with diverse skills, backgrounds, and cultures to transform 5Gs potential into world-changing technologies and products. This is the Invention Age and this is where you come in. You will be joining a successful engineering team whose deliveries can be found in billions of mobile, compute and IoT products worldwide. Based out of Qualcomm's Bangalore office, this role offers a position in Low Power controller IP cores and subsystem digital design targeted for variety of industry leading Snapdragon SoCs for mobile, compute, IoT and Automotive markets. Key Responsibilities Micro-architecture and RTL design for Cores / subsystems. Work in close coordination with Systems, Verification, SoC, SW, PD & DFT teams for design convergence. Enable SW teams to use HW blocks. Qualify designs using static tool checks including Lint, CDC, LEC and CLP. Synthesis, LEC and Netlist CLP Report status and communicate progress against expectations. Preferred Qualifications 5 to 10 years of strong experience in digital front end design (RTL design) for ASICs Expertise in RTL coding in Verilog/SV/VHDL of complex designs with multiple clock domains and multiple power domains Familiar with UPF and power domain crossing Experience in Synthesis, Logical Equivalence checks, RTL and Netlist CLP Familiarity with various bus protocols like AHB, AXI, SPMI, I2C, SPI Experience in low power design methodology and clock domain crossing designs Experience in Spyglass Lint/CDC checks and waiver creation Experience in formal verification with Cadence LEC Understanding of full RTL to GDS flow to interact with DFT and PD teams Expertise in Perl/TCL/Python language Experienced in database management flows with Clearcase/Clearquest. Expertise in post-Si debug is a plus Excellent oral and written communications skills to ensure effective interaction with Engineering Management and team members. Team player, self-motivated, should be able to work with minimal supervision. Minimum Qualifications Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. Applicants : Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries). Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law. To all Staffing and Recruiting Agencies : Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications. If you would like more information about this role, please contact Qualcomm Careers. 3076998

As an Astera Labs Principal DFT (Design for Test) Engineer, you will be part of the DFT Design team that develops the next generation of Astera Labs connectivity products that support the world s leading cloud service providers and server and networking OEMs. In this role, you have exposure and be responsible for the full product life cycle, from definition to mass production to end of life of the products. You will be working closely with all engineering teams, physical design and functions like back-end testing, manufacturing, defect, and reliability analysis. This employee must be team oriented with a focus on solving problems in a collaborative manner between multiple engineering teams. Basic qualifications: Minimum of bachelor s degree in computer engineering/ electrical engineering, Masters preferred. Minimum 12+ years of experience in a semiconductor company as a DFT engineer Must be local or willing to relocate Required experience : Chip design, Verilog and System Verilog Verification, UVM methodology ATPG tools Scan insertion tools Gate-level simulations Static timing analysis Scripting (Perl/Tcl) Familiarity with ATE Hands-on expertise with commercial test generation tools for large complex designs Strong fundamental knowledge of DFT techniques include JTAG, ATPG, test pattern translation, yield learning, logic diagnosis, scan compression Experience running test compression software Experience using the Mentor Tessent or synopsys DFT Max and Tetramax tools Preferred experience: Experience with defining and implementing SOC level verification on large designs. Working with 93k Tester Experience with IEEE 1500 Standard or IEEE 1687 standard and MBIST, LBIST

We are seeking a Senior Staff Verification Engineer to lead and contribute to the functional verification of complex SoC and IP designs for next-generation AI, HPC, and data center products. The ideal candidate has extensive experience in UVM/SystemVerilog , SoC and IP-level verification, and is passionate about ensuring first-pass silicon success . This role involves defining verification strategies, developing scalable environments, and collaborating cross-functionally with architecture, design, and software teams. Experience with Virtual Modeling, SystemC, and TLM is a plus , enabling advanced verification and early system-level validation. Qualifications Required Qualifications Education & Experience B. S. /M. S. in Electrical Engineering, Computer Engineering, or related field. 8+ years of experience in IP/SoC verification with a proven track record of successful silicon delivery. Technical Expertise Deep knowledge of UVM/SystemVerilog for testbench development and verification IP integration. Strong understanding of SoC architecture and protocols such as DDR5, HBM3, PCIe Gen6, CXL 3. 0 , and other high-speed interfaces. Expertise in coverage-driven verification , constrained-random testing, and assertion-based verification. Proficient in debugging RTL, testbenches, and simulation failures using industry-standard tools. Tools & Languages Hands-on experience with simulation tools (VCS, Xcelium, Questa, etc. ), waveform viewers, coverage tools, and automation scripting (Python, Perl, TCL). Preferred/Additional Skills Virtual Modeling and System-Level Verification Familiarity with SystemC and Transaction-Level Modeling (TLM) for virtual prototyping and early system validation. Experience developing or using virtual platforms for hardware/software co-verification is a strong plus. Emulation & Prototyping Exposure to emulation platforms (Palladium, ZeBu) and FPGA-based prototyping for system-level validation and performance analysis. Software Co-verification Experience working alongside firmware/software teams for pre-silicon software validation and early driver/OS bring-up. Low-Power and DFT Verification Knowledge of power-aware verification (UPF/CPF) and DFT validation methodologies is desirable.

Define and implement DFT architecture and strategy for complex SoCs and ASICs Insert and verify scan chains, MBIST, LBIST, boundary scan (JTAG), and other test structures Develop and maintain ATPG (Automatic Test Pattern Generation) patterns and flows Work closely with RTL designers, verification teams, and physical design teams to ensure DFT requirements are met Debug DFT-related issues during simulation, emulation, and silicon bring-up Perform timing analysis and constraints development for DFT logic Drive silicon validation and yield improvement initiatives related to DFT Document DFT design and verification methodology Bachelor or Master degree in Electronics 48 years of hands-on experience in VLSI DFT Strong expertise in scan insertion, ATPG, MBIST/LBIST, and JTAG implementation Proficiency with DFT tools (Synopsys DFT Compiler, Tetramax, Cadence Modus, Mentor Tessent, etc. ) Good understanding of RTL design, synthesis, and timing closure Experience with silicon bring-up and production test support Excellent problem-solving and debugging skills Strong communication and teamwork abilities Experience in low-power DFT techniques Familiarity with scripting (Perl, Python, Tcl) for automation Work Experience Strong expertise in scan insertion, ATPG, MBIST/LBIST, and JTAG implementation Proficiency with DFT tools (Synopsys DFT Compiler, Tetramax, Cadence Modus, Mentor Tessent, etc. ) Experience in low-power DFT techniques Familiarity with scripting (Perl, Python, Tcl) for automation Good understanding of RTL design, synthesis, and timing closure

Job Requirements 1. Lead High Performance ARM Core Hardening Job Title: Lead Engineer ARM Core Hardening Location: BLR/Hyd Experience: 812 years Technology Node: 5nm/3nm/2nm FinFET/GAA Reports To: Director/Technical Manager SoC Implementation Key Responsibilities: Lead end-to-end RTL-to-GDSII hardening of ARM Cortex-A/X/Neoverse cores (single and multi-cluster). Collaborate with RTL, CAD, DFT, low power, and architecture teams to define floorplan and implementation strategy. Own full flow: floorplanning, power planning (UPF-based), placement, CTS, routing, ECO, timing closure, physical verification, and signoff. Drive design quality metrics: PPA (Performance, Power, Area), DRC/LVS clean, IR drop, EM, and thermal-aware optimization. Architect physical implementation methodology tailored to ARM hardening: hierarchical flow, black-boxing strategy, physical partitioning, clocking architecture. Interface with foundry and EDA vendors for process tech enablement and tool issues. Technical Skills: Deep understanding of ARM core microarchitecture (pipeline, fetch/decode, FPU/NEON, L1/L2 cache). Expert in Synopsys/Cadence tools: ICC2/Fusion Compiler, Tempus/Innovus, Primetime, StarRC, RedHawk/Totem. Advanced clock tree design: CCOpt, custom H-trees, mesh, and multi-source CTS. Experience with UPF-based low power flows and Conformal Low Power (CLP) verification. Familiarity with physical-aware DFT and scan compression (test-mode aware synthesis/placement). Familiar with physical architecture trade-offs (voltage islands, power domains, channel management). Knowledge of EMIR, thermal, aging-aware closure in HPC-class cores. Experience taping out at 5nm or lower is mandatory. --- 2. Engineer ARM Core Hardening Job Title: Physical Design Engineer ARM Core Hardening Location: BLR/Hyd Experience: 38 years Technology Node: 5nm/3nm/2nm FinFET/GAA Key Responsibilities: Implement physical design of ARM core and subsystems from RTL to GDSII. Responsible for floorplanning, placement, CTS, routing, timing and physical closure of core logic. Perform static timing analysis, IR/EM validation, and physical verification. Optimize for frequency, leakage, and area within power and thermal budgets. Support integration of hardened cores into SoC top-level environment. Technical Skills: Good understanding of ARM core architecture and pipeline structure. Experience in Synopsys or Cadence PnR and signoff tools (ICC2, Fusion Compiler, Innovus, PT, RedHawk). Experience in UPF flows, CPF/UPF constraints, and low-power verification tools. Good in timing ECOs, DFT integration, scan reordering and hold fixing in low power designs. Strong debugging skills: congestion, IR drop, setup/hold, crosstalk, antenna, and DRC. Familiar with scripting (TCL, Python, Perl) to automate flows and reports. Work Experience Lead High Performance ARM Core Hardening Experience working with ARM POP (Processor Optimization Pack) or ARM Artisan Physical IP. Worked with multi-core cluster hardening and coherent interconnects (e. g. , CMN-600). Experience with RTL-based performance modeling and correlation with implementation ARM Core Engineer: ARM POP usage experience. Previous tapeout at \u22647nm. Exposure to hierarchical and multi-voltage designs. Familiarity with advanced floorplanning constraints for multi-core clusters.

We are looking for a technical leader to drive the DFT aspects of high-performance compute MCU development. The candidate must be experienced, hands-on and have robust understanding of testability features including SSN, MBIST, LBIST, Scan Insertion, ATPG, GLS and post silicon debug on automotive grade SOCs. Responsibilities Handling hierarchical scan insertion ATPG flow. Integration and Verification of MBIST at RTL level. RTL Integration, Verification, gate level Coverage and GLS enablement for LBIST. Implementation and Verification of IEEE1149. 1 JTAG, IJTAG standards. Post silicon debug activities for DFT patterns. Collaboration with RTL design, Physical design and verification teams will be a daily aspect of the role. Qualifications Degree/PG in Electrical/Electronic Engineering, Computer Engineering or Computer Science. At least 12+ years of experience in related domains and have working knowledge of industry standard digital EDA toolkits. Must be conversant on EDA tools such Tessent, Genus, FC, VCS and Conformal/Formality etc. Strong scripting skills for Automation and Flow development using PERL/TCL/Python. Can do attitude, openness to new environment, people and culture. Strong communication skills (written and verbal), problem solving, attention to detail, commitment to task, and quality focus. Ability to work independently and as part of a team. Mentor and guide junior engineers in DFT.

Post-Silicon ATE Lead to lead and manage post-silicon validation and production testing efforts using ATE platforms. This role requires strong technical expertise in silicon characterization, test development, and working closely with cross-functional teams including design, DFT, packaging, and product engineering. Own and lead post-silicon validation and ATE characterization for silicon devices (SoC/MCU/ASIC). Develop and debug ATE test programs for characterization, qualification, and production ramp-up. Collaborate with design and DFT teams to define test coverage and validation strategy. Analyze silicon test data to identify functional/parametric failures, yield issues, or corner case behaviours. Lead silicon debug and root cause analysis of test failures. Define and drive test cost optimization strategies (e. g. , multisite, parallel test, retest strategy). Work with OSATs and vendors for probe card, loadboard, and socket development. Define test limits, corner conditions, and environmental conditions (HTOL, AC/DC, ESD, etc. ). Support qualification testing (e. g. , HTOL, HAST, Temp Cycle) and drive correlation Qualifications B. E. / B. Tech or M. E. / M. Tech in Electronics, Electrical, or related field. 1 2+ years of experience in post-silicon validation and ATE development. Strong hands-on experience with ATE platforms (e. g. , Teradyne UltraFlex, Advantest 93K, NI STS). Solid understanding of mixed-signal, digital, and analog test methodologies. Experience with scripting (Python, Perl, and C) for automation and data analysis. Familiarity with lab equipment (oscilloscopes, source meters, BERTs, etc. ) for correlation and debug. Excellent problem-solving skills and ability to work across global teams.

Drive Architecture that will define the SOC/MCU architecture and detailed technical specifications from product requirements provided by business and product marketing organizations. Collaborate closely with product and software architects to define and refine SoC-level architecture Play a key role in shaping the microarchitecture of complex IP blocks and SoC subsystems Work closely with functional verification teams on test-plan development and reviews Collaborate with other functional teams including Design, Validation, DFT, physical design and emulation teams to achieve architectural goals and performance targets Provide support to functional validation teams in post silicon debug IP selection and make/buy decisions are a key factor for this role Qualifications Strong communication skills (written and verbal), problem solving, teamwork, attention to detail, commitment to task, and quality focus BTech/MTech in Electrical / Electronic / Computer / Hardware Engineering with experience of 12+ years Can do attitude, openness to new environment, people and culture Experience in Microcontroller and Microprocessor architecture, Interconnect, Cache Coherency Experience with benchmarking IP/SoC performance and tuning IP/SoC architecture Experience in protocols like AHB/AXI/CHI, Memory (ROM, RAM, Flash, LPDDR/DDR3/4) and memory controllers. Strong domain knowledge of clocking, system modes, power management, debug, security and other architectures is a must Any of following experience would be a plus: High Speed Peripherals like DDR, PCIe, Ethernet, GPU, VPU (Video Processing Unit); NIC/FlexNOC interconnect; Flash memory subsystems. Experience in using Virtual Prototype tools (ARM Fast Models, Synopsys Virtualizer, Windriver SIMICS etc. . ) is a plus

Assist in Design for Testability (DFT) activities for VLSI chip designs. Support scan insertion, ATPG pattern generation, and simulation tasks. Work with senior engineers to validate test coverage and resolve issues. Learn and apply industry-standard DFT tools and methodologies. Prepare basic documentation and status reports as required. Bachelor degree in Electronics, Electrical, or related field. Basic understanding of digital design and DFT concepts. Familiarity with Verilog or VHDL is an advantage. Good analytical and communication skills Work Experience Assist in Design for Testability (DFT) activities for VLSI chip designs. Support scan insertion, ATPG pattern generation, and simulation tasks. Work with senior engineers to validate test coverage and resolve issues. Learn and apply industry-standard DFT tools and methodologies.

Senior SoC Director / SoC Director Hyderabad Founded by highly respected Silicon Valley veterans - with its design centers established in Santa Clara, California. / Hyderabad/Bangalore A US based well-funded product-based startup looking for highly talented SoC Director for the following roles Senior Director / SoC Director of SOC is : Trust, loyalty, and ability to command Technical respect with foreign partners after having Taped out Successfully multiple chips to high volume production….this should be easily achieved under his/her belt !!!!!!!! Somebody we can trust to drive on the World stage without embarrassing us Job Description: We are seeking an experienced professional to lead full chip design for multi-million gate SoCs. The ideal candidate will have expertise in digital design and RTL development, with a deep understanding of the design convergence cycle, including architecture, micro-architecture, synthesis, timing closure, and verification. Key Responsibilities: Proficiency in AI Accelerators DNN Accelerators co-processors Interconnect Fabric Cache Coherency D2D C2C SoC Director Bangalore We are a AI semiconductor startup company headquartered in Ann Arbor, Michigan, with branches in , Taiwan and Bangalore, India. We develop highly scalable and innovative AI accelerator chips that offer high performance, low energy, and customer ease of implementation for embedded Edge AI vision-based applications and real-time data processing. Company has working HW & SW for customer sampling, with production designs in the pipeline, and a system architecture designed a future of neuromorphic computing. We are backed by excellent VC funding and is currently in a stage of rapid growth. While our tech is one of a kind we would not be able to make these advancements without our team. Our collaborative culture is one of the keys to our success. Who You Are You are an open and honest communicator who values your team You are innovative, enjoy bringing new ideas to the table and are receptive to ideas and feedback from others You’re passionate about advancing the state of the world through new technology You enjoy the ambiguity and pace of a startup environment The role This leadership role will be responsible for the global VLSI efforts at and India Site Management. It is a highly visible role reporting to Senior Director with ownership of all pre/post Si activities, leading interface with external EDA, IP, Design Service partners, managing the India site operations and a global VLSI team. What you will be doing: Ownership of pre-Si Design of the next-gen AI accelerator at driving deliverables with Design and IP Service providers, CAD tools, IPs, DFT/PD/Packaging and Test. Work closely with internal Architecture, SW, Emulation, and system board designers on product definition, microarchitecture, and design implementation. Build and manage the VLSI team of front-end design and verification engineers across India and Taiwan. Establish best practices for development, testing, reviews, and documentation. Participate in strategic discussions for product features and roadmap. What we expect to see: BS/MS in Electrical/Electronic Engineering with 18+ years of experience in VLSI, SOC design, several Si tape-out/production. Hands-on experience in front-end design, VLSI flows, and working experience for all aspects of Si tape-out, post-Si validation. Self-driven, organized with strong leadership and communication skills. Experience in building and managing teams with the ability to motivate and lead in a startup environment. Proven track record in several successful productizations. What we would be happy to see: Knowledge of AI, specifically Deep Neural Networks Application-specific accelerators or co-processors Startup experience Site Leadership experience Reports to: Site Lead Work location: Bangalore, India Hours: Full time Employment Opportunity and Benefits of Employment: We are committed to creating and fostering a diverse and inclusive workplace environment for all of our employees. We are an equal opportunity employer. Contact: Uday Mulya Technologies Email: muday_bhaskar@yahoo.com Contact: Uday Mulya Technologies muday_bhaskar@yahoo.com "Mining The Knowledge Community"