5 Dft Insertion Jobs

Qualcomm India Private Limited is a leading technology innovator that is dedicated to pushing the boundaries of what is possible. As a Qualcomm Hardware Engineer, you will be involved in planning, designing, optimizing, verifying, and testing electronic systems. These systems encompass a wide range of components such as yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems. Your work will contribute to the development of cutting-edge, world-class products that drive digital transformation and enable next-generation experiences. To qualify for this role, you must hold a Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or a related field, along with at least 3 years of Hardware Engineering or related work experience. Alternatively, a Master's degree with 2+ years of experience or a PhD with 1+ year of experience in the relevant field will also be considered. As a Hardware Engineer at Qualcomm, your responsibilities will include front-end implementation of SERDES high-speed Interface PHY designs, RTL development and validation, collaboration with the functional verification team, development of timing constraints, UPF writing, DFT insertion, ATPG analysis, and support for SoC integration and chip level pre/post-silicon debug. The ideal candidate for this role should possess an MTech/BTech in EE/CS with 4 to 7 years of hardware engineering experience. You should have expertise in micro-architecture development, RTL design, front-end flows (Lint, CDC, low-power checks, etc.), synthesis/DFT/FV/STA, high-speed interface design, and industry-standard protocols like USB/PCIe/MIPI. Experience with post-silicon bring-up and debug is considered a plus, along with the ability to collaborate effectively with global teams and excellent communication skills. Qualcomm is an equal opportunity employer and is committed to providing accessible processes for individuals with disabilities. If you require accommodations during the application/hiring process, you can reach out to disability-accommodations@qualcomm.com or Qualcomm's toll-free number. The company expects its employees to adhere to all applicable policies and procedures, including those related to the protection of confidential information. Please note that Qualcomm's Careers Site is intended for individuals seeking jobs directly at Qualcomm. Staffing and recruiting agencies are not authorized to submit profiles, applications, or resumes through the site. Unsolicited submissions from agencies will not be accepted, and Qualcomm does not entertain any fees related to such submissions. For further information about this role, you can contact Qualcomm Careers for assistance.,

Job description This role is based in Bangalore. But youll also get to visit other locations in India and globe, so need to go where this job takes you. In return, youll get the chance to work with teams impacting entire cities, countries, and the shape of things to come. This is the role: Lead a Team of Engineers working on solving the latest design challenged in Logic Synthesis Can you collaborate with RnD and drive the roadmap for next generation RTL2GDSII solution! An ability to work with design community in solving critical designs problems to achieve desired performance, area and power targets. Deployment of Synthesis solution with various customers working on groundbreaking technologies (7nm and forward). We require to develop & deploy training and technical support to customers using Siemens EDA tools. We dont need superheroes, just superminds! Experience & Qualifications: We are looking out for a candidate with ME/M.Tech in VLSI or Microelectronics with 7+ years of experience in RTL2GDSII, Physical Design with mainstream synthesis and P&R tools. We are looking for someone with hands on experience in Synthesis, DFT insertion, Logical Equivalence and Physical Design. We need hands-on experience with commercial synthesis tools such as Genus, DC, Fusion Compiler which is a must. Tapeout experience of 2 or more projects or proficient experience in implementation CAD flows and methodology. Hands on knowledge on place & route tools like Synopsys-lCC2, Cadence-Innovus or Aprisa and Logical Equivalence tools like Conformal is an advantage. Good understanding of timing, power, and area trade-offs. Knowledge on Static Timing concepts, hands on knowledge on Tempus, Primetime, knowledge on Physical Verification, DRC/LVS, IR drop analysis, hands on mPower etc is a plus. Do you have the ability to pick up new flows, learn on the job and influence QOR Strong verbal and written communication skills; good presentation skills; good problem solving and debugging skills.

Roles and Responsibilities Good Experience in Top/Block, FLAT/Hier DFT insertion flow methodologies Executed scan & MBIST insertion, ATPG and verification at full chip level Experience in timing closure in DFT modes - understanding of shift, capture timing constraints, MBIST constraints and their impacts Generate, review and validate DFT constraints to achieve timing closure of high speed design Experience in timing closure in DFT modes, RTL analysis, logic synthesis, physical design, signoff verification (STA, Formality, Simulations) Exposure to analog and mixed signal IP tests such as PLLs, MIPI etc., methods of their pattern generation and verification Exposure to post-silicon bring-up. Diagnosis and debug methods to arrive at fail points for logic or memory tests Should be able to comprehend architecture and associated limitations with respect to DFT and be able to predict the schedule, amount of task and personnel involved Understanding of Power Estimation/Management for DFT modes is preferred Mentor juniors, support periodic training sessions, work with teams across sites and cross-functional teams and lead by examples Strong written and oral communication skills Experience 5+ Years Qualifications B.Tech/B.E/M.Tech/M.E

Providing expertise for test solutions during design planning, budgeting, and implementation. MBIST implementation and validation, including BIST architecture planning, memory grouping, pattern generation, validation, silicon bring-up, diagnostics analysis, and debug. Participating in customer s design and flow reviews. Driving, prototyping, and developing new Design for Test methodologies. Multitasking across various issues and priorities to help customers exploit new technologies. Collaborating with Solution Architects to develop and productize next-gen test technologies. The Impact You Will Have: Enhancing Synopsys ability to deliver cutting-edge test solutions that meet customer needs. Contributing to the successful integration and silicon bring-up of complex digital ICs. Ensuring high customer satisfaction through effective technical support and problem resolution. Driving innovation in test methodologies and technologies. Supporting the development of next-gen test technologies that push the boundaries of whats possible. Playing a key role in winning new customers and expanding Synopsys market presence. What You ll Need: Minimum BS+10 years of relevant experience/MS+8 years of relevant experience in Electrical Engineering, Computer Engineering, or other relevant fields of study. Experience with RTL coding, DFT insertion, ATPG, MBIST architecture planning, insertion, validation, pattern generation, and silicon bring-up. Excellent knowledge of memory BIST flows, memory fault models, MBIST algorithms, hard/soft repair, and eFuse repair flow. Experience in handling memory BIST for large, complex SoCs with various IPs. Exposure to MBIST of automotive designs is a plus. Good understanding of protocols like 1149.1, 1500, 1687.

This role is based in Bangalore. But youll also get to visit other locations in India and globe, so need to go where this job takes you. In return, youll get the chance to work with teams impacting entire cities, countries, and the shape of things to come. This is the role: Lead a Team of Engineers working on solving the latest design challenged in Logic Synthesis Can you collaborate with RnD and drive the roadmap for next generation RTL2GDSII solution! An ability to work with design community in solving critical designs problems to achieve desired performance, area and power targets. Deployment of Synthesis solution with various customers working on groundbreaking technologies (7nm and forward). We require to develop & deploy training and technical support to customers using Siemens EDA tools. We dont need superheroes, just superminds! Experience & Qualifications: We are looking out for a candidate with ME/M.Tech in VLSI or Microelectronics with 7+ years of experience in RTL2GDSII, Physical Design with mainstream synthesis and P&R tools. We are looking for someone with hands on experience in Synthesis, DFT insertion, Logical Equivalence and Physical Design. We need hands-on experience with commercial synthesis tools such as Genus, DC, Fusion Compiler which is a must. Tapeout experience of 2 or more projects or proficient experience in implementation CAD flows and methodology. Hands on knowledge on place & route tools like Synopsys-lCC2, Cadence-Innovus or Aprisa and Logical Equivalence tools like Conformal is an advantage. Good understanding of timing, power, and area trade-offs. Knowledge on Static Timing concepts, hands on knowledge on Tempus, Primetime, knowledge on Physical Verification, DRC/LVS, IR drop analysis, hands on mPower etc is a plus. Do you have the ability to pick up new flows, learn on the job and influence QOR? Strong verbal and written communication skills; good presentation skills; good problem solving and debugging skills.