10.0 - 14.0 years

0 Lacs

karnataka

On-site

As a Manager, DFT, you will be responsible for implementing the hardware Memory BIST (MBIST) features that support ATE, in-system test, debug, and diagnostics needs of the memories in design. You will work closely with the design, design-verification, and backend teams to enable the integration and validation of the test logic in all phases of the design and backend implementation flow. The job requires you to have good scripting skills and the ability to design and debug with minimal oversight. Additionally, you will be involved in high-quality pattern release to the test team and support silicon bring-up and yield improvement. Key Responsibilities: - Implement hardware Memory BIST (MBIST) ...

Posted 4 weeks ago

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DFT Engineer Proxelera

5.0 - 10.0 years

25 - 40 Lacs

bengaluru

Work from Office

Position: DFT Engineer Location: Bangalore Experience: 5+ Years Email: karthik.adasu@proxelera.com Job Description: We are looking for an experienced DFT Engineer with strong hands-on expertise in ATPG and Scan-based test methodologies. The candidate will be responsible for implementing and validating DFT features to ensure robust test coverage and high-quality silicon delivery. Key Responsibilities: * Perform scan insertion and ensure DFT design compliance. * Execute SCAN DRC checks and perform coverage debug for improved fault coverage. * Generate and validate ATPG patterns for stuck-at and transition faults. * Run gate-level simulations (Zero Delay and Timing Delay) for DFT verification. ...

Posted 1 month ago

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DFT Engineer Proxelera

5.0 - 10.0 years

25 - 40 Lacs

hyderabad, bengaluru

Work from Office

Position: Senior DFT Engineer Location: Bangalore / Hyderabad Experience: 5+ Years Email: karthik.adasu@proxelera.com Job Description: We are seeking an experienced Senior DFT Engineer with strong expertise in DFT design, verification, and test methodologies. Key Responsibilities: * Implement and verify DFT logic including MBIST, scan chains, compression, TAP, iJTAG, and eFuse. * Perform scan insertion, scan compression, ATPG pattern generation, and coverage analysis. * Execute MBIST insertion, simulation, and debug at RTL and gate levels. * Collaborate with silicon and test engineering teams for test plan creation and pattern generation. * Participate in post-silicon bring-up, diagnostics, ...

Posted 1 month ago

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Manager, DFT MediaTek

10.0 - 14.0 years

0 Lacs

karnataka

On-site

The Manager, DFT will be responsible for implementing the hardware Memory BIST (MBIST) features that support ATE, in-system test, debug, and diagnostics needs of the memories in design. You will work closely with the design, design-verification, and backend teams to enable the integration and validation of the test logic in all phases of the design and backend implementation flow. The job requires you to have good scripting skills and the ability to design and debug with minimal oversight. You will also be involved in high-quality pattern release to the test team and support silicon bring-up and yield improvement. The ideal candidate for this role should be an ASIC Design DFT engineer with 1...

Posted 3 months ago

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