Design Verification Lead/Staff Engineer

Job Title: Lead / Staff Engineer ASIC IP & Subsystem Verification

Location

About the Role

highly experienced Design Verification professional (Lead/Staff Engineer)

Key Responsibilities

• Lead

  end-to-end verification

  for IPs, Subsystems, and SoCs – including planning, execution, and coverage closure.
• Architect, enhance, and maintain

  UVM/SystemVerilog/Specman-based testbenches

  .
• Define and execute

  verification plans (VPlans)

  , ensuring 100% functional, assertion, and code coverage.
• Drive

  low-power (PARTL, PAGLS) and GLS verification flows

  to ensure signoff-quality.
• Collaborate with

  design, architecture, STA, PD, and firmware teams

  for bug closure and performance validation.
• Debug RTL/netlist issues and provide

  hands-on technical guidance

  to team members.
• Automate regression, coverage, and debug tasks using

  Python/Perl/Shell scripting

  .
• Contribute to

  methodology enhancements

  and drive adoption across teams.
• Lead and mentor

  small teams (5–8 members)

  , providing ramp-up, task delegation, and review support.
• Interface with

  cross-geo teams

  and contribute to global project execution.

Technical Expertise Required

• Experience

  : 14–26 years in ASIC/SoC/IP Verification with strong subsystem experience.

• Languages/Methodologies

  : SystemVerilog, UVM, Specman “e”, Verilog, VMM.

• Verification Domains

  : IPs (PCIe/CXL, Cache, PHY, Modem, Display, Crypto), Subsystems (DSP, MSS, Memory Controllers), and SoC-level integration.

• Low-Power & GLS

  : Power-aware RTL verification (PARTL), GLS, PAGLS, UPF/CPF flows.

• Protocols/Interfaces

  : AXI, AHB, APB, OCP, PCIe, CXL, DDR, I2C, SPI.

• Tools

  : VCS, NCSim, Specman, Verdi, IUS, vManager, IMC, adcanvas.

• Scripting

  : Python, Perl, Shell, TCL for automation and debug.

• Mixed-Signal/AMS

  : Experience in verification of digital + mixed-signal subsystems (MPHY receiver, display, PHYs).

• Validation

  : Experience in pre-silicon validation environments with SoC bring-up support.

Soft Skills & Leadership

• Proven ability to

  lead 5–8 member teams

  – task delegation, ramp-up, mentoring.
• Strong

  debug, problem-solving, and performance analysis skills

  .
• Track record of

  technical papers/publications

  (SNUG, TI ITC, CDNLive).
• Ability to collaborate effectively with

  multi-site and multicultural teams

  .

Why Join Micron

• Work on

  state-of-the-art memory and SoC verification challenges

  across IP, Subsystem, and SoC.
• Lead

  cross-functional and cross-geo projects

  with ownership of signoff quality.
• Exposure to

  low-power verification, AMS/DMS flows, and validation

  .
• Drive

  methodology improvements and leadership opportunities

  within a global engineering team.

Immediate–30 Day joiners please share your CVs to: