615 Design Verification Jobs - Page 3

In the role of GPU Functional Verification Engineer , your project responsibilities will include the following, Develop deep understanding of 3-D Graphics hardware pipeline, feature sets, data paths, block functionalities & interfaces Strategize, brainstorm, and propose a DV environment, develop test bench, own test plan, debug all RTL artefacts, and achieve all signoff matrices Engage with EDA vendors, explore new and innovative DV methodologies to push the limits of sign off quality Collaborate with worldwide architecture, design, and systems teams to achieve all project goals Currently, we are looking for candidates who can match one or more of the profiles listed below, Strong knowledge of UVM based System Verilog TB Knowledge of GPU pipeline design is a plus, not mandatory Proficiency with formal tools working knowledge of Property based FV is a plus, not mandatory Strong communication skills (both written and verbal) Most importantly, ability to learn, improve and deliver Experience Minimum 3 years of Design verification experience Senior positions will be offered to candidates with suitable years of experience and proven expertise matching the profiles listed above Education Requirements BE/ME/M.Sc. in Electrical, Electronics, VLSI, Microelectronics, or equivalent coursesfrom reputed universities Selected candidates will be part of the GPU HW team which is passionate about developing and delivering the best GPU Cores for all Qualcomm Snapdragon SOC products. Qualcomm GPU is an industry-leading solution which is driving the benchmarks in mobile computing industry and the future of mobile AR/VR. The pre-Si verification team in Bangalore is currently heavily involved in the following UVM/SV based constrained random test bench for functional verification Subsystem level TB for complete GPU workload analysis and compliance Emulation platforms to analyze performance and pipeline bottlenecks Formal tools both for reduced time to bug & property based FV sign-off Power Aware & Gate level simulations to deliver a high-quality GPU implementation Perl/Python scripts for automation in managing regressions, optimize run time, manage database and bug Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. ORMaster's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. ORPhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field.

General Summary: As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. . Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 6+ years of Hardware Engineering or related work experience. ORMaster's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 5+ years of Hardware Engineering or related work experience. ORPhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience. As CPU IntegrationCADengineer, you will enable the floor-planning, physical design (PD), physical design verification (PDV), and signoff of Qualcomms class-leading Oryon CPU cores . You will build and support agile flows and methodologies that enable the first time right development of products with industry-leading power, performance and area. Experience: 6 to 15 years of experience with good academics . Roles andResponsibilities Work closely with worldwide cross-functional teams such as CPU physical design, CPU and SOC Integration, Technology and Central CAD Develop, integrate and release flows and methodologies for floor planning, power planning, pin placement, chip assembly, PDV analysis Develop and maintain unit and system tests to enable correct-by-construction floorplans and physical layouts Architect and recommend methodology improvements to ensure our silicon has the best power, performance and area Maintain and support implementation flows, and resolve project-specific issues Work with EDA vendors to define roadmap and to resolve tool issues Preferred Qualifications: Bachelors/Masters degree in Electrical/Electronics Engineering or Computer Science 10+ years of hands-on experience in development of high-performance chips - either in a design or CAD role High level of programming proficiency ( Python and TCL ). Knowledge of data structures and algorithms Experience with automation Experience with a broad variety of Physical Design tasks - ranging all the way from place-and-route, analysis, timing sign-off and PDV Experience with advanced technology nodes (5nm or lower) Strong user of industry-standard PDV tools such as Siemens/Mentor Calibre Strong user of industry-standard place-and-route tools such as Cadence Innovus Proven track record of managing and regressing place-and-route flows

General Summary: We are hiring talented engineers for CPU RTL development targeted for high performance, low power devices. As a CPU Micro-architecture and RTL Design Engineer, you will work with chip architects to conceive of the micro-architecture, and also help with architecture/product definition through early involvement in the product life-cycle. Roles And Responsibilities Performance exploration. Explore high performance strategies working with the CPU modeling team. Microarchitecture development and specification. From early high-level architectural exploration, through micro architectural research and arriving at a detailed specification. RTL ownership. Development, assessment and refinement of RTL design to target power, performance, area and timing goals. Functional verification support. Help the design verification team execute on the functional verification strategy. Performance verification support. Help verify that the RTL design meets the performance goals. Design delivery. Work with multi-functional engineering team to implement and validate physical design on the aspects of timing, area, reliability, testability and po Preferred Qualifications Thorough knowledge of microprocessor architecture including expertise in one or more of the following areas: instruction fetch and decode, branch prediction, instruction scheduling and register renaming, out-of-order execution, integer and floating point execution, load/store execution, prefetching, cache and memory subsystems Knowledge of Verilog and/or VHDL. Experience with simulators and waveform debugging tools Knowledge of logic design principles along with timing and power implications Understanding of low power microarchitecture techniques Understanding of high performance techniques and trade-offs in a CPU microarchitecture Experience using a scripting language such as Perl or Python Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 6+ years of Hardware Engineering or related work experience. ORMaster's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 5+ years of Hardware Engineering or related work experience. ORPhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience.

As a member of our team, you will be responsible for designing and developing process control instruments, as well as verifying and validating products. Your role will involve working on embedded product development and ensuring compliance with international standards such as EMI/EMC, General Safety, CE Marking, and Flameproof requirements. You will be involved in project planning, scheduling, and execution, as well as coordinating with various departments within the organization. Additionally, you will be responsible for PCB layout development using EAGLE software and creating technical documentation. The ideal candidate for this position should have a BE/BTech/MTech degree in Electronics, Instrumentation, or Embedded Systems, along with 5-10 years of relevant experience in research and development. This is a full-time position with a day shift schedule that requires in-person work at our location. If you are passionate about designing innovative products, ensuring quality and compliance with standards, and collaborating with cross-functional teams, we encourage you to apply for this exciting opportunity.,

Role: Design Verification Experience: 8+Years Location: Bangalore (WFO) Timings: IST 8+ years of design verification experience. MS (or higher) in EE/EC/ECC Engineering As a member of the Design Verification [Pre-Silicon DV] Team for NXP WCS/SCE BU You will be responsible for verification of various IPs and/or SoC. Candidate must be self-motivated and capable of working independently or as part of a team You will implement simulation testbenches, low power simulation setup, assembly/C language diagnostics, assertion checkers or coverage monitors to meet target verification goals. You will also assist with developing test-plans, debugging failures and analyzing coverage information. Must have excellent knowledge of computer architecture and design verification fundamentals Must have experience with Verilog and popular EDA simulation, System Verilog assertions and testbench methodologies Must have experience in developing complex test bench in System Verilog using OVM/UVM methodology Hands-on experience in AMBA protocol, PCIe MAC, USB MAC, Bluetooth MAC, Wifi 802.11 MAC layer protocol Experience in Low Power Simulation/UPF setup, debug low power simulation failures. Exposure to scripting languages like Perl, Unix shell or similar languages Good to have some experience with assembly language programming required Excellent written and oral communication skills necessary Hands-on experience in PCIe MAC, USB MAC, Bluetooth MAC, Wifi 802.11 MAC layer protocol above MAC priority will get changed. Either only MAC PCI or MAC Bluetooth or MAC Wifi

Job Description Responsibilities : - Expertise in Digital Verification - Expertise in Functional Verification - Expertise in SOC / IP Verification - Expertise in working on system Verilog assertions & test benches - Expertise in working on OVM / UVM / VMM based verification flow - Expertise in working on ARM processor - Expertise in working on AMBA bus protocols (AXI, AHB, APB) - Expertise in CXL or PCIe Protocol Verification - Expertise in simulation tools (VCS, ModelSim, Questa) - Expertise in driving Verification Strategy, writing Test Plan, developing Test Bench, Test cases. - Expertise in analysing Code Coverage, Functional Coverage and Assertions. - Expertise in verification of complex SoCs. - Expertise in Test Plan creation and Verification technologies like Code Coverage, Functional coverage, assertion based verification. - Expertise in Verification of complex datapath, DSP based ASICs - Expertise in MAC Protocol: USB, WiFi , Bluetooth , PCIe is mandatory for Pune location - Good knowledge in gate-level simulation, and Scripting languages like Python, TCL - Expert level proficiency (Oral + Written) in Chinese language is mandatory incase Beijing, Taiwan are the preferred work locations - Preferred resources with valid regional work permit. Location - Bangalore/Pune/Beijing,Dallas,Romania,Taiwan

Job Requirements Experience 4-8 yrs in Design Verification. Strong SV UVM Verification exp in real projects. Peripheral I/O, Ethernet ARM SOC-based Experience in Physical design with block level and familiar with ASIC design flow from synthesis to GDSII. Experience in handling High utilized critical blocks and Congestion mitigation Work very closely with Architecture teams to come up with micro-architecture and hardware specification for features Design and RTL ownership Work very closely with Design Verification teams to review test plans and sign off the validation of all design features across products. Work closely with physical design teams to achieve the right power, performance and area metrics for the GPU blocks. WFO mandated.

WHAT YOU DO AT AMD CHANGES EVERYTHING We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world s most important challenges. We strive for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives. AMD together we advance_ Silicon Design Verification Engineer (Multiple Levels) The role: An RTL Design Verification Engineer role in our Security IP (SECIP) development team, where a large number of individual embedded micro-processor (MP) subsystems and associated hardware accelerators vital to improve subsystems performance and functionality are designed and verified. These subsystem IPs provide high performance functions to System on Chip (SoC) products across all AMD business units such as client computers, servers, discrete graphics, and gaming. Our verification engineers will work on block level functional verification and its closure, and/or on subsystem level integration and verification for a variety of embedded MP subsystems. Your expertise will impact security policy management, cryptography, data compression, high throughput DMA, power management, and many other subsystem applications. The person: A talented hardware/firmware co-design/verification engineer with strong records of technical ownership and execution to drive block level IP and/or MP subsystem design and verification assignments to completion. A forward-thinking engineer who tends to optimize/improve the workflow, anticipate/analyze/resolve technical issues, enjoy a competitive pace while empowering and mentoring team members. A strong written and verbal communicator with strong problem solving and attention to detail skills along with professional interpersonal communication capability. Key responsibilities: Develop and maintain block level IP and MP subsystem verification architecture, testbenches, test methodology and infrastructure Develop and debug test plans using SystemVerilog/UVM constrained-random test methodology, C-DPI directed test methodology, formal proof verification methodology, and using object-oriented programming (OOP) techniques to implement/maintain testbenches and tests Triage regressions, debug simulations, analyze coverage, work/resolve technical issues with design, verification and other teams to achieve verification closure Participate in MP subsystem specification, influence IP micro-architecture development (design for verification aspect), design and execute reusable test methodology across individual MP subsystems Debug and solve integration issues with SoC Integration and SoC DV teams Provide technical leadership in verification methodology development and critical problem resolution if as advanced level team members Provide project execution leadership in term of technical assignment ownership, technical mentorship, task planning through divide and conquer, task progress reporting and forecasting if as advanced level team members Preferred experience: BSc with a minimum of equivalent 5 years relevant experience; or MSc with a minimum of equivalent 3 years; or PhD in a directly related research area and a minimum of 1 year A minimum of equivalent 10 years relevant experience if as advanced level team members Proven understanding of MP subsystem and/or common hardware datapath accelerator architectures as well as deep knowledge of applicable state-of-art verification methodology and best practices, if as advanced level team members Proficient in System Verilog, object oriented programming, and scripting (using Ruby, Perl, Python and Makefile) Proven skills in creating UVC and other UVM components. Experience with C-DPI and Formal Verification techniques are valuable assets. Excellent understanding of standard bus/interface protocols (i.e. AXI, AHB, AMBA) Proven experience with ASIC verification tools: simulation, debugging, linting, power aware simulation, etc. Relevant design domain specific knowledge and technical leadership capability required for advanced level candidates Academic credentials: Bachelors Degree or Masters Degree in Electrical Engineering, Computer Engineering, or Computer Science, or possibly a related field Masters Degree preferred. Benefits offered are described: AMD benefits at a glance . AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants needs under the respective laws throughout all stages of the recruitment and selection process.

Responsibilities : - Expertise in Digital Verification - Expertise in Functional Verification - Expertise in SOC / IP Verification - Expertise in working on system Verilog assertions & test benches - Expertise in working on OVM / UVM / VMM based verification flow - Expertise in working on ARM processor - Expertise in working on AMBA bus protocols (AXI, AHB, APB) - Expertise in CXL or PCIe Protocol Verification - Expertise in simulation tools (VCS, ModelSim, Questa) - Expertise in driving Verification Strategy, writing Test Plan, developing Test Bench, Test cases. - Expertise in analysing Code Coverage, Functional Coverage and Assertions. - Expertise in verification of complex SoCs. - Expertise in Test Plan creation and Verification technologies like Code Coverage, Functional coverage, assertion based verification. - Expertise in Verification of complex datapath, DSP based ASICs - Expertise in MAC Protocol: USB, WiFi , Bluetooth , PCIe is mandatory for Pune location - Good knowledge in gate-level simulation, and Scripting languages like Python, TCL - Expert level proficiency (Oral + Written) in Chinese language is mandatory incase Beijing, Taiwan are the preferred work locations - Preferred resources with valid regional work permit. Location - Bangalore/Pune/Beijing,Dallas,Romania,Taiwan

Project description We are passionate about transforming lives through cutting-edge technology, enriching industries, communities, and the world. Our mission is to create exceptional products that drive next-generation computing experiences, serving as the foundation for data centers, artificial intelligence, PCs, gaming, and embedded systems. At the core of our mission lies a culture of innovation. We challenge boundaries to solve some of the world's most critical problems. We are committed to execution excellence, fostering a culture of openness, humility, collaboration, and inclusivity, valuing diverse perspectives along the way. Responsibilities Develop, implement, and maintain verification environments using Verilog/SystemVerilog. Apply UVM methodology to build and enhance testbenches, ensuring thorough coverage of verification scenarios. Perform debugging and root-cause analysis of test failures to ensure design quality. Verify and validate AMBA protocols (AXI, AHB, APB) where applicable. Collaborate on ARM-based SoC verification tasks (preferred, but not mandatory). Leverage strong knowledge of digital design fundamentals to identify design and verification gaps. Create and maintain automation scripts (Perl, Tcl, Make, Shell scripting) to improve verification efficiency. Work closely with design, validation, and architecture teams to ensure timely closure of verification tasks. Skills Must have 8+yrs exp Strong verification skills with hands-on experience in Verilog and SystemVerilog. Proven expertise in UVM methodology, with solid experience in developing testbenches. Good debugging and problem-solving skills. Familiarity with AMBA protocols (AXI, AHB, APB) good to have. Strong foundation in digital design fundamentals. Proficiency in scripting languages (Perl, Tcl, Make, Shell scripting) for automation. Nice to have Exposure to ARM-based SoCs preferred but not mandatory.

6+ years of hands-on DV experience in System Verilog/UVM. Must be able to own and drive the verification of a block / subsystem or a SOC. Extensive experience in IP/sub-system and/or SoC level verification based on SV/UVM

Role & responsibilities Description: Performs semiconductor design engineering assignments including engineering and designing chip layout circuits, circuit checking, documenting specifications, modifying and evaluating semiconductor devices and components. Reviews product requirements and logic diagrams for device definition. Typically responsible for projects, or portions of projects, to design, fabricate, modify, and evaluate semiconductor devices and components. 3-5 years of experience Guide and set the direction for the verification effort within your areas of expertise in any project that the team undertakes. Provide verification support to design projects by simulating, analyzing and debugging pre-silicon full chip designs. Develop Test cases/Stimulus to increase the functional coverage for all DRAM and emerging memory architectures and features. Participate in developing verification methodology and verification environments for advanced DRAM and emerging memory products. Co-work with international colleagues on developing new verification flows to take on the challenges in DRAM and emerging memory design. Experience with Gate Level Simulations and timing debugs. Develop and maintain test benches and test vectors using simulation tools and run regressions for coverage analysis and improvements. Additional Details TSMC Certification:- Added Advantage

Role and Responsibilities Develop and maintain the Design Verification Plan and Report (DVP&R) for body systems. Translate system and component-level requirements into comprehensive test plans. Support DFMEA and DVP&R development and execution. Define test methodologies in alignment with vehicle development programs & milestones. Analyze CAE simulations to identify performance-related issues and propose solutions. Deliver efficient test property usage through re-use strategies. Manage, track, and deliver any required test property updates and retrofits. Drive delivery of testing to project milestones. Coordinate logistics for prototype vehicles, parts, and fixtures for testing. Ensure quality test reports and proper data collection. Communicate all test results to the cross-functional teams. Qualifications and Education Requirements Strong knowledge and familiarity with automotive closures and interior test requirements and standards. Experience with Door KLT, SAG, Overload Durability, Oil Canning, Floor Pan Deflection, Tie Down Strength testing, Life Cycle testing, and a deep understanding of FMVSS regulations (208, 207, 210, 216, 225) is preferred. Preferred Experience and Skills Expertise in automotive closures and interior testing standards.

Role & responsibilities 4+ Years of experience in Design Verification Expertise in SV & UVM Experience in any one of the following protocols like PCIe, Ethernet, DDR, USB, AXI etc., Excellent Communication

Sr. Executive - R&D | QNPD | 4 to 8 years | Peenya Office Roles & Responsibilities Accountable for designing and developing new medical and surgical devices in compliance with engineering and biomechanical standards. Prepare design documents, conduct design reviews and plan test methodologies for design verification. Collaborate with QA, RA and Production teams to ensure regulatory and compliance requirements are met. Perform design risk analysis and implement mitigation plans. Work with the Project Manager to define processes for new product manufacturing. Coordinate with internal and external laboratories for execution of product and safety testing. Act as coordinator for smooth functioning of NPD activities, including trackers management and vendor management. Maintain accurate documentation of NPD activities including design documents, test protocols and reports. Qualifications Graduation in Biomedical Engineering or Mechanical Engineering. 4 8 years of experience in new product design and development, preferably in the medical device industry.

3 years Service Agreement Experience: 0 - 4 years Role & responsibilities: Responsible for development and support of Projects. Responsible for debugging the source codes in Verilog, SV, and UVM. Responsible for Monitoring the trainee's progress. Will be a point of contact for trainees to query on Technical concepts. Preferred candidate profile Freshers Sound Knowledge on Verilog, SV, Digital ,UVM / Back-end design. Physical Design, Analog Good communication skill. Should be good in Digital Electronics. 3 years Service Agreement.

DV Manager with 10+ Years Location : AHMD/BLRE/HYD 10 + years of relevant experience in IP or SOC Verification Must have experience in, developing test bench/test case using System Verilog & UVM Must have experience in functional coverage & assertions development. Experience High Speed Protocol Verification is preferrable Good Leadership and Team Management skills responsible for Delivery Interested professionals can share your updated profile to chakradhar.marupuru@quest-global.com Current CTC : Expected CTC: Notice Period :

This job might be for you if You enjoy solving problems. You love taking on difficult challenges and finding creative solutions. You dont know the answer but will dig until you find it. You communicate clearly. You write well. You are motivated and driven. You volunteer for new challenges without waiting to be asked. You will take ownership of the time you spend with us and make a difference. You can impress our customers with your enthusiasm to solve their issues (and solve them!) Job Overview We are seeking an experienced and highly skilled Senior SOC Design Verification Engineer with a minimum of 5 years of hands-on experience in SOC Design Verification. As a key member of our team, you will play a pivotal role in ensuring the robustness and correctness of our cutting-edge System on Chip designs. Job Description Lead and manage SOC Design Verification efforts for complex projects, ensuring the successful execution of verification plans. Develop and implement comprehensive verification strategies, test plans, and test benches for high-speed SOCs, including low-speed peripherals like I2C/I3C, SPI, UART, GPIO, QSPI, and high-speed protocols like PCIe, Ethernet, CXL, MIPI, DDR and HBM Conduct Gate-level simulations, and power-aware verification using Xprop and UPF.Collaborate closely with cross-functional teams, architects, designers, and pre/post-silicon verification teams. Analyze and implement System Verilog assertions and coverage (code, toggle, functional). Provide mentorship and technical guidance to junior verification engineers.Manage and lead a dynamic team of verification engineers, fostering a collaborative and innovative work environment. Ensure verification signoff criteria are met and documentation is comprehensive.Demonstrate dedication, hard work, and commitment to achieving project goals and deadlines. Adhere to quality standards, implement good test practices, and contribute to the continuous improvement of verification methodologies. Experience with verification tools from Synopsys and Cadence, including VCS and Xsim. Integration of third-party VIPs (Verification IP) from Synopsys and Cadence. Qualifications Bachelors degree in computer science, Electrical/Electronics Engineering, or related field. ORMasters degree in computer science, Electrical/Electronics Engineering, or related field. ORPhD in Computer Science, Electrical/Electronics Engineering, or related field. 5+ years of hands-on experience in SOC Design Verification. Expertise in UVM (Universal Verification Methodology) and System Verilog. Prior experience working on IP level and SOC level verification projects. Proficient in verification tools such as VCS, Xsim, waveform analyzers, and third-party VIP integration (e.g., Synopsys VIPs and Cadence VIPs). Hands-on experience with UFS (Universal Flash Storage), Ethernet, PCIe, CXL, MIPI protocols.Solid understanding of low-speed peripherals (I2C/I3C, SPI, UART, GPIO, QSPI) and high-speed protocols. Experience in DDR, HBM, Gate-level simulations, and power-aware verification using Xprop and UPF. Proficiency in scripting languages such as shell, Makefile, and Perl. Strong understanding of processor-based SOC verification, including native, Verilog, System Verilog, and UVM mixed environment. C-System Verilog handshake and writing C test cases for bootup verification. Excellent problem-solving, analytical, and debugging skills.

Transport is at the core of modern society. Imagine using your expertise to shape sustainable transport and infrastructure solutions for the future. If you seek to make a difference on a global scale, working with next-gen technologies and the sharpest collaborative teams, then we could be a perfect match. Who we are and what we believe in We are committed to shaping the future landscape of efficient, safe, and sustainable transport solutions. Fulfilling our mission creates countless career opportunities for talents across the group s leading brands and entities. Position: Experienced Engineer, Chassis Equipment Key Responsibilities: Takes active role in design and development of storage tanks, installation of components on to chassis, media routing of Urea System and Fuel system. Delivers value through creation of design concepts by balancing of cross functional needs, collaborating with suppliers to co-develop product solutions. Work closely with colleagues in different Volvo Group global sites, cross functional teams to develop the system and its parts. Carryout component packaging, durability verification and physical validation needs. Come up with optimized design solutions while working with FE simulation analysts. Work closely with project managers and cross functional teams to anticipate process steps and propose mitigation plans for identified risks. Engineering documentation of drawings, technical requirement, functional specification and managing change. Product maintenance: Solving quality issues and market support. Education, Skills and Experience: BE/ME Mechanical/Automobile Engineering equivalent with 3 to 6 years of relevant work experience. Hands-on work experience in truck chassis aggregates / equipment installation. Strong in vehicle packaging, media routing and being analytical. Knowledge of design verification and validation is required in automotive context. Good knowledge of application of GD&T. Hands-on experience in Creo and PDM software, exposure to vehicle packaging is required. Additional requirements: Good networking and interpersonal skills with good verbal and written English communication. Process oriented way of working and a team player mindset are success factors in this role. Be able to recognize the value and importance of providing solutions with the right quality level and on time. Applying to this job offers you the opportunity to join Volvo Group . Every day, you will be working with some of the sharpest and most creative brains in our field to be able to leave our society in better shape for the next generation. We are passionate about what we do, and we thrive on teamwork. We are almost 100, 000 people united around the world by a culture of care, inclusiveness, and empowerment. Group Trucks Technology are seeking talents to help design sustainable transportation solutions for the future. As part of our team, you ll help us by engineering exciting next-gen technologies and contribute to projects that determine new, sustainable solutions. Bring your love of developing systems, working collaboratively, and your advanced skills to a place where you can make an impact. Join our design shift that leaves society in good shape for the next generation.

Transport is at the core of modern society. Imagine using your expertise to shape sustainable transport and infrastructure solutions for the future. If you seek to make a difference on a global scale, working with next-gen technologies and the sharpest collaborative teams, then we could be a perfect match. We value your data privacy and therefore do not accept applications via mail. Who we are and what we believe in We are committed to shaping the future landscape of efficient, safe, and sustainable transport solutions. Fulfilling our mission creates countless career opportunities for talents across the group s leading brands and entities. Position: Experienced Engineer, Chassis Equipment Key Responsibilities: Takes active role in design and development of storage tanks, installation of components on to chassis, media routing of Urea System and Fuel system. Delivers value through creation of design concepts by balancing of cross functional needs, collaborating with suppliers to co-develop product solutions. Work closely with colleagues in different Volvo Group global sites, cross functional teams to develop the system and its parts. Carryout component packaging, durability verification and physical validation needs. Come up with optimized design solutions while working with FE simulation analysts. Work closely with project managers and cross functional teams to anticipate process steps and propose mitigation plans for identified risks. Engineering documentation of drawings, technical requirement, functional specification and managing change. Product maintenance: Solving quality issues and market support. Education, Skills and Experience: BE/ME Mechanical/Automobile Engineering equivalent with 3 to 6 years of relevant work experience. Hands-on work experience in truck chassis aggregates / equipment installation. Strong in vehicle packaging, media routing and being analytical. Knowledge of design verification and validation is required in automotive context. Good knowledge of application of GD&T. Hands-on experience in Creo and PDM software, exposure to vehicle packaging is required. Additional requirements: Good networking and interpersonal skills with good verbal and written English communication. Process oriented way of working and a team player mindset are success factors in this role. Be able to recognize the value and importance of providing solutions with the right quality level and on time. Applying to this job offers you the opportunity to join Volvo Group . Every day, you will be working with some of the sharpest and most creative brains in our field to be able to leave our society in better shape for the next generation. We are passionate about what we do, and we thrive on teamwork. We are almost 100,000 people united around the world by a culture of care, inclusiveness, and empowerment. Group Trucks Technology are seeking talents to help design sustainable transportation solutions for the future. As part of our team, you ll help us by engineering exciting next-gen technologies and contribute to projects that determine new, sustainable solutions. Bring your love of developing systems, working collaboratively, and your advanced skills to a place where you can make an impact. Join our design shift that leaves society in good shape for the next generation. Job Category: Technology Engineering Organization: Group Trucks Technology Travel Required: Occasional Travel Requisition ID: 24364 View All Jobs Do we share the same aspirations Every day, Volvo Group products and services ensure that people have food on the table, children arrive safely at school and roads and buildings can be constructed. Looking ahead, we are committed to driving the transition to sustainable and safe transport, mobility and infrastructure solutions toward a net-zero society. Joining Volvo Group, you will work with some of the world s most iconic brands and be part of a global and leading industrial company that is harnessing automated driving, electromobility and connectivity. Our people are passionate about what they do, they aim for high performance and thrive on teamwork and learning. Everyday life at Volvo is defined by a climate of support, care and mutual respect. If you aspire to grow and make an impact, join us on our journey to create a better and more resilient society for the coming generations.

Experienced Engineer-Chassis Equipment Location: Bangalore, IN, 562122 Position Type: Professional Transport is at the core of modern society. Imagine using your expertise to shape sustainable transport and infrastructure solutions for the future. If you seek to make a difference on a global scale, working with next-gen technologies and the sharpest collaborative teams, then we could be a perfect match. We value your data privacy and therefore do not accept applications via mail. Who we are and what we believe in We are committed to shaping the future landscape of efficient, safe, and sustainable transport solutions. Fulfilling our mission creates countless career opportunities for talents across the group s leading brands and entities. Position: Experienced Engineer, Chassis Equipment Key Responsibilities: Takes active role in design and development of storage tanks, installation of components on to chassis, media routing of Urea System and Fuel system. Delivers value through creation of design concepts by balancing of cross functional needs, collaborating with suppliers to co-develop product solutions. Work closely with colleagues in different Volvo Group global sites, cross functional teams to develop the system and its parts. Carryout component packaging, durability verification and physical validation needs. Come up with optimized design solutions while working with FE simulation analysts. Work closely with project managers and cross functional teams to anticipate process steps and propose mitigation plans for identified risks. Engineering documentation of drawings, technical requirement, functional specification and managing change. Product maintenance: Solving quality issues and market support. Education, Skills and Experience: BE/ME Mechanical/Automobile Engineering equivalent with 3 to 6 years of relevant work experience. Hands-on work experience in truck chassis aggregates / equipment installation. Strong in vehicle packaging, media routing and being analytical. Knowledge of design verification and validation is required in automotive context. Good knowledge of application of GD&T. Hands-on experience in Creo and PDM software, exposure to vehicle packaging is required. Additional requirements: Good networking and interpersonal skills with good verbal and written English communication. Process oriented way of working and a team player mindset are success factors in this role. Be able to recognize the value and importance of providing solutions with the right quality level and on time. Group Trucks Technology are seeking talents to help design sustainable transportation solutions for the future. As part of our team, you ll help us by engineering exciting next-gen technologies and contribute to projects that determine new, sustainable solutions. Bring your love of developing systems, working collaboratively, and your advanced skills to a place where you can make an impact. Join our design shift that leaves society in good shape for the next generation. Job Category: Technology Engineering Organization: Group Trucks Technology Travel Required: Occasional Travel Requisition ID: 24364 View All Jobs Do we share the same aspirations

Lead a team of 5-10 resources Understand the design specification , PowerOn Specification Understand boot firmware and reset flow. Develop skills in IBM BIST verification tools and apply them successfully Develop the verification environment and test bench Debug fails using waveform, trace tools and debug RTL code Work with Design team in resolving/debugging logic design issues and responsible for deliveries Required education Bachelor's Degree Preferred education Bachelor's Degree Required technical and professional expertise 8+ years of experience in Design Verification - demonstrated execution experience of verification of logic blocks Strong in SoC verification Chip reset sequence and initialization. ( for SoA) Knowledge of verification (any) methodology, Knowledge of HDLs (Verilog, VHDL) Good programming skills in C/C++, Python/Perl Exposure in developing testbench environment, write complex test scenario, debugging and triaging fails Hardware debug skills backed by relevant experience on projects Exposure in developing testbench environment, write complex test scenarios Good communication skills and be able to work effectively in a global team environment Drive verification coverage closure Preferred technical and professional experience Knowledge of Chip-Initialisation , SCAN , BIST is a plus Scripting Expertise backed up relevant experience in the same Writing Verification test plans Functional and code coverage analysis and debug

Minimum qualifications: Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience. 10 years of experience in ASIC development with Verilog/SystemVerilog, Vhsic Hardware Description Language (VHDL). Experience in micro-architecture and design IPs and Subsystems. Experience in ASIC design verification, synthesis, timing/power analysis, and Design for Testing (DFT). Preferred qualifications: Experience with scripting languages (e.g., Python or Perl). Experience in SoC designs and integration flows. Knowledge of bus architectures, fabrics/NoC, processor design, accelerators, or memory hierarchies.. Knowledge of high performance and low power design techniques. About the job In this role, you'll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive cutting-edge TPU (Tensor Processing Unit) technology that powers Google's most demanding AI/ML applications. You'll be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's TPU. You'll contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML-driven systems. In this role, you will be part of a team developing ASICs used to accelerate and improve traffic efficiency in data centers. You will collaborate with members of architecture, verification, power and performance, physical design, etc. to specify and deliver high quality designs for next generation data center accelerators. You will solve technical problems with innovative micro-architecture and practical logic solutions, and evaluate design options with complexity, performance, power and area in mind.Behind everything our users see online is the architecture built by the Technical Infrastructure team to keep it running. From developing and maintaining our data centers to building the next generation of Google platforms, we make Google's product portfolio possible. We're proud to be our engineers engineers and love voiding warranties by taking things apart so we can rebuild them. We keep our networks up and running, ensuring our users have the best and fastest experience possible. Responsibilities Drive development of Complex IPs and Subsystems along with a team of engineers in the Bengaluru design organization. Own micro-architecture and implementation of IPs and subsystems. Work with Architecture, Firmware and Software teams to drive feature closure and develop micro-architecture specifications. Drive design methodology, libraries, debug, code review in coordination with other IPs Design Verification (DV) teams and physical design teams. Identify and drive Power, Performance and Area improvements for the domains owned.

Role & responsibilities Key Responsibilities: Develop and execute test plans for high-speed protocols such as PCI, PCIe (Gen1 to Gen5), USB (2.0/3.0), Ethernet (10/100/1G/10G), and MAC. Write and maintain SystemVerilog/UVM testbenches for functional verification. Collaborate with design teams to understand architecture and develop verification strategies. Debug RTL issues, analyze simulation failures, and provide comprehensive bug reports. Perform coverage analysis (code and functional) and drive coverage closure. Integrate VIPs (Verification IPs) and ensure compliance with industry standard protocol specifications. Work on assertions, checkers, and monitor development for protocol features. Participate in design and verification reviews, and contribute to continuous improvement. Required Skills: Strong expertise in SystemVerilog, UVM methodologies. Solid understanding of PCIe, USB, Ethernet/MAC protocols . Experience in testbench architecture, test planning, and constrained-random verification . Knowledge of debugging tools like SimVision , Verdi , or similar. Exposure to protocol compliance testing and formal verification is a plus. Experience with scripting languages (Python, Perl, Tcl, Shell) for automation. Preferred candidate profile

As a highly skilled Regulatory Affairs Professional specializing in biosimilar combination products (drug-device combinations), your main responsibility will be to develop and execute global regulatory strategies for combination product devices. You will play a crucial role in ensuring compliance with evolving regulatory requirements from agencies such as the FDA, EMA, MHRA, and other global health authorities. To excel in this role, you should have a minimum of 5 years of regulatory affairs experience in biosimilars, biologics, or combination product development. Your expertise will be instrumental in providing regulatory guidance on device design, human factors, risk management, and manufacturing considerations. You will lead and coordinate regulatory submissions for biosimilar combination products, including IND, BLA, and EU MDR filings. Accuracy in regulatory documentation for design control, risk assessment, usability studies, and post-market surveillance will be critical in this position. Collaboration with R&D, Quality, Clinical, and Manufacturing teams is essential to align regulatory strategies with product development. You will also support design verification and validation activities, including human factors engineering (HFE) and risk management. Your role will involve providing regulatory support for product lifecycle management, including manufacturing changes, labeling updates, and device modifications. By leveraging your expertise in regulatory affairs, you will contribute significantly to the success of regulatory processes for biosimilar combination products.,