Design Verification Engineer

ole Overview

We are seeking a Design Verification Engineer with strong expertise in SystemVerilog, UVM, and AMBA protocols. The role involves developing and maintaining verification environments, debugging regression failures, and achieving coverage closure. Experience in image processing is preferred.

Key Responsibilities

• Develop, enhance, and maintain UVM-based testbenches.
• Create verification test cases and sequences based on design specifications and verification plans.
• Execute regressions, analyse failures, and debug issues in collaboration with design teams.
• Develop and analyse functional coverage and review code coverage to identify verification gaps.
• Drive coverage closure through targeted tests, constrained-random stimulus, and debugging.
• Verify AMBA-based interfaces and protocol behaviour.
• Use Synopsys and Cadence simulation environments for test execution, waveform analysis, and debugging.
• Document verification progress, defects, and closure status.

Required Skills

• Strong knowledge of SystemVerilog and UVM methodology.
• Hands-on experience in testbench development and regression debugging.
• Understanding of AMBA protocols such as AXI, AHB, or APB.
• Experience with functional coverage, code coverage analysis, and coverage closure.
• Familiarity with Synopsys (SNPS) and Cadence (CDNS) simulation infrastructure.
• Strong analytical, problem-solving, and communication skills.

Preferred Skills

• Verification experience in image processing or related IP/subsystems.
• Scripting knowledge for regression automation and result analysis.

Key Deliverables

• Updated and validated UVM testbenches.
• Regression execution and failure analysis reports.
• Coverage reports and closure of identified verification gaps.
• Documented debug findings and verified fixes.

Qualification: B.E./B.Tech or M.E./M.Tech in Electronics, Electrical Engineering, or a related discipline.

Pay: ₹1,500,000.00 - ₹1,800,000.00 per year

Work Location: In person