RTL Synthesis Engineer Allegis Services India

4.0 - 9.0 years

20 - 35 Lacs

hyderabad

Work from Office

Role : RTL Synthesis Engineer (Vivado Backend / RTL Synthesis ,Hyderabad) Work Location (Client): Hyderabad Work Mode or timing : Work From Office / Normal Working hours Qualification : MS or equivalent work experience in Electrical Engineering or similar technology area Experience Level : 4+ years Job Description : An experienced application engineer to focus on FPGA & ACAP Compilation flows, design closure ease-of-use, tools specification, validation, documentation, and key customers support Responsibilities Contribute to triaging reported issues in several Vivado product areas, such as design entry, synthesis, implementation, and help engineering address them effectively. Actively explore innovative methodologies and their impact on flow and design practices, with emphasis on timing closure and compile time, as well as productivity with the new Versal ACAP family. Develop and deliver training materials on new features and methodologies. Stay current with and propose the internal use of industry approaches, algorithms, and practices.

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