Physical Design Engineer, Sr/Lead/Staff Qualcomm

4.0 - 10.0 years

0 Lacs

hyderabad, telangana, india

On-site

Company Qualcomm India Private Limited Job Area Engineering Group, Engineering Group > Hardware Engineering General Summary Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. Pd Jd Thorough knowledge of the ASIC designs Place a...

Posted 1 week ago

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Physical Design Engineer, Sr/Lead/Staff Qualcomm

4.0 - 10.0 years

0 Lacs

hyderabad, telangana

On-site

As an experienced Hardware Engineer at Qualcomm India Private Limited, you will be responsible for the physical design of ASICs, ensuring successful execution from netlist to GDS2. Your expertise in ASIC designs Place and Route flow, low-power methodologies, and PnR tools like Innovus/Fusion compiler will be crucial in this role. Your ability to debug Congestion and CTS issues, as well as familiarity with Sign-off methodology and tools, will be essential for ensuring the quality of the final product. Key Responsibilities: - Thorough knowledge and hands-on experience in ASIC designs Place and Route flow and methodology - Execute complete PD ownership from netlist to GDS2, including HM level P...

Posted 3 weeks ago

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Physical Design Engineer, Sr/Lead/Staff Qualcomm

4.0 - 10.0 years

0 Lacs

hyderabad, telangana

On-site

As a Hardware Engineer at Qualcomm India Private Limited, you will be responsible for the physical design aspects of ASICs, including Place and Route (PnR) flow and methodology. Your key responsibilities will include: - Executing complete PD ownership from netlist to GDS2, encompassing HM level PV, LEC, low-power checks, PDN, and STA closure - Implementing Voltage Islands and low power methodologies, flows, and implementation - Debugging Congestion and Clock Tree Synthesis (CTS) issues - Utilizing PnR tools such as Innovus/Fusion compiler and flow - Familiarity with Sign-off methodologies and tools (PV/PDN/STA/FV/CLP/Scan-DRC(tk)) - Enhancing existing methodologies and flows - Proficiency in...

Posted 3 months ago

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