4.0 - 6.0 years

0 Lacs

noida, uttar pradesh, india

On-site

Responsibilities JOB DESCRIPTION The successful candidate will have experience in leading the development and delivery of integral part of highways and highway drainage projects through various stages of the design process, from feasibility to planning/detailed design and onto construction. Responsibilities You will be working on a range of highways schemes associated with highway drainage elements You will be responsible for producing drainage engineering designs / modelling and construction drawings independently for various UK schemes using the Design Manual for Roads and Bridges and other relevant standards. You will be expected to play a proactive part in the design process and to be ac...

Posted 3 weeks ago

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SOC/ Fullchip STA Engineer 7Rays Semiconductors India Private Limited

4.0 - 8.0 years

0 Lacs

karnataka

On-site

You should have 4 to 8 years of experience in RTL to Netlist Synthesis, specifically in Genus and Design Compiler. Meeting all the DC/Genus exit criteria, including PPA meeting and constraints validation, is a basic requirement. Knowledge of floorplan-based synthesis like DCG is essential. Working closely with RTL designers on constraints debug and feedback on a constant basis is a key aspect of the role. Conducting pre-layout timing analysis and reporting out, as well as post-layout timing analysis for placement, CTS & PRO, are part of the responsibilities. You will be involved in clock gating checks, timing closure, ECOs, and final tapeout timing closure skills across corners and modes. Co...

Posted 3 months ago

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Fullchip STA Engineer 7Rays Semiconductors India Private Limited

4.0 - 8.0 years

0 Lacs

karnataka

On-site

You should have 4 to 8 years of experience in RTL to Netlist Synthesis, specifically in Genus and Design Compiler. Meeting all the DC/Genus exit criteria, including PPA meeting and constraints validation, is a basic requirement. Additionally, you must have floorplan-based synthesis knowledge like DCG, and work closely with RTL designers on constraints debug and feedback on a constant basis. Your responsibilities will include pre-layout timing analysis and reporting, post-layout timing analysis for placement, CTS & PRO, clock gating checks, and timing closure. You should also have experience in ECOs and final tapeout timing closure skills across corners and modes. Collaboration with RTL desig...

Posted 3 months ago

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