3 Cxl) Jobs

What You ll Be Doing: Develop and review the verification test-plan for multi-protocol 112G PHY IP sub-system of Controller/MAC+PCS+PHY. Create and optimize the verification environment based on UVM. Verify the inter-operability of Controller/MAC, PCS, with PHY of different Tech nodes. Execute RTL simulations, Gate Level Simulations, and ensure coverage closure (Functional + Code). Deliver high-quality RTL and Simulation models to customers. Coordinate between RTL, Analog design, and Tech pub teams. Support customers with the integration and bring-up of IP in their simulation environments. Develop and deliver SV verification components for customer integration. Assist customers with silicon bring-up and debug issues when customer silicon is available. The Impact You Will Have: Ensure the delivery of robust and high-quality verification solutions for Synopsys high-performance PHY IPs. Drive innovation and efficiency in verification processes, contributing to the advancement of cutting-edge technologies. Enhance customer satisfaction through exceptional support and high-quality deliverables. Facilitate the seamless integration of Synopsys IPs into customer designs, ensuring successful product launches. Contribute to the development of industry-leading verification methodologies and best practices. Help maintain Synopsys reputation as a leader in chip design and verification solutions. What You ll Need: B.Tech/M.Tech with 7+ years of relevant experience. Proficiency in interface protocols such as Ethernet, PCIe, CXL, JESD, and CPRI. Experience with functional verification flow, Verification tools, and methodologies VMM, OVM/UVM, and System Verilog. Expertise in Gate Level Simulation with SDF, System Verilog Assertions, and coverage implementation. Fundamental knowledge of Analog and Digital mixed signal design. Proficiency in scripting and automation using TCL/Perl/Python. Excellent debug and diagnostic skills.

Creating System verification solutions for Arm AMBA5 protocols such as CHI, AXI5/ACE5 for on-chip, chip-to-chip, die-to-die, coherent, and non-coherent design topologies. Responsible for functional verification involving coherent and non-coherent IP designs. Collaborating with market leaders in High Performance Computing, Data Centre, Mobile/Client, Automotive, and IoT segments to define and develop products that meet complex verification requirements. Architecting and building SystemVerilog UVM-based verification components, testbenches, checkers, scoreboards, and verification IPs. Developing verification plans and driving functional coverage-driven verification closure of real designs. Debugging and resolving issues in verification environments to ensure robust and reliable verification processes. The Impact You Will Have: Enhancing the reliability and performance of high-performance computing and data center systems through rigorous verification processes. Contributing to the advancement of mobile and client devices by ensuring the integrity and functionality of their verification protocols. Driving innovation in the automotive sector by developing robust verification solutions for automotive systems. Supporting the growth of IoT applications by providing reliable and efficient verification for IoT devices. Collaborating with industry leaders to shape the future of system verification and contribute to technological advancements. Ensuring the successful implementation and integration of verification IPs, thereby enhancing the overall quality of our products. What You ll Need: B.E/B.Tech in Electrical Engineering/Electronics & Communications Engineering with 5-8 years of relevant experience, OR M.E/M.Tech in VLSI Design/Microelectronics with 4-8 years of relevant experience. Hands-on experience in architecting and building SystemVerilog UVM-based verification components, testbenches, checkers, scoreboards, and verification IPs. In-depth understanding of cache coherency protocols such as Arm AMBA AXI/ACE, CHI; CCIX or CXL Cache. Experience in creating verification plans and achieving functional coverage-driven verification closure of real designs. Proficiency in writing scripts using Perl, Python, and Shell scripting. Who You Are: Excellent problem-solving, debugging, and analytical skills. Strong programming skills and familiarity with object-oriented programming concepts. Creative and innovative mindset. Excellent verbal and written communication skills. A collaborative team player with a passion for functional verification.

What You ll Be Doing: Develop and review the verification test-plan for multi-protocol 112G PHY IP sub-system of Controller/MAC+PCS+PHY. Create and optimize the verification environment based on UVM. Verify the inter-operability of Controller/MAC, PCS, with PHY of different Tech nodes. Execute RTL simulations, Gate Level Simulations, and ensure coverage closure (Functional + Code). Deliver high-quality RTL and Simulation models to customers. Coordinate between RTL, Analog design, and Tech pub teams. Support customers with the integration and bring-up of IP in their simulation environments. Develop and deliver SV verification components for customer integration. Assist customers with silicon bring-up and debug issues when customer silicon is available. The Impact You Will Have: Ensure the delivery of robust and high-quality verification solutions for Synopsys high-performance PHY IPs. Drive innovation and efficiency in verification processes, contributing to the advancement of cutting-edge technologies. Enhance customer satisfaction through exceptional support and high-quality deliverables. Facilitate the seamless integration of Synopsys IPs into customer designs, ensuring successful product launches. Contribute to the development of industry-leading verification methodologies and best practices. Help maintain Synopsys reputation as a leader in chip design and verification solutions. What You ll Need: B.Tech/M.Tech with 7+ years of relevant experience. Proficiency in interface protocols such as Ethernet, PCIe, CXL, JESD, and CPRI. Experience with functional verification flow, Verification tools, and methodologies VMM, OVM/UVM, and System Verilog. Expertise in Gate Level Simulation with SDF, System Verilog Assertions, and coverage implementation. Fundamental knowledge of Analog and Digital mixed signal design. Proficiency in scripting and automation using TCL/Perl/Python. Excellent debug and diagnostic skills. Who You Are: You are an innovative and detail-oriented professional with a strong technical background and a collaborative mindset. Your excellent communication skills, problem-solving abilities, and interpersonal skills make you a valuable team player. You thrive in a dynamic environment, continually seeking to improve processes and deliver high-quality results. Your passion for technology and dedication to customer success drive you to excel in your role. The Team You ll Be A Part Of: You will join a dynamic and collaborative team focused on the verification of high-performance multi-protocol PHY IPs. Our team is dedicated to delivering innovative solutions and exceptional support to our customers, ensuring the successful integration and deployment of Synopsys IPs. Together, we drive technological advancements and set industry standards in chip design and verification. Rewards and Benefits: We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.