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STA / SignOff Timing Closure BLR LABS

3.0 - 7.0 years

0 Lacs

bangalore, karnataka

On-site

As an experienced ASIC/SoC designer with 3-5 years of experience, you will be responsible for the following key responsibilities: - Definition and development of signoff methodology and corresponding implementation solution. - Flow for STA, Crosstalk Delay and Crosstalk Noise analysis for digital ASIC/SoCs. - Full chip timing constraints development, full chip / Sub-System STA and Signoff for a complex, multi-clock, multi-voltage SoC. - Streamlining the timing signoff criterions, timing analysis methodologies and flows. - Analyze and incorporate advance timing signoff flows (AOCV, POCV Based STA, IR Drop aware STA) into SoC timing signoff flow. - Collaborate with Systems and Architecture, So...

Posted 6 days ago

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