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Physical Design - Director Qualcomm

6.0 - 20.0 years

0 Lacs

chennai, tamil nadu

On-site

As a Hardware Engineer at Qualcomm India Private Limited, you will be responsible for independent planning and execution of Netlist-to-GDSII. Your role will involve a good understanding of basics of static timing analysis and well-versed with Block level and SOC level timing closure (STA) methodologies, ECO generation, and predictable convergence. You will collaborate closely with design, DFT, and PNR teams to resolve issues related to constraints validation, verification, STA, Physical design, and more. Your exposure to high frequency multi-voltage design convergence and good understanding of clock networks will be essential for this role. Additionally, your circuit level comprehension of t...

Posted 6 days ago

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