Director - ASIC Design Verification Eximietas Design

15.0 - 19.0 years

0 Lacs

karnataka

On-site

We are looking for a highly experienced and visionary leader to spearhead our ASIC Design Verification efforts. As the Director of ASIC Design Verification, you will have the opportunity to leverage your 15+ years of extensive technical and leadership experience in ASIC/SoC verification. Your primary responsibilities will include defining the verification strategy, leading cross-functional teams, and ensuring the successful delivery of cutting-edge silicon products with a focus on achieving first-pass success. To excel in this role, you should hold a degree in Electrical/Computer Engineering or a related field, such as Bachelors, Masters, or PhD. Additionally, you should possess a minimum of 15 years of hands-on experience in ASIC/SoC Design Verification, with at least 5 years in technical leadership positions. Your expertise should encompass in-depth knowledge of SystemVerilog, UVM, and coverage-driven verification methodologies. Successful candidates will demonstrate a proven track record of delivering complex ASICs/SoCs from specification to tape out, with a strong emphasis on achieving first-silicon success. Proficiency in low-power verification techniques, including UPF and power-aware testbench design, will be essential for this role. Moreover, you should be adept at debugging, waveform analysis, and advanced scripting for automation purposes. Excellent communication skills, coupled with strong problem-solving abilities and a knack for team-building, are crucial attributes we are seeking in our ideal candidate. Your background should showcase a history of leading global teams and effectively collaborating across different geographies and functional areas. If you are ready to take on this exciting opportunity and have what it takes to drive our ASIC Design Verification efforts to new heights, we encourage you to discuss, apply, or refer suitable candidates to nikhila.shankarabhotla@eximietas.design. Join us in shaping the future of ASIC verification!,

Posted 2 weeks ago

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ASIC Verification Engineer Eviden

3.0 - 7.0 years

0 Lacs

karnataka

On-site

Eviden, part of the Atos Group, with an annual revenue of circa 5 billion is a global leader in data-driven, trusted, and sustainable digital transformation. As a next-generation digital business with worldwide leading positions in digital, cloud, data, advanced computing, and security, it brings deep expertise for all industries in more than 47 countries. By uniting unique high-end technologies across the full digital continuum with 47,000 world-class talents, Eviden expands the possibilities of data and technology, now and for generations to come. Role: ASIC Verification Engineer Location: Bangalore (Whitefield) Experience: 3+ years Education: Bachelor's Degree (BE / BTech) or Master's Degree (ME / MTech) Verification Engineer integrating ASIC functional verification team. ASIC developed includes network controller, router, and cache coherence controller targeting Bull high-end servers and Bull high-performance ("big data" and "exascale" servers). Using Constraint-Random, Coverage Driven functional verification methodologies underlying UVM verification framework to ensure full and effective verification of complex ASIC. Main Responsibilities Acquire knowledge microarchitecture an ASIC unit by studying the specification and interacting with the logical design team. Write and perform the test plan in close cooperation with the logical design team. Develop coverage models and verification environments using UVM-SystemVerilog / C++. Write, maintain, and publish the verification specification. Monitor, analyze, and debug simulation errors. Monitor and analyze simulation coverage results to improve tests accordingly thereby achieving coverage targets on time. Produce a maintainable and reusable code across projects. Skills And Capacities Curious, demanding, and rigorous. Mastering object-oriented programming. Knowledge of UVM verification methodology (or equivalent) and SystemVerilog / SystemC hardware verification languages. Knowledge of Constraint-Random / Coverage-Driven verification environments development in SystemVerilog / C ++ (drivers / monitors, constraint random tests, checkers, and self-checking models and coverage models written in SystemVerilog-Covergroup / SVA). Knowledge of simulation tools and coverage database visualization tools. Effective in problems solving by rapidly identifying their root cause and developing patches or workarounds under tight timing constraints. #Eviden Let's grow together.,

Posted 1 month ago

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