4 Coverage-Driven Verification Jobs

What You ll Be Doing: Making architectural decisions on test bench design. Writing verification plans and specifications. Implementing test bench infrastructure and writing test cases. Implementing a coverage-driven methodology. Leading technical aspects of verification projects. Collaborating with international teams of architects, designers, and verification engineers. The Impact You Will Have: Enhancing the robustness and reliability of IP cores used in critical applications. Driving innovation in verification methodologies and tools. Ensuring high-quality deliverables through rigorous verification processes. Improving productivity, performance, and throughput of verification solutions. Contributing to the success of Synopsys customers in industries such as AI, automotive, and server farms. Mentoring and guiding junior engineers in the verification domain. What You ll Need: Knowledge of protocols such as DDR, PCIe, AMBA (AXI, CHI), SD/eMMC, Ethernet, USB, MIPI. Hands-on experience with UVM/VMM/OVM, test planning, and coverage closure. Proficiency in SystemVerilog and UVM, object-oriented coding, and verification. Experience with scripting languages like C/C++, TCL, Perl, Python. Experience with functional safety standards such as ISO26262 and FMEDA (preferred). Who You Are: Independent and precise in your work. Innovative and proactive in problem-solving. Excellent communicator and team player. Detail-oriented with a strong analytical mindset. Eager to learn and grow within a technical role

Requirements: Bachelors/masters with good academic record. 5+ years experience in developing HVL based verification environments, preferably using System Verilog. Exposure to coverage driven verification. Experience in verification methodologies like UVM/OVM. Exposure to complex SV test benches involving multiple protocols and VIPs. Experience in VIP development is highly desirable. Should have a work exposure on any of the industry standard protocols like Jedec UFS, MIPI Unipro, MIPI MPHY, PCIe, USB, Ethernet, etc. Demonstrates good analysis and problem-solving skills. Have a strong passion for work and driving things to closure. Leadership qualities to motivate and align team members towards business goals and priorities. As a motivator/leader of the R&D team in Synopsys, you will be responsible for Development and enhancements of features, flows and solutions Quality execution of VIP development, taking responsibility for designing, developing, debugging, creation of reliable plans and effort estimates for your projects. Focus on innovation to ensure continuous product enhancements

You Are: A highly-skilled ASIC Digital Verification Engineer with a passion for developing functional verification solutions for RTL based IP Cores You are experienced in handling complex protocols and thrive in a collaborative international environment With over 15 years of experience, you possess a deep understanding of verification methodologies and are proficient in SystemVerilog (SV) and Universal Verification Methodology (UVM) You are adept at making architectural decisions, implementing test benches, and driving innovation in verification solutions You are a proactive team player with excellent communication and problem-solving skills, ready to contribute to cutting-edge projects in AI/machine learning, automotive, and server farm applications What Youll Be Doing: Making architecture decisions on test bench design Writing verification plans and specifications Implementing test bench infrastructure and writing test cases Utilizing a coverage-driven methodology Providing technical leadership and guidance to the team Collaborating with architects, designers, and other verification team members across multiple sites worldwide The Impact You Will Have: Ensuring the reliability and performance of IP Cores used in critical applications Driving innovation in verification methodologies and solutions Contributing to the development of industry-leading technologies in AI, automotive, and server farms Enhancing productivity and throughput through effective verification strategies Maintaining high standards of quality and functionality in IP verification Mentoring and guiding junior engineers, fostering a culture of continuous learning and improvement What Youll Need: Extensive knowledge of protocols such as DDR, PCIe, AMBA (AXI, CHI), SD/eMMC, Ethernet, USB, MIPI Hands-on experience in creating test environments from functional specifications using UVM/VMM/OVM Proficiency in SystemVerilog (SV), UVM, and object-oriented coding and verification Ability to provide innovative verification solutions for enhanced productivity and performance Experience with scripting languages like C/C++, TCL, Perl, Python is an added advantage Experience of working with Functional safety, ISO26262 , FMEDA is an added advantage Who You Are: You are an independent thinker with a precise approach to work, capable of driving innovation and leading technical projects Your communication skills are excellent, and you thrive in a team-oriented environment You are committed to continuous learning and possess a strong problem-solving aptitude Experience with functional safety standards like ISO26262 and FMEDA is a plus The Team Youll Be A Part Of: You will be part of the Solutions Group at our Bangalore Design Center, India This team is dedicated to developing functional verification solutions for IP used in diverse applications, including server farms, AI/machine learning, and automotive sectors You will work closely with architects, designers, and other verification team members across multiple international sites, contributing to innovative and challenging projects Rewards and Benefits: We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs Our total rewards include both monetary and non-monetary offerings Your recruiter will provide more details about the salary range and benefits during the hiring process

The candidate would be part of the VIP group responsible for development of Verification IPs. Core responsibilities would include Designing and developing the VIP/Test-bench, Creating Verification plans, Coding sequences/Test-scenarios, Coverage driven verification. The responsibility would also include enhancement of the existing Verification IP products and interface with customers during VIP deployment. This is an opportunity to work with best-in-class verification, debug tools, Design IP & close collaboration with best protocol experts in the industry. You will work with highly professional and motivated colleagues who value and support your contribution. Requirements: Bachelors/masters with good academic record. 7+ years experience in developing HVL based verification environments, preferably using System Verilog. Exposure to coverage driven verification. Experience in verification methodologies like UVM/OVM. Exposure to complex SV test benches involving multiple protocols and VIPs. Experience in VIP development is highly desirable. Should have a strong work exposure on any of the industry standard protocols like PCIe, USB, Ethernet, MIPI etc.. Demonstrates good analysis and problem-solving skills. Have a strong passion for work and driving things to closure.