4 Constraints Management Jobs

As a CPU/GPU/IP Implementation Methodologies Engineer, you will be responsible for developing innovative methodologies to implement high-performance CPUs, GPUs, and interface IPs. You will utilize advanced technologies and tools to enhance the quality of results and streamline the implementation process. Your role will also involve contributing to the development and implementation of power, performance, and area (PPA) methodologies for complex IPs. You will work with industry-leading Synopsys tools like RTLA and Fusion Compiler to address critical design challenges. Collaboration with a global team will be essential to ensure staying ahead of technological advancements and design complexities. Your contribution will be crucial in driving continuous improvement in PPA and turnaround time (TAT) metrics. To excel in this role, you must possess deep knowledge of synthesis, timing closure, power optimization, and constraints management. Your experience with low-power, high-performance design at advanced nodes below 5nm will be valuable. Proficiency in RTL, DFT, LDRC, TCM, VCLP, and PTPX is required to effectively carry out your responsibilities. Familiarity with scripting languages such as TCL, Perl, and Python will aid in performing tasks efficiently. A BS or MS in Electrical Engineering or a related field along with 9+ years of relevant experience is necessary to succeed in this position.,

Sr. Engineer - ASIC Digital Design (Physical Implementation/Design/STA, 2+ years of exp) We Are: At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation. You Are: You are a highly skilled and experienced ASIC Digital Design Engineer passionate about working on the latest processes for STA and physical implementation flows on cutting-edge technology nodes. You thrive in dynamic environments and excel in collaborating with functional teams to optimize and develop IO validation vehicles, Mixed Signal IPs, 3DIO PHYs and UCIe-3D PHY. You have a strong focus on Timing Closure and are adept at defining signoff criteria. Your background includes extensive experience with ASIC design flow, hierarchical physical design strategies, and a deep understanding of sub-micron technology issues. You possess a strong knowledge of timing analysis, constraints management, and various verification strategies, including Primepower-based power analysis. Your scripting skills are excellent, and you are innovative, self-motivated, and able to work both independently and as part of a team. Your communication skills, both verbal and written, are outstanding, and you have a desire to understand RTL/Timing signoff criteria. What Youll Be Doing: Working on new processes for physical implementation flows and cutting-edge technology nodes. Collaborating with functional teams to optimize and develop Qualificaition vehicles and 3D PHYs. Defining signoff criteria with a strong focus on Timing Closure. Maturing the physical implementation guide used for customers and internal hardening teams. Participating in next-generation physical design methodology and flow development. Performing physical design implementation, including synthesis, floor planning, PG Grid design, PnR, CTS, STA, and power/signal integrity signoff. Evaluating PPA targets (Area/Speed/Power) and collaborating with the design team to improve design and constraints. The Impact You Will Have: Ensuring the optimization and successful implementation of cutting-edge technology nodes. Contributing to the development of high-performance silicon chips and software content. Enhancing the efficiency and performance of Synopsys IPs through rigorous timing closure and signoff criteria. Improving customer satisfaction by maturing physical implementation guides. Supporting the achievement of Synopsys' operational goals through innovative design solutions. What Youll Need: Extensive experience with ASIC design flow and hierarchical physical design strategies. Strong background in timing analysis, constraints management, and frontend synthesis. Experience with physical-aware synthesis, formality, and various verification strategies. Knowledge of Primepower-based power analysis and clock gating for power reduction. Fair knowledge of FC design planning methodologies, floor planning, and PG Grid creation using Synopsys Tools. Strong physical implementation flow debugging skills and scripting abilities. Who You Are: Innovative, self-motivated, and able to work independently or as a team player. Excellent verbal and written communication skills. Strong analytical and problem-solving abilities. Passionate about continuous learning and staying updated with the latest technological advancements in ASIC digital design. The Team Youll Be A Part Of: You will join a highly skilled and collaborative team focused on developing and optimizing physical design flows for cutting-edge technology nodes. The team is dedicated to innovation, continuous improvement, and delivering high-performance solutions that meet the evolving needs of our customers. Rewards and Benefits: We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process. Show more Show less

You are a highly skilled and experienced engineer with a deep understanding of synthesis, timing closure, power optimization, and constraints management. Your expertise includes working on advanced nodes under 5nm and proficiency in low-power, high-performance design. Familiarity with RTL, DFT, LDRC, TCM, VCLP, and PTPX gives you an edge in tackling complex design challenges. Your ability to use scripting languages such as TCL, Perl, and Python is a valuable asset. Holding a BS or MS in Electrical Engineering or a related field with over 9 years of relevant experience, you are well-equipped to drive continuous technological innovation and transform the future. Your responsibilities will include developing innovative methodologies for implementing high-performance CPUs, GPUs, and interface IPs. You will utilize advanced technologies and tool features to enhance quality of results and streamline the implementation process. Contributing to the development and implementation of power, performance, and area (PPA) methodologies for complex IPs will be a key part of your role. Working with industry-leading Synopsys tools such as RTLA and Fusion Compiler, you will solve critical design challenges and collaborate with a global team to stay ahead of technological advancements. Your impact will be significant as you advance the state-of-the-art in high-performance core and IP implementation, enhance the performance and efficiency of Synopsys" design methodologies and tools, and enable the development of cutting-edge semiconductor technologies at advanced nodes. You will contribute to the successful delivery of high-quality, high-performance IPs to the market, drive innovation, and support Synopsys" mission to lead in chip design, verification, and IP integration. To excel in this role, you will need deep knowledge of synthesis, timing closure, power optimization, and constraints management, along with experience in low-power, high-performance design at advanced nodes under 5nm. Proficiency in RTL, DFT, LDRC, TCM, VCLP, and PTPX, as well as familiarity with scripting languages such as TCL, Perl, and Python, are essential. A BS or MS in Electrical Engineering or a related field with 9+ years of relevant experience will further strengthen your qualifications. You are a detail-oriented and innovative engineer with a passion for pushing the limits of technology. Your problem-solving skills, ability to optimize design processes, and effective collaboration with a global team set you apart. Motivated by continuous improvement and making a significant impact in the field of semiconductor design, you are well-suited to join the growing global team at Synopsys dedicated to advancing high-performance core and IP implementation.,

The role requires a strong understanding of Oracle database architecture and administration, along with proficiency in Linux server administration. It is essential to stay updated with the latest developments and best practices in both Oracle databases and Linux systems to effectively manage and optimize their performance. Key Responsibilities include installing and maintaining the Oracle database software, familiarizing with Oracle database management tools and utilities, resolving user-related queries in Production and Test Databases, creating new users and assigning profiles in production databases as per client request, managing and maintaining all database users, logical backup using Export-Import and Data Pump utility, managing Database Structure, Storage Allocation, Table/Index segments, Rollback Segments, Undo Segments, and Constraints. The ideal candidate should have 3+ years of experience in Oracle Database Administration, strong database and operating system concepts, a basic understanding of SQL and PL/SQL programming languages, experience in Oracle Real Application Clusters (RAC) and Data Guard, and experience in Patching and cloning of Oracle database. Additionally, candidates should be able to provide 24/7 operational & project support for Oracle Database Technology and should be willing to work over the weekends for scheduled maintenance activities. Experience with Oracle Engineered Systems such as Exadata, ODA, Virtualization like OLVM, Open Source databases like MySQL or PostgreSQL, MS SQL Server, cloud platforms like Azure, OCI, or AWS, ServiceNow, LogicMonitor, and previous MSP experience are considered additional positives. Interested candidates can send their updated resume to careers@suventure.in/madhuri@suventure.in.,