Technical Lead, Application Specific Integrated Circuit IP Design Google

6.0 - 10.0 years

0 Lacs

karnataka

On-site

As an RTL Engineering Lead at Google, you will play a vital role in driving innovation and developing custom silicon solutions for Google's direct-to-consumer products. Your contributions will be instrumental in shaping the future of hardware experiences that cater to millions of users worldwide. By leveraging your expertise, you will enhance performance, efficiency, and integration in the next generation of Google products. With a Bachelor's degree in Electrical Engineering, Computer Science, or equivalent practical experience, along with 6 years of hands-on experience in micro-architecture and coding, particularly in memory compression, interconnects, coherence, cache, Dynamic Random-Access Memory controller, and Physical Layer Device, you are well-equipped to excel in this role. Proficiency in Verilog or SystemVerilog language is a must to thrive in this dynamic environment. Ideally, you possess experience in high-performance design, multi-power domains with complex clocking, and have a proven track record of delivering successful SoCs. Your expertise in microarchitecture design and system design will be pivotal in developing highly optimized IPs with excellent Power, Performance, and Area (PPA) metrics. Familiarity with chip design flow and quality checks at the front end, including Lint, CDC/RDC, Synthesis, and Line Echo Cancellation, will further enhance your capabilities. In this role, you will lead a team of RTL engineers, overseeing IP development plan tasks, conducting code and design reviews, and driving the development of complex features within the IP. Collaboration with the architecture team is essential to strategize microarchitecture and coding implementations that align with quality, schedule, and PPA goals. Additionally, you will work closely with cross-functional teams, including Verification, Design for Test, Physical Design, and Software teams, to make informed design decisions and ensure project progress is effectively communicated throughout the development lifecycle. Join our diverse team of passionate individuals who are committed to pushing boundaries and creating innovative solutions that enhance the lives of people globally. Together, we aim to make technology faster, seamless, and more powerful, ultimately realizing Google's mission of organizing the world's information and making it universally accessible and useful.,

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STA - Synthesis Design Engineer 2 Advanced Micro Devices (AMD)

2.0 - 7.0 years

3 - 6 Lacs

Hyderabad, Telangana, India

On-site

THE ROLE: The focus of this role is to execute the front end implementation of sub-blocks or IP. This involves ownership of synthesis, LEC, CLP, prelayout STA and postlayout STA/Timing closure. Co-ordinate with design team and PNR teams. KEY RESPONSIBILITIES: Responsible for front end implementation of IPs which includes synthesis, LEC, CLP, prelayout STA and postlayout STA/Timing closure Collaborate with designer and PNR teams to achieve closure. Execute as per schedule. Complete quality delivery for synthesis and timing closure. Debug and resolve technical issues PREFERRED EXPERIENCE: Experienced in synthesis and timing closure Good to have experience in LEC, CLP Have handled blocks with complex designs, high frequency clocks and complex clocking complete understanding of timing constraints, low power aspects and concepts of DFT Have debug experience to solve issues. scripting and automation ACADEMIC CREDENTIALS: Bachelors with 2 years of experience or Masters degree with 1 years of experience in Electrical Engineering

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