437 Compiler Jobs - Page 18

Company Qualcomm India Private Limited Job Area Engineering Group, Engineering Group > Hardware Engineering General Summary As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. Job Role Should have strong understanding and in-depth knowledge of Physical Synthesis and Synthesis methodologies with leading industry standard tools.Experience with writing timing constraints for synthesis, STA, timing closure and pipelining at different levels for performance optimization and timing closure.Experience in all aspects of timing closure for multi-clock domain designs.Should be familiar with MCMM synthesis and optimization.Should have good understanding of low-power design implementation using UPF.Experience with scripting language such as Perl/ Python, TCL.Experience with different power optimization flows or technique such as clock gating.Should be able to work independently with design, DFT and PD team for netlist delivery, timing constraints validationShould be able to handle ECOs and formal verification and maintain high quality matrix Skill Set Proficiency in Python/Tcl Familiar with Synthesis tools (Fusion Compiler/Genus), Fair knowledge in LEC, LP signoff tools Proficient in VLSI front end design steps- Verilog/VHDL, Synthesis, QoR optimization & Equivalence Checking Familiarity with standard software engineering practices like Version Control, Configuration Management, Regression is a plus Should be sincere, dedicated and willing to take up new challenges Applicants: Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries). Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law. To all Staffing and Recruiting Agencies: Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications. If you would like more information about this role, please contact Qualcomm Careers. 3075441

Company Qualcomm India Private Limited Job Area Engineering Group, Engineering Group > Hardware Engineering General Summary As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. 5+ Year of industry experiences in the following areas: Expertise in Synthesis - Synopsys Design Compiler, DCG/DC_NXT/Fusion Compiler and/or Cadence RC/Genus. o Hands on with multi-voltage, power aware synthesis, UPF flows in synthesis and low power designs. o Expertise in formal verification with Cadence LEC/ Synopsys Formality o Expertise in writing and debugging timing constraints o Perl and/or TCL scripting, makefile flows. Qualcomm's compute sub system engineers will work on next generation low power, machine Learning sub-system for our system-on-chip (SoC) products used in Smartphone, Automotive and other low power devices. Become a key member of the core team developing fastest smartphone SoC devices implemented on the latest cutting-edge process technologies. In this role candidate will be responsible for compute sub system implementation that includes Physically aware Synthesis -DCG/Fusion Compiler/Genus. In addition, he/she will perform tasks toward constraints development, clock definitions, timing analysis, UPF, CLP check, Formal Verification and ECO flow. He/She will be working closely with physical Design team to optimize designs for power, area, and performance. Applicants: Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries). Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law. To all Staffing and Recruiting Agencies: Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications. If you would like more information about this role, please contact Qualcomm Careers. 3075459

JOB DESCRIPTION YOU ARE READY TO MAKE AN IMPACT As a member of Oracle’s Financial Services Enterprise Risk and Finance Development organization, you’ll work in a multidisciplinary team to design, develop and deliver leading edge next generation SaaS solutions for the global marketplace. Our development approach balances user design with best-in-class software development practices, in close alignment with business objectives. YOU ARE SETTING STANDARDS As a Cloud UI Senior Software Developer, you will design, develop, deliver, operate and support one or more user interfaces comprising our next generation cloud native Financial Services solution. In this capacity you exhibit the following qualities: Self-Starter. You are motivated and ambitious and you pursue your work without the help or prompting of others. Problem Solver. You focus on problem solving and your can-do attitude accelerates our work and brings our solutions alive. Efficient. You perform your work in a well-organized and competent way with minimum wasted effort or expense. Aligned. You are aligned to the goals and objectives of the organization, the organization’s development agenda and the management team’s priorities, doing your part in a flexible and proactive way to achieve the overall mission. RESPONSIBILITIES YOU ARE SKILLED To land this job you will demonstrate expertise in the following areas: Deep knowledge of HTML, JavaScript, CSS (SASS a plus), DHTML, DOM, Ajax and OJET 4+ years developing user interfaces Expertise using Spring MVC and other frameworks Web Services and APIs using the latest technologies Understanding of design for Mobile Devices and Responsive Design Techniques Continuous integration for real-time testing and diagnostics Responding to reported incidents and anomalies Qualifications Primary Skills Minimum 4+ years coding experience in JavaScript, HTML5, CSS 4+ years expereince with React and experience with handling complex text based event loops (e.g natural language grammar cheking) Expereince building EBNF grammars, working with language servers (LSP) and other compiler technologies are highly regarded Comfortable building complex UI event handling logic and building high performing REact/ Preact components from the ground up Experience with REST Hands on experience with user interface development for mobile devices Experience developing rich UI’s for data visualization Exposure to Cloud concepts (SaaS, PaaS, IaaS) with Oracle Cloud, AWS, or Azure, any certification(s) a plus Problem solving skills Proven design skills and expertise Excellent writing and oral communications skills (in English) Natural collaborator who enjoys working in cross organizational teams residing in multiple time zones. Secondary Skills Practiced Agile Development and knowledge of Tools such as Confluence/JIRA Exposure to Selenium, PostMan Tools Experience in consuming and working with web services QUALIFICATIONS Career Level - IC3 ABOUT US As a world leader in cloud solutions, Oracle uses tomorrow’s technology to tackle today’s challenges. We’ve partnered with industry-leaders in almost every sector—and continue to thrive after 40+ years of change by operating with integrity. We know that true innovation starts when everyone is empowered to contribute. That’s why we’re committed to growing an inclusive workforce that promotes opportunities for all. Oracle careers open the door to global opportunities where work-life balance flourishes. We offer competitive benefits based on parity and consistency and support our people with flexible medical, life insurance, and retirement options. We also encourage employees to give back to their communities through our volunteer programs. We’re committed to including people with disabilities at all stages of the employment process. If you require accessibility assistance or accommodation for a disability at any point, let us know by emailing accommodation-request_mb@oracle.com or by calling +1 888 404 2494 in the United States. Oracle is an Equal Employment Opportunity Employer. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability and protected veterans’ status, or any other characteristic protected by law. Oracle will consider for employment qualified applicants with arrest and conviction records pursuant to applicable law. Show more Show less

Job Description: C++ Architect Overview We are seeking an experienced and proficient C++ Enterprise Architect to oversee all phases of software architectural work, including planning, designing, and supervising the development process. The successful candidate will be involved in creating new software systems, extending existing systems, and implementing innovative solutions from the initial stages through to project completion. The primary objective is to align with clients' requirements and deliver sustainable, scalable, functional, and high-performance software designs. Responsibilities Lead and oversee enterprise software architectural projects from inception to delivery. Engage with stakeholders to understand their business requirements and devise architectural solutions that align with their strategic objectives. Prepare comprehensive architectural blueprints, models, and specifications. Ensure strict adherence to all relevant industry standards, protocols, and regulations. Coordinate with engineering and development teams to facilitate seamless integration and execution of the architecture in projects. Supervise the development lifecycle to ensure timely, within-budget, and high-quality project completion. Evaluate existing systems and provide recommendations to meet organizational requirements. Provide technical leadership and mentorship to junior architects and development teams. Conduct code reviews and architectural evaluations to monitor progress and address technical challenges. Stay informed on the latest trends, technologies, and best practices in enterprise software development. Requirements Bachelor's or Master's degree in Computer Science, Engineering, Information Technology, or a related field. Extensive experience as an Enterprise, Technical, or Software Architect, or in a related role, with over 12 years (M Level) to 15+ years (SM Level) of experience in C++ 11 or later. Strong proficiency in C++ 11/C++14/C++17/C++20 or later, with excellent design and visualization skills, and familiarity with relevant software tools. In-depth knowledge of software development methodologies, standards, and best practices, with the ability to develop high-quality software that meets requirements and facilitates ease of support. Strong project management and organizational skills, and the ability to work collaboratively in a team environment. Excellent communication and interpersonal skills, with a creative and innovative mindset. Ability to diagnose, isolate, and implement remedies for system failures caused by errors in software code, and develop software for complex, performance-intensive programs in resource-scarce environments. Utilize software-based system maintenance and tracking tools, and provide input and technical content for technical documentation, user help materials, and customer training. Conduct unit tests, track problems, and implement changes to ensure adherence to test plans and functional/non-functional requirements. Analyze, design, and implement software mechanisms to improve code stability, performance, and reusability; participate in and lead code review sessions. Create high-fidelity estimates of work efforts, assist others in estimating task effort and dependencies, and be responsible for team commitments within the Sprint. Lead and advise other Engineering resources as part of project activities and be recognized as subject matter experts in their chosen field. Stay current with technology and industry trends, disseminate knowledge to team members, and establish best practices through participation in industry groups. Communicate effectively with Management, Stakeholders, and other internal teams, and participate in cross-functional collaboration within the organization. Must Have Skills In-depth knowledge of Object-Oriented Programming, Algorithmic skills, and Design Patterns. Proficiency in Data Structures such as Vector, List, Map, Hash Map, etc. Expertise in Templates, Casting, Inheritance. Experience with Multi-threading and Socket Programming using TCP, UDP, SSL etc. Ability to design a Class Model, Data Model for given requirements. Strong debugging skills, experience with Memory Leaks, Profiling, Crashes, blue screen issues. Hands-on experience with C++11 or later, C++ GNU Toolchain (gcc, g++, gdb etc.), cross-compiler toolchains, Linux OS, Kernel programming or Visual C++ using Microsoft Visual Studio, DLL development. Hands-on with build tools like make, CMake, Static analyzers, code checkers, etc. Knowledge of common C++ tools & libraries including STL, HTTP libraries, xml, QT framework. Proficiency in scripting languages like Bash shell scripts and Python3. Experience with version control tools like GIT, Gerrit, GitHub, Bitbucket. Experience with bug trackers and agile development tools like Jira. Deep understanding of Software Development and Quality Assurance best practices. Strong teamwork and collaboration abilities, along with proficient written and verbal communication skills. Experience operating in an Agile environment, with a deep understanding of agile development principles. Experience with Jenkins or Ansible, CI/CD pipeline, Dockers, Kubernetes, Azure/GCP, and Gen AI, code companion tools like Microsoft co-pilot is preferred. If you are a passionate and talented C++ Software Architect ready to undertake challenging projects and make a lasting impact, we would be delighted to hear from you. Apply today and join our team of dedicated professionals in creating innovative and high-performance software solutions. Show more Show less

Overview: WHAT YOU DO AT AMD CHANGES EVERYTHING We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences – the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world’s most important challenges. We strive for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives. AMD together we advance_ Responsibilities: LOCATION: Bangalore WHAT YOU’LL BE DOING: Candidate has opportunitites to work on functional and performance analysis of various enterprise tools and also research on LLVM compiler support for various cutting edde modern programming lanugages. If good in LLVM compiler tool chain and compiler internals, has potential opportunity to get hands on modern programming standards. Candidate can leverage opportunity to understand end to end flow of compiler development Opportunity to contribute and claim to the success of AMD CPU compilers working with the world class compiler engineers and performance engineers in AMD and in opensource communities Daily responsibilities may include root cause analysis of compiler issues, communicating with the compiler engineers, participating in team meetings, downstreaming LLVM community code, research on compiler functions across AOCC and competition etc.. By end of the COOP candidate is expected to have gained a good knowledge and experience on end to end work flow of compiler development and release. A good knowledge on functional support of LLVM, GCC and intel compilers. Potential to gain confidence on compiler engineering with hands on to compiler code base KEY QUALIFICATIONS: Compiler design, LLVM/GCC compiler tool chain, Strong in C++. Any knowledge in devops tools and process including gtihup, gerrit and Jenkins is an added advantage Do not include specific years of experience, or use the word REQUIRED (use preferred or desired). WHAT WOULD SET YOU APART: Good problem solving skills. Appetite to learn and explore the unknown WHO WE’RE LOOKING FOR: Bachelors in computer engineering from a reputed institute with good communication skills who is looking for COOP in his/her final year #LI-SG1 Qualifications: Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

Meta is hiring ASIC Frontend Implementation Engineers within our Infrastructure organization. We are looking for individuals with experience in front-end implementation from RTL to netlist, including RTL Lint, CDC analysis, timing constraints, synthesis to build efficient System on Chip (SoC) and IP for data center applications. ASIC Frontend Implementation, CDC/RDC Responsibilities: Perform Flat and Hierarchical Clock Domain Crossing and work with the designers to analyze the complex clock domain crossings and sign off the CDC. Perform Flat and Hierarchical Reset Domain crossing Checks. Understand the Reset-Architecture by working with Design and FW teams and develop reset groups and the corresponding reset sequence for RDC. Perform RTL Lint and work with the Designers to create waivers. Perform RTL DFT Analysis and improve the DFT coverage for Stuck-at faults. Run Logic/Physical Synthesis using advanced optimization techniques and generate optimized Gate Level Netlist for Timing, Area, Power. Developing Automation scripts and Methodology for all FE-tools including (Lint, CDC, RDC,). Work closely with the Design Engineers, DV Engineers, Emulation Engineers in supporting them with the handoff tasks. Interact with Physical Design Engineers and provide them with timing/congestion feedback. Minimum Qualifications: Bachelor's degree in Computer Science, Computer Engineering, relevant technical field, or equivalent practical experience. 8+ years of experience in static verification tools Experience with Lint, Clock Domain & Reset Domain crossing. Knowledge of SOC Integration (Clocking, Reset, PLL, etc) Knowledge of front-end ASIC flows Experience with RTL design using SystemVerilog or other HDL. Bachelor's degree in Computer Science, Computer Engineering, relevant technical field, or equivalent practical experience. 5+ years of experience in static verification tools Experience with communicating across functional internal teams and vendors. Experience with Lint, Clock Domain & Reset Domain crossing Experience with SOC CDC signoff Knowledge of SOC Integration (Clocking, Reset, PLL, etc) Knowledge of front-end ASIC flows Experience with RTL design using SystemVerilog or other HDL. Experience with communicating across functional internal teams and vendors. Preferred Qualifications: Experience with SOC Design Integration and Front-End Implementation Knowledge of Timing/physical libraries, SRAM Memories. Experience with Design Compiler, Spyglass, PrimeTime, Formality or equivalent tools. Experience with Netlist-CDC Analysis and improving MTBF Experience with developing structural rule based checks for RTL & Netlist Scripting and programming experience using Perl/Python, TCL, and Make Experience with SOC Design Integration and Front-End Implementation. Knowledge of Timing/physical libraries, SRAM Memories. Experience with Design Compiler, Spyglass, PrimeTime, Formality or equivalent tools. Experience with Netlist-CDC Analysis and improving MTBF Experience with developing structural rule based checks for RTL & Netlist Scripting and programming experience using Perl/Python, TCL, and Make. About Meta: Meta builds technologies that help people connect, find communities, and grow businesses. When Facebook launched in 2004, it changed the way people connect. Apps like Messenger, Instagram and WhatsApp further empowered billions around the world. Now, Meta is moving beyond 2D screens toward immersive experiences like augmented and virtual reality to help build the next evolution in social technology. People who choose to build their careers by building with us at Meta help shape a future that will take us beyond what digital connection makes possible today—beyond the constraints of screens, the limits of distance, and even the rules of physics. Individual compensation is determined by skills, qualifications, experience, and location. Compensation details listed in this posting reflect the base hourly rate, monthly rate, or annual salary only, and do not include bonus, equity or sales incentives, if applicable. In addition to base compensation, Meta offers benefits. Learn more about benefits at Meta.

Institute of Information Science Postdoctoral Researcher 2 Person The Computer Systems Laboratory - Machine Learning Systems Team Focuses On Research Areas Including Parallel And Distributed Computing, Compilers, And Computer Architecture. We Aim To Leverage Computer System Technologies To Accelerate The Inference And Training Of Deep Learning Models And Develop Optimizations For Next-generation AI Models. Our Research Emphasizes The Following Job DescriptionUnit Institute of Information ScienceJobTitle Postdoctoral Researcher 2 PersonWork Content Research on Optimization of Deep Learning Model Inference and Training AI Model Compression and Optimization Model Compression Techniques (e.g., Pruning And Quantization) Reduce The Size And Computational Demands Of AI Models, Which Are Crucial For Resource-constrained Platforms Such As Embedded Systems And Memory-limited AI Accelerators. We Aim To Explore AI compiler: deployment methods for compressed models across servers, edge devices, and heterogeneous systems. High performance computing: efficient execution of compressed models on processors with advanced AI extensions, e.g., Intel AVX512, ARM SVE, RISC-V RVV, and tensor-level accelerations on GPUs and NPUs. AI Accelerator Design We aim to design AI accelerators for accelerating AI model inference, focusing on software and hardware co-design and co-optimization. Optimization of AI Model Inference in Heterogeneous Environments Computer Architectures Are Evolving Toward Heterogeneous Multi-processor Designs (e.g., CPUs + GPUs + AI Accelerators). Integrating Heterogeneous Processors To Execute Complex Models (e.g., Hybrid Models, Multi-models, And Multi-task Models) With High Computational Efficiency Poses a Critical Challenge. We Aim To Explore Efficient scheduling algorithms. Parallel algorithms for the three dimensions: data parallelism, model parallelism, and tensor parallelism. Qualifications Ph.D. degree in Computer Science, Computer Engineering, or Electrical Engineering Experience in parallel computing and parallel programming (CUDA or OpenCL, C/C++ programming) or hardware design (Verilog or HLS) Proficient in system and software development Candidates With The Following Experience Will Be Given Priority Experience in deep learning platforms, including PyTorch, TensorFlow, TVM, etc. Experience in high-performance computing or embedded systems. Experience in algorithm designs. Knowledge of compilers or computer architectureWorking EnvironmentOperating Hours 8:30AM-5:30PMWork Place Institute of Information Science, Academia SinicaTreatment According to Academia Sinica standards: Postdoctoral Researchers: NT$64,711-99,317/month. Benefits include: labor and healthcare insurance, and year-end bonuses. Reference Site 洪鼎詠網頁: http://www.iis.sinica.edu.tw/pages/dyhong/index_zh.html, 吳真貞網頁: http://www.iis.sinica.edu.tw/pages/wuj/index_zh.html Please Email Your CV (including Publications, Projects, And Work Experience), Transcripts (undergraduate And Above), And Any Other Materials That May Assist In The Review Process To The Following PIs Acceptance MethodContacts Dr. Ding-Yong Hong Contact Address Room 818, New IIS Building, Academia Sinica Contact Telephone 02-27883799 ext. 1818Email dyhong@iis.sinica.edu.tw Required Documents Dr. Ding-Yong Hong: dyhong@iis.sinica.edu.tw Dr. Jan-Jan Wu: wuj@iis.sinica.edu.twPrecautions for application DatePublication Date 2025-01-20Expiration Date 2025-12-31

JOB DESCRIPTION YOU ARE READY TO MAKE AN IMPACT As a member of Oracle’s Financial Services Enterprise Risk and Finance Development organization, you’ll work in a multidisciplinary team to design, develop and deliver leading edge next generation SaaS solutions for the global marketplace. Our development approach balances user design with best-in-class software development practices, in close alignment with business objectives. YOU ARE SETTING STANDARDS As a Cloud UI Senior Software Developer, you will design, develop, deliver, operate and support one or more user interfaces comprising our next generation cloud native Financial Services solution. In this capacity you exhibit the following qualities: Self-Starter. You are motivated and ambitious and you pursue your work without the help or prompting of others. Problem Solver. You focus on problem solving and your can-do attitude accelerates our work and brings our solutions alive. Efficient. You perform your work in a well-organized and competent way with minimum wasted effort or expense. Aligned. You are aligned to the goals and objectives of the organization, the organization’s development agenda and the management team’s priorities, doing your part in a flexible and proactive way to achieve the overall mission. RESPONSIBILITIES YOU ARE SKILLED To land this job you will demonstrate expertise in the following areas: Deep knowledge of HTML, JavaScript, CSS (SASS a plus), DHTML, DOM, Ajax and OJET 4+ years developing user interfaces Expertise using Spring MVC and other frameworks Web Services and APIs using the latest technologies Understanding of design for Mobile Devices and Responsive Design Techniques Continuous integration for real-time testing and diagnostics Responding to reported incidents and anomalies Qualifications Primary Skills Minimum 4+ years coding experience in JavaScript, HTML5, CSS 4+ years expereince with React and experience with handling complex text based event loops (e.g natural language grammar cheking) Expereince building EBNF grammars, working with language servers (LSP) and other compiler technologies are highly regarded Comfortable building complex UI event handling logic and building high performing REact/ Preact components from the ground up Experience with REST Hands on experience with user interface development for mobile devices Experience developing rich UI’s for data visualization Exposure to Cloud concepts (SaaS, PaaS, IaaS) with Oracle Cloud, AWS, or Azure, any certification(s) a plus Problem solving skills Proven design skills and expertise Excellent writing and oral communications skills (in English) Natural collaborator who enjoys working in cross organizational teams residing in multiple time zones. Secondary Skills Practiced Agile Development and knowledge of Tools such as Confluence/JIRA Exposure to Selenium, PostMan Tools Experience in consuming and working with web services QUALIFICATIONS Career Level - IC3 ABOUT US As a world leader in cloud solutions, Oracle uses tomorrow’s technology to tackle today’s challenges. We’ve partnered with industry-leaders in almost every sector—and continue to thrive after 40+ years of change by operating with integrity. We know that true innovation starts when everyone is empowered to contribute. That’s why we’re committed to growing an inclusive workforce that promotes opportunities for all. Oracle careers open the door to global opportunities where work-life balance flourishes. We offer competitive benefits based on parity and consistency and support our people with flexible medical, life insurance, and retirement options. We also encourage employees to give back to their communities through our volunteer programs. We’re committed to including people with disabilities at all stages of the employment process. If you require accessibility assistance or accommodation for a disability at any point, let us know by emailing accommodation-request_mb@oracle.com or by calling +1 888 404 2494 in the United States. Oracle is an Equal Employment Opportunity Employer. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability and protected veterans’ status, or any other characteristic protected by law. Oracle will consider for employment qualified applicants with arrest and conviction records pursuant to applicable law.

Chip Lead (Sr Mgr/Director) Hyderabad A Hyderabad based SoC product design company is looking for a talented, energetic and diligent SoC Director for leading the development of a new generation of devices. Job Description: We are seeking an experienced professional to lead full chip design for multi-million gate SoCs in the area of HBM. Job responsibilities include: Driving the specification of the chip with architect and design leads – eventually cascading into block specifications.Make PPA decisions for the chip.Defining multiple development checkpoints – for IP/SoC Design/DV/PDCome up with overall project plan and cascaded schedule details for other teamsWork with Analog/Digital IP teams to laydown integration details for the IPs.Drive the full chip floorplan / bump maps and provide area/floorplan targets to IP teams.Define the sign-off criteria for the device.Define the SoC verification plan items/scenarios to be covered.Assist/Review the micro architecture definition for digital blocksDefine RTL Quality gate criteria for integration – Lint/CDC/Drive the timing constraints/timing analysis/closure activities.Define the DFT targets for the chip and cascade that into activities needed on the DFT front.Work with PD enginers to get the physical design closure.Handle tapeout formalities Qualifications:Close to 15 years of solid experience in SoC design. A self starter. Candidate ready to define things where none exist. Ready for once in a lifetime project exposure, but ready to do heavy lifting for the effort.Proven ability to develop architecture and micro-architecture from specifications.Understanding of chip I/O design and packaging is advantageous.Experience in reviewing top-level test plans.Expertise in Synopsys Design Compiler for synthesis and formal verification.Strong working knowledge of timing closure processes.Experience with post-silicon bring-up and debugging.Familiarity with SoC integration challenges.Knowledge of design verification aspects is essential.Experience from SoC specification to GDS and commercialization is highly desired.Ability to make timely and effective decisions, even with incomplete information.Demonstrated expertise in specific technical areas, with significant experience in related fields.Provide direction, mentoring, and leadership to small to medium-sized teams.Strong communication and leadership skills are necessary for effective collaboration with program stakeholders. Contact:UdayMulya Technologiesmuday_bhaskar@yahoo.com"Mining The Knowledge Community"

Senior Software Technical Director / Software Technical DirectorWe are looking for a Software Technical Director with a strong technical foundation in systems software, Linux platforms, or machine learning compiler stacks to lead and grow a high-impact engineering team in Bangalore. You will be responsible for shaping the architecture, contributing to codebases, and managing execution across projects that sit at the intersection of systems programming, AI runtimes, and performance-critical software. Key Responsibilities: Technical Leadership:Lead the design and development of Linux platform software, firmware, or ML compilers and runtimes.Drive architecture decisions across compiler, runtime, or low-level platform components.Write production-grade C++ code and perform detailed code reviews.Guide performance analysis and debugging across the full stack—from firmware and drivers to user-level runtime libraries.Collaborate with architects, silicon teams, and ML researchers to build future-proof software stacks. Team & Project Management:Mentor and coach junior and senior engineers to grow technical depth and autonomy.Own end-to-end project planning, execution, and delivery, ensuring high-quality output across sprints/releases.Facilitate strong cross-functional communication with hardware, product, and other software teams globally.Recruit and grow a top-tier engineering team in Bangalore, contributing to the hiring strategy and team culture. Required Qualifications:Bachelor’s or Master’s degree in Computer Science, Electrical Engineering, or related field.18+ years of experience in systems software development with significant time spent in C++, including architectural and hands-on roles.Proven experience in either:Linux kernel, bootloaders, firmware, or low-level platform software, orMachine Learning compilers (e.g., MLIR, TVM, Glow) or runtimes (e.g., ONNX Runtime, TensorRT, vLLM).Excellent communication skills—written and verbal.Prior experience in project leadership or engineering management with direct reports. Highly Desirable:Understanding of AI/ML compute workloads, particularly Large Language Models (LLMs).Familiarity with performance profiling, bottleneck analysis, and compiler-level optimizations.Exposure to AI accelerators, systolic arrays, or vector SIMD programming. Why Join Us?Work at the forefront of AI systems software, shaping the future of ML compilers and runtimes.Collaborate with globally distributed teams in a fast-paced, innovation-driven environment.Build and lead a technically elite team from the ground up in a growth-stage organization. Contact:UdayMulya Technologiesmuday_bhaskar@yahoo.com"Mining The Knowledge Community"

Job Information Department Name Platforms & Compilers Job Type Full time Date Opened 25/04/2025 Industry Software Development Minimum Experience In Years 5 Maximum Experience In Years 10 City Chennai Province Tamil Nadu Country India Postal Code 600001 About Us MulticoreWare is a global software solutions & products company with its HQ in San Jose, CA, USA. With worldwide offices, it serves its clients and partners in North America, EMEA and APAC regions. Started by a group of researchers, MulticoreWare has grown to serve its clients and partners on HPC & Cloud computing, GPUs, Multicore & Multithread CPUS, DSPs, FPGAs and a variety of AI hardware accelerators. MulticoreWare was founded by a team of researchers that wanted a better way to program for heterogeneous architectures. With the advent of GPUs and the increasing prevalence of multi-core, multi-architecture platforms, our clients were struggling with the difficulties of using these platforms efficiently. We started as a boot-strapped services company and have since expanded our portfolio to span products and services related to compilers, machine learning, video codecs, image processing and augmented/virtual reality. Our hardware expertise has also expanded with our team; we now employ experts on HPC and Cloud Computing, GPUs, DSPs, FPGAs, and mobile and embedded platforms. We specialize in accelerating software and algorithms, so if your code targets a multi-core, heterogeneous platform, we can help. Job Description We are seeking a highly skilled and experienced Senior Compiler and Workload Performance Analyst. As a Senior Performance Analyst, you will play a pivotal role in analyzing and optimizing the performance of the compiler infrastructure and workloads. In addition, you will provide technical leadership, guidance, and mentorship to performance analysis teams. Your expertise in compiler technologies, workload analysis, and team leadership will drive the efficient and effective performance optimization of the target software systems. Responsibilities: Lead and mentor a team of performance analysts, providing technical guidance, support, and feedback to maximize individual and team performance. Conduct performance analysis and evaluation of the target compiler infrastructure, identifying bottlenecks and areas for optimization across various workloads and usage scenarios. Utilize advanced performance profiling and monitoring tools to gather and analyze performance data, identifying performance hotspots and areas of inefficiency. Develop and implement advanced performance optimization techniques, including algorithmic improvements, code transformations, and workload-specific optimizations. Lead workload analysis efforts, including workload modeling, characterization, and performance evaluation, to assess the performance impact on the compiler infrastructure. Generate comprehensive performance reports and documentation, presenting findings, recommendations, and optimization strategies to stakeholders in a clear and concise manner. Stay updated on the latest advancements in compiler technologies, workload analysis methodologies, and performance optimization techniques, driving innovation within the performance analysis teams. Qualifications: Bachelor's or Master's degree in Computer Science, Engineering, or a related field. Extensive experience as a Compiler and Workload Performance Analyst or in a similar role, with a strong track record in performance analysis and optimization. Experience in leading and mentoring teams, providing technical guidance, and fostering a collaborative and high-performance culture. In-depth expertise in compiler technologies, including compiler optimization techniques, code generation, and compiler internals. Proficiency in using performance profiling and monitoring tools to gather and analyze compiler and workload performance data. Strong knowledge of workload analysis methodologies, including workload modeling, characterization, and performance evaluation. Familiarity with programming languages such as C/C++, familiarity with LLVM or GCC compiler frameworks, and expertise in performance optimization at the compiler level. Solid understanding of computer architecture, hardware-software interactions, and workload-specific performance considerations. Strong analytical and problem-solving skills, with the ability to diagnose and resolve complex performance issues effectively. Attention to detail, a proactive mindset, and the ability to prioritize and manage multiple tasks and projects simultaneously

Senior SoC Director / SoC DirectorHyderabadFounded by highly respected Silicon Valley veterans - with its design centers established in Santa Clara, California. / Hyderabad/Bangalore A US based well-funded product-based startup looking for highly talented SoC Director for the following roles Senior Director / SoC Director of SOC is : Trust, loyalty, and ability to command Technical respect with foreign partners after having Taped out Successfully multiple chips to high volume production….this should be easily achieved under his/her belt !!!!!!!!Somebody we can trust to drive on the World stage without embarrassing us Job Description:We are seeking an experienced professional to lead full chip design for multi-million gate SoCs. The ideal candidate will have expertise in digital design and RTL development, with a deep understanding of the design convergence cycle, including architecture, micro-architecture, synthesis, timing closure, and verification.Key Responsibilities:Proficiency inInterconnect FabricCache CoherencyD2DC2COversee full chip design for complex SoCs.Develop and implement digital designs (RTL).Manage IP dependencies and track all front-end design tasks.Drive project milestones across design, verification, and physical implementation phases.Qualifications:At least 15-25 years of solid experience in SoC design.Proven ability to develop architecture and micro-architecture from specifications.Familiarity with bus protocols such as AHB and AXI, as well as peripherals like QSPI, NVMe, and I3C.Knowledge of memory controller designs and microprocessors is a plus.Understanding of chip I/O design and packaging is advantageous.Experience in reviewing top-level test plans.Expertise in Synopsys Design Compiler for synthesis and formal verification.Strong working knowledge of timing closure processes.Experience with post-silicon bring-up and debugging.Familiarity with SoC integration challenges.Knowledge of design verification aspects is essential.Experience from SoC specification to GDS and commercialization is highly desired.Ability to make timely and effective decisions, even with incomplete information.Demonstrated expertise in specific technical areas, with significant experience in related fields.Provide direction, mentoring, and leadership to small to medium-sized teams.Strong communication and leadership skills are necessary for effective collaboration with program stakeholders. Contact:UdayMulya Technologiesmuday_bhaskar@yahoo.com"Mining The Knowledge Community"