231 Compiler Jobs - Page 10

Chip Lead (Sr Mgr/Director) Hyderabad A Hyderabad based SoC product design company is looking for a talented, energetic and diligent SoC Director for leading the development of a new generation of devices. Job Description: We are seeking an experienced professional to lead full chip design for multi-million gate SoCs in the area of HBM. Job responsibilities include: Driving the specification of the chip with architect and design leads – eventually cascading into block specifications.Make PPA decisions for the chip.Defining multiple development checkpoints – for IP/SoC Design/DV/PDCome up with overall project plan and cascaded schedule details for other teamsWork with Analog/Digital IP teams to laydown integration details for the IPs.Drive the full chip floorplan / bump maps and provide area/floorplan targets to IP teams.Define the sign-off criteria for the device.Define the SoC verification plan items/scenarios to be covered.Assist/Review the micro architecture definition for digital blocksDefine RTL Quality gate criteria for integration – Lint/CDC/Drive the timing constraints/timing analysis/closure activities.Define the DFT targets for the chip and cascade that into activities needed on the DFT front.Work with PD enginers to get the physical design closure.Handle tapeout formalities Qualifications:Close to 15 years of solid experience in SoC design. A self starter. Candidate ready to define things where none exist. Ready for once in a lifetime project exposure, but ready to do heavy lifting for the effort.Proven ability to develop architecture and micro-architecture from specifications.Understanding of chip I/O design and packaging is advantageous.Experience in reviewing top-level test plans.Expertise in Synopsys Design Compiler for synthesis and formal verification.Strong working knowledge of timing closure processes.Experience with post-silicon bring-up and debugging.Familiarity with SoC integration challenges.Knowledge of design verification aspects is essential.Experience from SoC specification to GDS and commercialization is highly desired.Ability to make timely and effective decisions, even with incomplete information.Demonstrated expertise in specific technical areas, with significant experience in related fields.Provide direction, mentoring, and leadership to small to medium-sized teams.Strong communication and leadership skills are necessary for effective collaboration with program stakeholders. Contact:UdayMulya Technologiesmuday_bhaskar@yahoo.com"Mining The Knowledge Community"

Senior Software Technical Director / Software Technical DirectorWe are looking for a Software Technical Director with a strong technical foundation in systems software, Linux platforms, or machine learning compiler stacks to lead and grow a high-impact engineering team in Bangalore. You will be responsible for shaping the architecture, contributing to codebases, and managing execution across projects that sit at the intersection of systems programming, AI runtimes, and performance-critical software. Key Responsibilities: Technical Leadership:Lead the design and development of Linux platform software, firmware, or ML compilers and runtimes.Drive architecture decisions across compiler, runtime, or low-level platform components.Write production-grade C++ code and perform detailed code reviews.Guide performance analysis and debugging across the full stack—from firmware and drivers to user-level runtime libraries.Collaborate with architects, silicon teams, and ML researchers to build future-proof software stacks. Team & Project Management:Mentor and coach junior and senior engineers to grow technical depth and autonomy.Own end-to-end project planning, execution, and delivery, ensuring high-quality output across sprints/releases.Facilitate strong cross-functional communication with hardware, product, and other software teams globally.Recruit and grow a top-tier engineering team in Bangalore, contributing to the hiring strategy and team culture. Required Qualifications:Bachelor’s or Master’s degree in Computer Science, Electrical Engineering, or related field.18+ years of experience in systems software development with significant time spent in C++, including architectural and hands-on roles.Proven experience in either:Linux kernel, bootloaders, firmware, or low-level platform software, orMachine Learning compilers (e.g., MLIR, TVM, Glow) or runtimes (e.g., ONNX Runtime, TensorRT, vLLM).Excellent communication skills—written and verbal.Prior experience in project leadership or engineering management with direct reports. Highly Desirable:Understanding of AI/ML compute workloads, particularly Large Language Models (LLMs).Familiarity with performance profiling, bottleneck analysis, and compiler-level optimizations.Exposure to AI accelerators, systolic arrays, or vector SIMD programming. Why Join Us?Work at the forefront of AI systems software, shaping the future of ML compilers and runtimes.Collaborate with globally distributed teams in a fast-paced, innovation-driven environment.Build and lead a technically elite team from the ground up in a growth-stage organization. Contact:UdayMulya Technologiesmuday_bhaskar@yahoo.com"Mining The Knowledge Community"

Senior SoC Director / SoC DirectorHyderabadFounded by highly respected Silicon Valley veterans - with its design centers established in Santa Clara, California. / Hyderabad/Bangalore A US based well-funded product-based startup looking for highly talented SoC Director for the following roles Senior Director / SoC Director of SOC is : Trust, loyalty, and ability to command Technical respect with foreign partners after having Taped out Successfully multiple chips to high volume production….this should be easily achieved under his/her belt !!!!!!!!Somebody we can trust to drive on the World stage without embarrassing us Job Description:We are seeking an experienced professional to lead full chip design for multi-million gate SoCs. The ideal candidate will have expertise in digital design and RTL development, with a deep understanding of the design convergence cycle, including architecture, micro-architecture, synthesis, timing closure, and verification.Key Responsibilities:Proficiency inInterconnect FabricCache CoherencyD2DC2COversee full chip design for complex SoCs.Develop and implement digital designs (RTL).Manage IP dependencies and track all front-end design tasks.Drive project milestones across design, verification, and physical implementation phases.Qualifications:At least 15-25 years of solid experience in SoC design.Proven ability to develop architecture and micro-architecture from specifications.Familiarity with bus protocols such as AHB and AXI, as well as peripherals like QSPI, NVMe, and I3C.Knowledge of memory controller designs and microprocessors is a plus.Understanding of chip I/O design and packaging is advantageous.Experience in reviewing top-level test plans.Expertise in Synopsys Design Compiler for synthesis and formal verification.Strong working knowledge of timing closure processes.Experience with post-silicon bring-up and debugging.Familiarity with SoC integration challenges.Knowledge of design verification aspects is essential.Experience from SoC specification to GDS and commercialization is highly desired.Ability to make timely and effective decisions, even with incomplete information.Demonstrated expertise in specific technical areas, with significant experience in related fields.Provide direction, mentoring, and leadership to small to medium-sized teams.Strong communication and leadership skills are necessary for effective collaboration with program stakeholders. Contact:UdayMulya Technologiesmuday_bhaskar@yahoo.com"Mining The Knowledge Community"

Our vision is to transform how the world uses information to enrich life for all. Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. CAD Staff Engineer Micron Technology, Inc., is a leading semiconductor company dedicated to pushing the boundaries of innovation. Our vision is to transform how the world uses information to enrich life. Join an inclusive team focused on one thing: using their expertise in the relentless pursuit of innovation for customers and partners. The solutions we create helps make everything from virtual reality experiences to breakthroughs in neural networks possible. We do it all while contributing to integrity, sustainability, and giving back to our communities. Because doing so can spark the very innovation we are pursuing. Job Description We are seeking a talented CAD Staff engineer specialized in analog and digital simulations to join our high-achieving engineering team. As a CAD staff engineer, you will play a pivotal role in optimizing and simulating complex analog and digital circuits, contributing to the development of state-of-the-art products that shape our industry. You will get a chance to develop the industry's first and unique flows to enhance productivity and reduce pre-silicon failures. Responsibilities And Tasks Include, But Not Limited To Work closely with memory design teams and solve their daily challenges and provide complete solutions for the future.Proactively identify problem areas for improvement, propose, and develop innovative solutions.Develop highly scalable, and clean software systems.Continuously evaluate and implement new tools and technologies to improve the current software flows.Work with EDA vendors to evaluate and integrate EDA tools in CAD flows.Provide technical leadership and guidance to junior engineers, fostering their professional growth and development. Knowledge, Skills, And Experience 8+ years of progressive experience in analog or digital circuit simulation flows.Expert in circuit simulation debugging with required knowledge of leading-edge circuit design and simulation methodologies.Hands on experience with one of the circuit simulators (Finesim/Primesim/XA/Spectre/VCS/Xcelium etc.)Hands-on experience with Cadence custom IC Virtuoso platform, Virtuoso-L, and Virtuoso-XL, schematic capture, or Synopsys custom compiler or equivalent.Hands on with Python/Perl Object Oriented Programming.Good understanding of CMOS concepts and electronic fundamentals.Knowledge of Linux, LSF, shell scripting, TCL scripting, SKILL(Cadence) language.Knowledge of parasitic extraction tools like StarRC/Quantus will be an added advantage.Excellent problem-solving skills with the ability to troubleshoot complex circuit issues effectively.Proficiency in working effectively with global teams and stakeholders.Experience in EM/IR & STA (Static Timing Analysis) will be an added advantage.Experience in AI/ML will be an added advantage. Education Bachelor’s/master’s degree in Electronics/Electrical/Computer engineering or related fields. About Micron Technology, Inc. We are an industry leader in innovative memory and storage solutions transforming how the world uses information to enrich life for all. With a relentless focus on our customers, technology leadership, and manufacturing and operational excellence, Micron delivers a rich portfolio of high-performance DRAM, NAND, and NOR memory and storage products through our Micron® and Crucial® brands. Every day, the innovations that our people create fuel the data economy, enabling advances in artificial intelligence and 5G applications that unleash opportunities — from the data center to the intelligent edge and across the client and mobile user experience. To learn more, please visit micron.com/careers All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, veteran or disability status. To request assistance with the application process and/or for reasonable accommodations, please contact hrsupport_india@micron.com Micron Prohibits the use of child labor and complies with all applicable laws, rules, regulations, and other international and industry labor standards. Micron does not charge candidates any recruitment fees or unlawfully collect any other payment from candidates as consideration for their employment with Micron.

We Are: At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation. You Are: You are a seasoned professional with a passion for cutting-edge technology and innovation. With 8-12 years of experience, you bring a wealth of knowledge in CMOS memory design and circuit implementation. Your expertise lies in developing non-volatile memories or SRAM. You are proficient in schematic entry, circuit simulation, layout planning, and design verification. You thrive in a collaborative environment, interfacing with CAD and Frontend engineers to drive memory compiler automation and EDA model generation. Your attention to detail ensures the highest quality in circuit and physical layout design. Self-motivated and self-directed, you demonstrate excellent analytical and problem-solving skills. You are adept at programming in C-Shell or Perl. Your strong command of English, both verbal and written, enables you to communicate effectively with team members and stakeholders. You are committed to continuous learning and professional growth, and you bring professionalism, critical thinking, and a focus on future goals to your work. Inclusion and diversity are important to you, and you contribute to a collaborative and inclusive work environment. What You’ll Be Doing: Develop CMOS embedded non-volatile memories such as MRAM and RRAM. Design architecture and circuit implementation, focusing on high speed, low power, and high-density designs. Perform schematic entry, circuit simulation, layout planning, layout supervision, design verification, and validation. Interface with CAD and Frontend engineers for memory compiler automation, EDA model generation, and full verification flow. Perform design verification and drive physical layout design and verification. Provide support and/or perform other duties as assigned and required. The Impact You Will Have: Contribute to the development of high-performance silicon chips and software content. Enhance the efficiency and performance of our CMOS non-volatile memory designs. Drive innovation in high speed, low power, and high density memory designs. Ensure the highest quality in circuit development and physical layout design. Collaborate effectively with CAD and Frontend engineers to streamline automation and verification processes. Support the continuous improvement and advancement of our memory design technology. What You’ll Need: Bachelor’s or Master’s degree in Electrical Engineering, Telecommunication, or related fields. Proficiency in CMOS memory design (NVM or SRAM), circuit simulation, memory layout designs, layout parasitic extraction, and layout verification tools and debugging techniques. Basic circuit know-how of Charge Pump, Voltage Regulator, Current Mirror, Reference voltage and current, Comparators preferred Programming capability in C-Shell or Perl Strong analytical and problem-solving skills with attention to detail. Experience in developing documents, reports, or presentations for a range of tasks. Who You Are: Self-motivated, self-directed, detail-oriented, and well-organized. Possess excellent analytical, problem-solving, and negotiation skills. Capable of leading and mentoring trainees and junior engineers, as well as managing projects. Strong command of English, both verbal and written. Exhibit strong interpersonal communication and teamwork skills. Professional, critical/logical thinker, and focused on future goals. Highly committed to continuous learning and professional development. The Team You’ll Be A Part Of: You will be a key member of our innovative R&D Engineering team, focused on developing cutting-edge CMOS embedded non-volatile memories (MRAM/RRAM). Our team thrives on collaboration and continuous improvement, working together to achieve technological advancements that shape the future. You will have the opportunity to lead and mentor junior engineers, contributing to a culture of learning and excellence. Rewards and Benefits: We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.

We Are: At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation. You Are: As an ideal candidate for the ASIC Digital Design Engineer, Senior role, you are a highly motivated and innovative individual with a deep understanding of ASIC development flow. You are someone who thrives in dynamic environments and embraces the challenges that come with constant technological changes. You are self-motivated, proactive, and able to balance good design quality with tight deadlines. Your excellent communication skills enable you to interact seamlessly with different design groups and customer support teams. You are known for your ability to resolve issues creatively and exercise independent judgment in selecting methods and techniques to obtain solutions. You are a team player who can produce excellent results both as an individual and as part of a team. What You’ll Be Doing: Supporting development and verification of ASIC digital designs for next-generation NRZ and PAM-based SerDes products.Setting up and running lint/cdc/rdc checks using VC-Spyglass and synthesis flow using Design Compiler/Fusion Compiler.Working with Verilog and VCS to ensure design accuracy.Defining synthesis design constraints and resolving STA issues.Setting up and running FPGA prototyping flows to map RTL designs to Xilinx FPGAs. The Impact You Will Have: Contributing to the development of cutting-edge SerDes products that lead the industry.Enhancing the performance, power, and size efficiency of our silicon IP offerings.Enabling rapid market entry for differentiated products with reduced risk.Driving innovation in high-speed digital design and data recovery circuits.Supporting the creation of high-performance silicon chips and software content.Collaborating with a world-class team to solve complex design challenges. What You’ll Need: BSEE or MSEE with a minimum of 2 years of experience in digital design and front-end flows.Proficiency in running lint/cdc/rdc checks and synthesis flow.Experience in coding, verifying Verilog and System Verilog design.Experience of working with minimum supervision and owning and delivering for front-end activities in IP/SOC.Experience of leading technically for front-end activities.Knowledge of digital design methodologies, DFT insertion, synthesis constraints, and flows.Scripting experience in Shell, Perl, Python, and TCL (preferred). Who You Are: Excellent communicator with the ability to interact with diverse teams.Self-motivated and proactive, with a strong attention to detail.A creative problem-solver who can think independently.Capable of working under tight deadlines while maintaining high-quality standards.A team player who can contribute effectively both individually and collaboratively. The Team You’ll Be A Part Of: Join our highly experienced mixed-signal design and verification team, where you will work alongside experts in digital and mixed-signal engineering. Our team is dedicated to developing innovative solutions for the next generation of high-speed SerDes products, providing continuous training and opportunities for growth. Rewards and Benefits: We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.