Senior Manager, Compact Modeling Micron Technology

15.0 - 20.0 years

17 - 22 Lacs

Hyderabad

Work from Office

As a Senior Manager for the Compact Modeling team, you will lead a high-impact team responsible for the development and delivery of compact models that enable next-generation NAND and DRAM technologies. A key part of this role is to foster a culture of technical excellence, collaboration, and continuous learning. You will be expected to mentor and grow technical talent, promote best practices, and create an environment where engineers are empowered to innovate and deliver high-quality modeling solutions. This position requires deep technical expertise, cross-functional collaboration, and a strong focus on model accuracy, predictability, and integration into design workflows. Key Responsibilities: Lead a team of engineers in the development, validation, and delivery of compact models across CMOS, interconnect, array, and reliability domains. Own and guide the complete model development lifecycle, including extraction, extrapolation, verification, and documentation. Collaborate closely with CAD, Process Integration, Design Engineering, Product Engineering, and Quality Assurance to ensure models meet performance and design enablement goals. Oversee the design and verification of test structures to support robust model development. Analyze DC and AC device data and direct advanced characterization efforts as needed to support model accuracy. Communicate model performance metrics and predictive insights to global design teams and technical leadership. Drive methodology innovation and continuous improvement in modeling workflows and tool integration. Mentor and develop technical talent, fostering a team culture centered on ownership, collaboration, and technical growth. This position will be based out of Micron's Hyderabad site. Qualifications: Masters or PhD in Electrical Engineering, Physics, or a related field. 15+ years of relevant experience in the semiconductor industry, with a strong focus on compact modeling. Proven experience in: Compact model development using tools such as BSIMPro+, IC-CAP, MBP, or equivalent. Model verification and validation through circuit simulation and data correlation. Test structure definition and validation. Delivering compact modeling collaterals as part of PDKs or design enablement flows. Strong understanding of CMOS device physics and modeling principles. Hands-on experience with wafer-level device characterization. Familiarity with PDK development, circuit simulators, and design environments. Demonstrated ability to mentor or manage technical teams. Experience in analog or memory circuit design is a plus.

Posted 3 weeks ago

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MTS - NAND Design Enablement Micron

10.0 - 12.0 years

0 Lacs

Hyderabad / Secunderabad, Telangana, Telangana, India

On-site

Our vision is to transform how the world uses information to enrich life for . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. As a MTS - NAND Design Enablement in Process Integration, primary responsibility is to drive and contribute to next generation 3D NAND development efforts. You will be working with several peer groups to define, complete, and coordinate effective actions to enable a node and shepherd it to production. Responsibilities include but are not limited to the following: Drive vertical integration with a network of collaborators varying from Business Units, Pathfinding, Design, Device, Process, Integration, Reliability, Product Engineering, Probe, Test, Assembly, mask tech, etc. Drive node health tracking, communication and documentation of key achievements delivery starting from project kick off till product qual. Ensure all node enabling teams have responsible owner for each node Collaborate with responsible owner to populate crystal clear specifications in the database Publish score cards of work from accountable owner in the health report Create timeline charts to provide clear visibility of project timelines and relative dependencies across node enabling teams Champion test structure definition for all designs within a node starting from test chip to final production design Aim for high quality proliferation of test structures from test chip to product designs. Responsible for requesting TCAD, structure, OPC, electrical and Reliability simulations Ensure all test structures are validated on silicon and are readily available for product debug Qualifications: Minimum of 10+ years of experience in semiconductor industry in the areas Process Integration, Device Engineering, Compact Modeling, Product Engineering, Test Structure Development, or Unit Process Development Project management experience with a highly collaborative personality Proven track record of coordinating high level roll up meetings Proven track record to think and communicate clearly in urgent and stressful situations In depth understanding of the 3D NAND process flow is a plus

Posted 1 month ago

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