7 Cmos Technology Jobs

As a NAND CMOS Device Engineer at Micron Technology, you will play a crucial role in shaping the current and future CMOS technology for Micron's NAND Memory Technology Roadmap. You will collaborate with various teams like Design, Process Integration, Design Engineering, and more to ensure the developed technology is manufacturable, highly yielding, and aligns with product roadmaps. Your responsibilities will include defining electrical targets, guiding device technology development, analyzing silicon experiments, and optimizing critical layout constrained Design Rules. Additionally, you will be instrumental in developing strategies for transistor structures to meet targets and ensuring that ...

As an ASIC Design Manager at MaxLinear, you will be part of the Digital ASIC Design group responsible for developing innovative ASIC solutions across various domains such as wired and wireless communications, storage, and networking. Your role will involve managing, mentoring, and guiding a high-performance team in architecting and designing advanced digital components like signal processing modules, network processors, hardware accelerators, and interface controllers. Your key responsibilities will include: - Leading and mentoring a team of digital ASIC designers across multiple projects and domains - Driving architecture and micro-architecture definition for complex digital blocks - Overse...

Job Description: As a Qualcomm Hardware Engineer at Qualcomm India Private Limited, you will be involved in planning, designing, optimizing, verifying, and testing electronic systems, circuits, mechanical systems, and various other cutting-edge technologies to launch world-class products. Your role will require collaboration with cross-functional teams to develop solutions and meet performance requirements. Key Responsibilities: - Demonstrating good knowledge of CMOS technology and physical design concepts such as flooplanning, place and route, clock tree synthesis (CTS), physical verification, and static timing analysis (STA). - Taking responsibility for developing CAD tool/flow solutions w...

As a Physical Design Engineer at UST, you will be responsible for the following: - Expected to be very good in Basic Fundamentals of C-MOS technology - Able to handle RTL/Netlist to GDSII independently at block level and should have done multiple tape outs (Low power implementation is preferred) - Hands-on experience of working on Lower technology nodes like 5nm, 7nm, 10nm, 14nm, 16nm, 28nm etc. - Proficient in floor planning, placement optimizations, clock tree synthesis (CTS), and routing - Experienced in block/top level signoff Static Timing Analysis (STA), physical verification (DRC/LVS/ERC/antenna) checks, and other reliability checks (IR/EM/Xtalk) - Expertise in industry standard EDA t...

Responsibilities MaxLinear is seeking an ASIC Design Manager to join our Digital ASIC Design group. Our team develops innovative ASIC solutions across domains such as wired and wireless communications, storage, and networking. In this leadership role, you will manage, mentor and guide a high-performance team responsible for architecting and designing advanced digital components including signal processing modules, network processors, hardware accelerators and interface controllers. In this role, you will focus on: Lead and mentor a team of digital ASIC designers across multiple projects and domains Drive architecture and micro-architecture definition for complex digital blocks Oversee RTL de...

The development of product gradeStandardCellIP covering the following phases: Layout Design ofStandard CellIPs Layout checks likeLVS, DRC,DFM, EMIR Review of Layouts and extend help for other Layout teams Design Kit prep from layout side,verificationand validation Layout automation and script support Being a goodteam player,taking key initiatives for productivity improvements and innovation Sign off and release into dedicated IP validation test chips Specification and documentation Support ofsiliconbring up and characterization Required Qualifications: Bachelor s degree with10+years or master s degree with8+years experience in semiconductors / Microelectronics / VLSI engineering. Practical e...

You will be integrated into the Foundry IP Development team in Bangalore at GLOBALFOUNDRIES. Collaborating closely with various engineering teams worldwide, you will be responsible for developing layout for Standard Cell IPs to facilitate high-quality product designs based on Globalfoundries" advanced process nodes. Your main responsibilities will include: - Designing layout for Standard Cell IPs - Performing layout checks such as LVS, DRC, DFM, EMIR - Reviewing layouts and assisting other layout teams - Preparing design kits from the layout side, along with verification and validation - Providing support for layout automation and scripting - Taking initiatives for productivity improvements ...