86 Cmos Jobs - Page 3

About The Role Designs, develops, and builds digital circuits for custom blocks including SRAM, register files, memory compilers, and caches. Designs floorplans, performs circuit design, schematic entry, simulation for major blocks, and verifies functionality to optimize custom circuit for power, performance, area, timing, and yield goals. Creates block level DFT models, develops memory test tools, and improves and automates flows and methodologies to ensure streamlining of design. Collaborates cross functionally to report design progress and to collect, track, and resolve any performance and memory circuit design issues. Optimizes performance, power, and area, reduce leakage of circuits, and drive characterization of individual memory instances and memory compilers. Works with architecture and layout teams to design circuit for best functionality, robustness, and electrical capabilities. Qualifications The candidate must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates. Minimum qualifications Must have a Bachelors (B.Tech) in Electronics or Masters (M.Tech) in Electrical, Microelectronics or VLSI Engineering. B.Tech with 8+ years and M. Tech with 6+ years' experience required. 6+ years' experience with scripting (Perl, tcl etc. 6+ years' experience in memory design convergence tools including formal equivalence verification, static timing methodology, electrical reliability and robustness analysis. 6+ years' experience with transistor level operation, memory bitcell design, design challenges under process variations and low power circuit techniques, Innovative architectural proposals, driving layouts and its driven decisions. Preferred Qualifications Some experience in scripting, compiler understanding and hands on experience in coding tilers. Inside this Business Group As the world's largest chip manufacturer, Intel strives to make every facet of semiconductor manufacturing state-of-the-art -- from semiconductor process development and manufacturing, through yield improvement to packaging, final test and optimization, and world class Supply Chain and facilities support. Employees in theTechnology Development and Manufacturing Groupare part of a worldwide network of design, development, manufacturing, and assembly/test facilities, all focused on utilizing the power of Moore's Law to bring smart, connected devices to every person on Earth.

We are seeking an Analog Layout Engineer 3-8 for designing PMIC, converters, high-speed clocking circuits, and analog modules in FinFET, CMOS, and BiCMOS/BCD technologies Strong skills in layout, parasitic extraction, and verification tools required. Perks and benefits Competitive Salary Referral program Insurance

Job Specs : We are seeking a highly skilled and motivated Analog Circuit Designer to join the offshore development teams of our group companies. You will work with the rapidly expanding team which focuses on the research and development of Analog / Mixed Signal IPs for Silicon Lifecycle Management, driving innovation and excellence in chip design and verification. You will work alongside a talented and dedicated group of engineers, all committed to pushing the boundaries of technology and delivering top-notch solutions to our customers. Desired Profile : - Bachelor's / Master's degree in engineering from EEE / E&C with 4+ Years of work expertise in mixed-signal or CMOS circuit design- Expertise in analog blocks like power management DC-DC convertor, LDOs or- Expertise in designing ADC / DAC/ PLLs or Experience in simulation or characterization of IO cells- Design and architect CMOS analog and mixed-signal integrated circuits- Simulate designs with state-of-the-art CAD tools- Document designs and simulation results - Experience with high-speed SERDES circuits- Knowledge of layout issues- Experience with circuit simulators (HSPICE, Spectre, etc)- Experience with Cadence Design Environment is an asset- Working knowledge of PERL and UNIX shell scripting languages is an asset Work Location : Bangalore / Hubli / Kolkata / Moscow / SFO Work Expertise : 4 - 10 years Rewards and Benefits : We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process. NOTE : Preferred resources holding valid regional s only Location - Bangalore,Kolkata,US,Others

About Us Unitedlex India Pvt. Ltd. (Formerly known as iRunway India Pvt Ltd) is a data and professional services company delivering outcomes for high-performing law firms and corporate legal departments in the areas of digital litigation, intellectual property, contracts, compliance, and legal operations. Founded in 2006 with a mission to push the boundaries of legal innovation, we provide solutions that enable measurable performance improvement, risk mitigation, revenue gain, cost reduction, and digital business synergy. Job location: Gurgaon or Bangalore Shift timing: 10:30 AM 7:30 PM Work Mode: Work from Office Must have/Eligibility criteria BE/ME in Electrical or Electronics or related technical field. Masters degree preferred At least 6 years of relevant experience in semiconductor product development. First-hand knowledge in System Design and/or Packaging Experience. First-hand knowledge of semiconductor manufacturing processes (design, process, fabrication, assembly, testing). Candidate should demonstrate interpersonal communication (including verbal and written communication), creative problem solving, time management, and team building skills. we look for a person who is curious enough to take a deep dive into a new and latest technology to explore anything anytime. Good to have/key differentiators (expertise in any of the following fields)- Expertise in Semiconductor packaging Expertise in semiconductor process and fabrication Expertise in designing any high-speed IO and SERDES architecture Experience in analog circuits including power management circuits such as converters, regulators; clock generators such as Crystal Oscillator, RC Oscillator, PLL, clock buffers and dividers, etc. Have good knowledge on The JEDEC memory specifications for semiconductor memory circuits and similar storage devices. Do you have any PCB or card or module layout experience? What layout tools have you use if any? (Example: Cadence, Mentor Graphics, OrCAD) Any Previous work experience with CMOS image sensors. Please refer to our Privacy Policy at UnitedLex for information, https://unitedlex.com/privacy-policy

Role and Responsibilities Responsible for Design and development of critical analog, mixed-signal, custom digital block and full chip level integration support. Highly motivated with passion, detail oriented, systematic and methodical approach in IC layout design Perform layout verification like LVS/DRC/Antenna, quality check and documentation. Responsible for on-time delivery of block-level layouts with acceptable quality. Demonstrate leadership Skill in planning, area/time estimation, scheduling, delegation and execution to meet project schedule/milestones in multiple project environment. Guide junior team-members in their execution of Sub block-level layouts & review their work Contribute to effective project-management. Effectively communicating with Global engineering teams to assure the success of layout project. Qualification/Requirements 8 to 15 years' experience in analog/custom layout design in advanced CMOS process, in various technology nodes (Planar, FinFET ) Expertise in Cadence VLE/VXL and Mentor Graphic Calibre DRC/LVS is a must. Should have hands on experience in creating layout of critical blocks such as Temperature sensor, PLL, ADC, DAC, LDO, Bandgap, Ref Generators, Charge Pump, Current Mirrors, Comparator, Differential Amplifier etc., Good understanding of Analog Layout fundamentals (e.g., Matching, Electro-migration, Latch-up, coupling, crosstalk, IR-drop, active and passive parasitic devices etc.) Understanding layout effects on the circuit such as speed, capacitance, power and area etc., Ability to understand design constraints and implement high-quality layouts. Ability to understand design hierarchy and different architectures for Memory designs. Excellent command and problem-solving skills in physical verification of custom layout. Multiple Tape out support experience will be an added advantage. Experience in managing multiple layout projects, ensuring quality checks are taken care at all stages of layout development. Excellent verbal and written communication skills. Education BE or MTech in Electronic/VLSI Engineering All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, veteran or disability status.

Job Area: Engineering Services Group, Engineering Services Group > Layout Engineer General Summary: Develops block, macro, or chip level layouts and floorplans according to project requirements, specifications, and design schematics. Applies understanding of design manuals, established processes, layout elements, and basic electronic principles to create accurate designs that meet project needs. Conducts analyses, tests, and verifies designs using different tools and techniques to identify and troubleshoot issues, and stays abreast of new verification methods. Works with multiple internal and external stakeholders to align on projects, provide updates, and resolve issues. Minimum Qualifications: Bachelor's degree in Electrical Engineering, Computer Science, Mathematics, Electronic Engineering, or related field and 2+ years of experience designing custom layouts in relevant domain (e.g., analog, mixed signal, RF, digital design), or related work experience. OR Associate's degree in Computer Science, Mathematics, Electrical Engineering or related field and 4+ years of experience designing custom layouts in relevant domain (e.g., analog, mixed signal, RF, digital design), or related work experience. OR High School diploma or equivalent and 6+ years of experience designing custom layouts in relevant domain (e.g., analog, mixed signal, RF, digital design), or related work experience. 2+ years of experience using layout design and verification tools (e.g., cadence, LVS, rmap). Solid experience of 3 to 6 years in developing high speed IO/ESD/Analog layout design. Expertise in working on FinFet layouts in lower nodes, preference to TSMCN 7nm and below. Expertise in using the best and latest features of Cadence VXL and Calibre DRC/LVS. Basic understanding of IO/ESD designs. Knowledge on Basic SKILL/PERL. Capable of working independently and with team and getting work done with contract work force. The ability to work & communicate effectively with global engineering teams.

About The Role : Works in the area of Software Engineering, which encompasses the development, maintenance and optimization of software solutions/applications. 1. Applies scientific methods to analyse and solve software engineering problems. 2. He/she is responsible for the development and application of software engineering practice and knowledge, in research, design, development and maintenance. 3. His/her work requires the exercise of original thought and judgement and the ability to supervise the technical and administrative work of other software engineers. 4. The software engineer builds skills and expertise of his/her software engineering discipline to reach standard software engineer skills expectations for the applicable role, as defined in Professional Communities. 5. The software engineer collaborates and acts as team player with other software engineers and stakeholders. Works in the area of Software Engineering, which encompasses the development, maintenance and optimization of software solutions/applications.1. Applies scientific methods to analyse and solve software engineering problems.2. He/she is responsible for the development and application of software engineering practice and knowledge, in research, design, development and maintenance.3. His/her work requires the exercise of original thought and judgement and the ability to supervise the technical and administrative work of other software engineers.4. The software engineer builds skills and expertise of his/her software engineering discipline to reach standard software engineer skills expectations for the applicable role, as defined in Professional Communities.5. The software engineer collaborates and acts as team player with other software engineers and stakeholders. About The Role : - Grade Specific Has more than a year of relevant work experience. Solid understanding of programming concepts, software design and software development principles. Consistently works to direction with minimal supervision, producing accurate and reliable results. Individuals are expected to be able to work on a range of tasks and problems, demonstrating their ability to apply their skills and knowledge. Organises own time to deliver against tasks set by others with a mid term horizon. Works co-operatively with others to achieve team goals and has a direct and positive impact on project performance and make decisions based on their understanding of the situation, not just the rules. Skills (competencies) Verbal Communication

In your new role you will: Define the overall chip architecture of our Automotive Microcontroller based on platform definitions Understand specific architectural requirements for power, cost &performance and define feasible implementation requirements Guide our teams how to fulfill these requirements Cooperate closely with other expert groups from various fields suchas platform definition, implementation and verification Report regularly to stakeholders, project managers as well asdepartment heads in an open, clear and active way Identify opportunities for efficiency improvements and cost reduction Act as coach and role model for other team members and support themto develop You are best equipped for this task if you have: At least 5 years of relevant work experience in microchiparchitecture, digital chip design or verification, preferably in powerrelated topics Knowledge about automotive microcontrollers Knowledge about state-of-the-art highly scaled digital SoCs based onthe latest CMOS technologies Understanding of system-level dependencies; understanding ofinteroperability with external components is a plus Automotive application domain knowledge is a plus Working experience in international and cross-functional technicalteams within a multi-cultural environment Fluent communication skills in English - with German (or thewillingness to learn) being an added plus

Role & responsibilities : * Pre-Silicon Support: Simulate, analyze, and debug pre-silicon full-chip designs to ensure functional accuracy. * Test Case Development: Develop stimulus and test cases to increase the functional coverage for DRAM, SRAM, and other emerging memory technologies. Core Requirements: * Strong Communication Skills: Ability to collaborate effectively within a team. * Leadership: Guide new team members and engineers, sharing your knowledge and experience. * Analytical Expertise: Deep understanding of complex CMOS and/or gate-level circuit designs. * Proficiency in SPICE and/or Verilog simulations. Preferred candidate profile : Required Skills: * Experience with SystemVerilog, PLI coding, and UVM Test Benches. * Expertise in DRAM, SRAM, or other memory-related fields. * Familiarity with AMS verification and co-simulation is a plus. * Experience with Ethernet, SATA, Perl Scripts, and Debugging is helpful. * Knowledge of full-chip DDR, gate-level simulation, and SPICE simulation is optional but advantageous. Perks and benefits : Flexible Working Hours , Transport facility, Competitive Salary

Job Opportunity: Technical Editor We are currently seeking a highly skilled and detail-oriented Technical Editor to join our team. The ideal candidate will meet the following qualifications: Education: Must hold a degree. Experience: A minimum of 2 years of experience as a technical editor, with expertise in both journals and books, preferably with a focus on books. Expertise in Style Manuals: In-depth knowledge of style manuals such as AMA (American Medical Association), APA (American Psychological Association), and CMoS (Chicago Manual of Style). Endnote Editing: Proven experience in editing endnotes in accordance with CMoS style. Proficient in MS Office: Strong working knowledge of MS Office Suite. Skills: Strong analytical and problem-solving abilities, with a keen eye for detail. If you have a passion for precision and enjoy working with the complex technical content, we would love to hear from you! We are seeking a highly motivated and enthusiastic Entry-Level Trainee/Shadow Salesperson with a strong digital marketing and social media background to join our growing team. This role will provide an excellent opportunity to learn the ropes of sales within the publishing and IT training sectors by shadowing experienced sales professionals, while also contributing to lead generation through digital channels. The ideal candidate will be a quick learner, possess excellent communication skills, and have a passion for building relationships. Responsibilities: Lead Generation (Digital Focus): Develop and execute digital marketing strategies to generate qualified leads. This includes: o Managing and optimizing social media platforms (LinkedIn, Twitter, etc.) o Creating engaging content for social media and other online channels. o Utilizing SEO best practices to improve online visibility. o Running targeted online advertising campaigns. o Tracking and analysing campaign performance and making data-driven adjustments. Market Research: Conduct market research to identify potential clients and understand their needs. CRM Management: Maintain accurate records of leads and client interactions within the company's CRM system. Sales Support: Assist the sales team with administrative tasks, such as preparing proposals, presentations, and other sales materials. Networking: Attend industry events and networking opportunities to build relationships with potential clients. Reporting: Regularly report on lead generation activities and sales progress. Qualifications: Bachelor's degree in Marketing, Business, or a related field preferred. Proven experience in digital marketing and social media marketing (portfolio or examples required). Strong understanding of social media platforms, analytics, and advertising. Excellent written and verbal communication skills. Ability to learn quickly and adapt to new situations. Strong organizational and time-management skills. Proficiency in Microsoft Office Suite (Word, Excel, PowerPoint). Experience with CRM software is a plus. Interest in the publishing and/or IT training industries is a plus.

About The Role : Works in the area of Software Engineering, which encompasses the development, maintenance and optimization of software solutions/applications. 1. Applies scientific methods to analyse and solve software engineering problems. 2. He/she is responsible for the development and application of software engineering practice and knowledge, in research, design, development and maintenance. 3. His/her work requires the exercise of original thought and judgement and the ability to supervise the technical and administrative work of other software engineers. 4. The software engineer builds skills and expertise of his/her software engineering discipline to reach standard software engineer skills expectations for the applicable role, as defined in Professional Communities. 5. The software engineer collaborates and acts as team player with other software engineers and stakeholders. Works in the area of Software Engineering, which encompasses the development, maintenance and optimization of software solutions/applications.1. Applies scientific methods to analyse and solve software engineering problems.2. He/she is responsible for the development and application of software engineering practice and knowledge, in research, design, development and maintenance.3. His/her work requires the exercise of original thought and judgement and the ability to supervise the technical and administrative work of other software engineers.4. The software engineer builds skills and expertise of his/her software engineering discipline to reach standard software engineer skills expectations for the applicable role, as defined in Professional Communities.5. The software engineer collaborates and acts as team player with other software engineers and stakeholders. About The Role : - Grade Specific Is fully competent in it's own area and has a deep understanding of related programming concepts software design and software development principles. Works autonomously with minimal supervision. Able to act as a key contributor in a complex environment, lead the activities of a team for software design and software development. Acts proactively to understand internal/external client needs and offers advice even when not asked. Able to assess and adapt to project issues, formulate innovative solutions, work under pressure and drive team to succeed against its technical and commercial goals. Aware of profitability needs and may manage costs for specific project/work area. Explains difficult concepts to a variety of audiences to ensure meaning is understood. Motivates other team members and creates informal networks with key contacts outside own area. Skills (competencies) Verbal Communication

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field. 2-4 yrs experience in Physical Design and timing signoff for high speed cores. Should have good exposure to high frequency design convergence for physical design with PPA targets and PDN methodology. Masters/Bachelors Degree in Electrical/Electronics science engineering with at least 7+ years of experience in IC design. Experience in leading block level or chip level Physical Design, STA and PDN activities. Work independently in the areas of RTL to GDSII implementation. Ability to collaborate and resolve issues wrt constraints validation, verification, STA, Physical design, etc. Knowledge of low power flow (power gating, multi-Vt flow, power supply management etc.) Circuit level comprehension of time critical paths in the design Understanding of deep sub-micron design problems and solutions (leakage power, signal integrity, DFM etc.) Tcl/Perl scripting Willing to handle technical deliveries with a small team of engineers. Strong problem-solving skills. Applicants : Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries). Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law. To all Staffing and Recruiting Agencies : Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications. If you would like more information about this role, please contact Qualcomm Careers.

The successful candidate will have the foundation to develop technical semiconductor knowledge. This role is essential for enabling high quality devices while minimizing time to market of Micron products supporting Technology Development and Manufacturing. Interested candidates should be comfortable working a non-standard work week(For Example, Friday through Thursday) to help Micron improve our speed of development and response times to the needs of our Manufacturing and R&D Fabrication Facilities Responsibilities include, but are not limited to the following: Develop Design Rule Checks through automated verification processes Innovate new approaches for design layout and data process verifications Understand design layout and processes of mask development Ensure visibility and communication to groups responsible for the mask development processes Document and report issues to related groups Drive problems to resolution; identify and manage risks Facilitate effective meetings with key stakeholders Successful candidates for this position will have: Skills in CAD layout Proficient in coding utilizing Python, Perl, or PerlTK Familiarity with Cadence SKILL Proven track record working with people Strong troubleshooting and problem-solving skills The ability to multi-task with strong project organizational skills Layout viewer (i.e. K2View) experience; DF2 database layout experience is ideal Basic understanding of semiconductor manufacturing technologies (basic CMOS understanding is desirable) Basic understanding of lithography and photo masks Experience working with off-shore teams (US and Japan desirable) Strong verbal and written ability in English Education: Bachelor's or Master's in EE or related science discipline

Works in the area of Software Engineering, which encompasses the development, maintenance and optimization of software solutions/applications. 1. Applies scientific methods to analyse and solve software engineering problems. 2. He/she is responsible for the development and application of software engineering practice and knowledge, in research, design, development and maintenance. 3. His/her work requires the exercise of original thought and judgement and the ability to supervise the technical and administrative work of other software engineers. 4. The software engineer builds skills and expertise of his/her software engineering discipline to reach standard software engineer skills expectations for the applicable role, as defined in Professional Communities. 5. The software engineer collaborates and acts as team player with other software engineers and stakeholders. Job Description - Grade Specific Is highly respected, experienced and trusted. Masters all phases of the software development lifecycle and applies innovation and industrialization. Shows a clear dedication and commitment to business objectives and responsibilities and to the group as a whole. Operates with no supervision in highly complex environments and takes responsibility for a substantial aspect of Capgeminis activity. Is able to manage difficult and complex situations calmly and professionally. Considers the bigger picture when making decisions and demonstrates a clear understanding of commercial and negotiating principles in less-easy situations. Focuses on developing long term partnerships with clients. Demonstrates leadership that balances business, technical and people objectives. Plays a significant part in the recruitment and development of people. Skills (competencies) Verbal Communication

About The Role : As an IP Structural Design Engineer, you will be working alongside Elite IP and SoC design teams to deliver next-generation Xeon products and related IPs for Server markets. We are looking for candidates with experience as physical design engineers as part of the Structural Design Expert Team in the IP organization. You will be fluent in all aspects of IP physical design flow from high-level block design to synthesis, place and route and timing and power convergence to build a design database that is ready for manufacturing. Your responsibilities will include all aspects of RTL2GDSII physical design flow convergence including but not be limited to:Oversees definition, design, verification, and documentation for SoC (System on a Chip) development. Block-level floor planning, interconnect planning and UPF based power delivery methodology. Logic synthesis of design blocks using Synopsys Design Compiler DCT- Formal Equivalence Verification FEV using Cadence's Conformal tool. Auto Place-and-Route APR using Synopsys Fusion Compiler tools. Timing and power verification using Synopsys PrimeTime as well as Intel tools. Layout Verification and DRC analysis. What we offer:We give you opportunities to transform technology and create a better future, by delivering products that touch the lives of every person on earth. As a global leader in innovation and new technology, we foster a collaborative, supportive, and exciting environment where the brightest minds in the world come together to achieve exceptional results. We offer a competitive salary and financial benefits such as bonuses, life and disability insurance, opportunities to buy Intel stock at a discounted rate, and Intel stock awards (eligibility at the discretion of Intel Corporation). We provide benefits that promote a healthy, enjoyable life:excellent medical plans, wellness programs, and amenities, time off, recreational activities, discounts on various products and services, and much more creative perks that make Intel a Great Place to Work. We're constantly working on making a more connected and intelligent future, and we need your help. Change tomorrow. Start today. Qualifications You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates. Experience would be obtained through a combination of prior education level classes, and current level school classes, projects, research, and relevant previous job and internship experience. Minimum Qualifications: Candidate must have a Bachelor's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field with 7+ years of experience. OR Master's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field with 5+ years of experience. OR PhD in Electrical Engineering, Computer Engineering, Computer Science, or related field with 3+ years of experience in:CMOS circuit design, and layout verification. Industry standard CAD tools/flows for digital and/or analog design. Preferred Qualifications: Experience in:Fusion Compiler/Primetime Process and Design co-optimization for Density/Performance improvements RTL based power estimation and optimization. Experience in CPU/ASIC design methodology and flow development, particularly in the RLS, Structural Design, APR and low power optimization domains. Unix skills, programming skills in TCL, Perl Script and shell scripting. Good understanding of overall CPU/SOC design cycle and requirements. Willing to multi-task and flexibility to work in a global environment. Good communication skills and have self-motivation. Good analytical and Problem solving skills. Experience in working on high frequency designs and methodologies. Experience in leading small teams to design IPs. Inside this Business Group The Data Center & Artificial Intelligence Group (DCAI) is at the heart of Intel's transformation from a PC company to a company that runs the cloud and billions of smart, connected computing devices. The data center is the underpinning for every data-driven service, from artificial intelligence to 5G to high-performance computing, and DCG delivers the products and technologies"”spanning software, processors, storage, I/O, and networking solutions"”that fuel cloud, communications, enterprise, and government data centers around the world.

About The Role : As an IP Structural Design Engineer, you will be working alongside Elite IP and SoC design teams to deliver next-generation Xeon products and related IPs for Server markets. We are looking for candidates with experience as physical design engineers as part of the Structural Design Expert Team in the IP organization. You will be fluent in all aspects of IP physical design flow from high-level block design to synthesis, place and route and timing and power convergence to build a design database that is ready for manufacturing. Your responsibilities will include all aspects of RTL2GDSII physical design flow convergence including but not be limited to: Oversees definition, design, verification, and documentation for SoC (System on a Chip) development. Block-level floor planning, interconnect planning and UPF based power delivery methodology. Logic synthesis of design blocks using Synopsys Design Compiler DCT- Formal Equivalence Verification FEV using Cadence's Conformal tool & Synopsis Formality tool . Auto Place-and-Route APR using Synopsys Fusion Compiler tools. Timing and power verification using Synopsys PrimeTime as well as Intel tools. Layout Verification and DRC analysis. Behavioral traits that we are looking for:Willing to multi-task and flexibility to work in a global environment. Good communication skills and have self-motivation. Good analytical and Problem solving skills. Experience in leading small teams to design IPs. What we offer:We give you opportunities to transform technology and create a better future, by delivering products that touch the lives of every person on earth. As a global leader in innovation and new technology, we foster a collaborative, supportive, and exciting environment where the brightest minds in the world come together to achieve exceptional results. We offer a competitive salary and financial benefits such as bonuses, life and disability insurance, opportunities to buy Intel stock at a discounted rate, and Intel stock awards (eligibility at the discretion of Intel Corporation). We provide benefits that promote a healthy, enjoyable life:excellent medical plans, wellness programs, and amenities, time off, recreational activities, discounts on various products and services, and much more creative perks that make Intel a Great Place to Work. We're constantly working on making a more connected and intelligent future, and we need your help. Change tomorrow. Start today. Qualifications Minimum Qualifications:Candidate must have a Bachelor's Degree in Electrical Engineering, Computer Engineering, Computer Science, with 4+ years of experience listed below. OR Master's Degree in Electrical Engineering, Computer Engineering, Computer Science, with 2+ years of experience listed below. OR PhD in Electrical Engineering, Computer Engineering, Computer Science, or related field experience in:CMOS circuit design, and layout verification.Industry standard CAD tools/flows for digital and/or analog design.Preferred Qualifications:Experience in Fusion Compiler/Primetime Process and Design co-optimization for Density/Performance improvements RTL based power estimation and optimization.Experience in CPU/ASIC design methodology and flow development, particularly in the RLS, Structural Design, APR and low power optimization domains.Unix skills, programming skills in TCL, Perl Script and shell scripting.Good understanding of overall CPU/SOC design cycle and requirements.Experience in working on high frequency designs and methodologies. Inside this Business Group The Data Center & Artificial Intelligence Group (DCAI) is at the heart of Intel's transformation from a PC company to a company that runs the cloud and billions of smart, connected computing devices. The data center is the underpinning for every data-driven service, from artificial intelligence to 5G to high-performance computing, and DCG delivers the products and technologies"”spanning software, processors, storage, I/O, and networking solutions"”that fuel cloud, communications, enterprise, and government data centers around the world.

Designs, develops, and builds analog circuits in advanced process nodes for analog and mixedsignal IPs. Designs floorplans, performs circuit design, extracts chip parameters, and simulates analog behavior models. Creates test plans to verify design according to circuit and block microarchitecture specifications and evaluates test results. Verifies functionality to optimize circuit for power, performance, area, timing, and yield goals. Collaborates cross functionally to report design progress and collects, tracks, and resolves any performance and circuit design issues. Optimizes performance, power, area, and reduces leakage of circuits. Works with architecture and layout team to design circuit for best functionality, robustness, and electrical capabilities. Qualifications B.Tech / M.Tech/ Phd with with 3+ hands-on experience in high-speed analog circuit design, with a proven track record of successful projects. Expertise in designing and verifying analog circuits such as High-speed transmitter, recevier, amplifiers, PLLs, voltage regulators, and data converters. Proficiency in using EDA tools like Cadence Virtuoso, SPICE, or Synopsys.

About The Role : Experience in Mixed-Signal layout design, holding bachelors degree To work independently on block levels analog layout design from schematic, estimating the Area, Optimizing Floorplan, Routing and Verifications. Firsthand experience in Critical Analog Layout design of blocks such as Temperature sensor, Serdes, PLL, ADC, DAC, LDO, Bandgap, Ref Generators, Charge Pump, Current Mirrors, Comparator, Differential Amplifier etc., Good at LVS/DRC debugging skills and other verifications for lower technology nodes like 14nm FinFet and below. Good understanding of Matching, EM, ESD, Latch-Up, Shielding, Parasitic and short channel concepts. Familiar with EDA tools like Cadence VLE/VXL, PVS, Assura and Calibre DRC/ LVS is a must. Understanding layout effects on the circuit such as speed, capacitance, power and area etc., Ability to understand design constraints and implement high-quality layouts. Multiple Tape out support experience will be an added advantage. Good people skills and critical thinking abilities to resolve the issue technically, and professionally. Excellent communication. Responsible for timely execution with high quality of layout design. Primary Skills Analog Layout Process or technology experience:TSMC 7nm, 5nm, 10nm,28nm, 45nm,40nm EDA Tools: Layout Editor:Cadence Virtuoso L, XL Physical verification:DRC,LVS,Calibre Secondary Skills IO layout

About The Role : The candidate will be expected to perform Development and support for DRC/LVS/PEX/PERC runset(ruledeck) generation on Intel's process. Development/support of ICV/Calibre/Pegasus/PVS runset (rule deck) for DRC/LVS/PEX/PERCConduct the L0QA of the codes. Bring in run time efficiency, automation and solve customer issues on rusets. Develop and maintain DRC/LVS/extraction flow, working closely with various design/development groups. Perform in a dynamic and challenging environment with drive and creativity. Qualifications Candidate needs to have:- B.tech or M.tech with 8+ years of experience in DRC/LVS/PEX/PERC runset development/QA on ICV/Calibre/Pegasus tools/flow.- Strong CMOS concepts- Strong debugging and scripting skills- Strong team working and leadership skills.- Layout tools:Virtuoso, CalibreDRV, IC Work Bench- Runset Development:Calibre, PVS, ICV, Pegasus- Scripting :Unix, Perl, Python or TCL Inside this Business Group As the world's largest chip manufacturer, Intel strives to make every facet of semiconductor manufacturing state-of-the-art -- from semiconductor process development and manufacturing, through yield improvement to packaging, final test and optimization, and world class Supply Chain and facilities support. Employees in theTechnology Development and Manufacturing Groupare part of a worldwide network of design, development, manufacturing, and assembly/test facilities, all focused on utilizing the power of Moore's Law to bring smart, connected devices to every person on Earth.

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field. 3+ yrs experience in Physical Design and timing signoff for high speed cores. Should have good exposure to high frequency design convergence for physical design with PPA targets and PDN methodology. Masters/Bachelors Degree in Electrical/Electronics science engineering with at least 7+ years of experience in IC design. Experience in leading block level or chip level Physical Design, STA and PDN activities. Work independently in the areas of RTL to GDSII implementation. Ability to collaborate and resolve issues wrt constraints validation, verification, STA, Physical design, etc. Knowledge of low power flow (power gating, multi-Vt flow, power supply management etc.) Circuit level comprehension of time critical paths in the design Understanding of deep sub-micron design problems and solutions (leakage power, signal integrity, DFM etc.) Tcl/Perl scripting Willing to handle technical deliveries with a small team of engineers. Strong problem-solving skills. Applicants :Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries). Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law. To all Staffing and Recruiting Agencies :Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications. If you would like more information about this role, please contact Qualcomm Careers.

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. 6 - 18 yrs experience in Physical Design and timing signoff for high speed cores. Should have good exposure to high frequency design convergence for physical design with PPA targets and PDN methodology. Masters/Bachelors Degree in Electrical/Electronics science engineering with at least 7+ years of experience in IC design. Experience in leading block level or chip level Physical Design, STA and PDN activities. Work independently in the areas of RTL to GDSII implementation. Ability to collaborate and resolve issues wrt constraints validation, verification, STA, Physical design, etc. Knowledge of low power flow (power gating, multi-Vt flow, power supply management etc.) Circuit level comprehension of time critical paths in the design Understanding of deep sub-micron design problems and solutions (leakage power, signal integrity, DFM etc.) Tcl/Perl scripting Willing to handle technical deliveries with a small team of engineers. Strong problem-solving skills. Applicants :Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries). Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law. To all Staffing and Recruiting Agencies :Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications. If you would like more information about this role, please contact Qualcomm Careers.

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field. Masters/Bachelors Degree in Electrical/Electronics science engineering with at least 8+ years of experience in IC design. 2-4 yrs experience in Physical Design and timing signoff for high speed cores. Should have good exposure to high frequency design convergence for physical design with PPA targets and PDN methodology. Experience in leading block level or chip level Physical Design, STA and PDN activities. Work independently in the areas of RTL to GDSII implementation. Ability to collaborate and resolve issues wrt constraints validation, verification, STA, Physical design, etc. Knowledge of low power flow (power gating, multi-Vt flow, power supply management etc.) Circuit level comprehension of time critical paths in the design Understanding of deep sub-micron design problems and solutions (leakage power, signal integrity, DFM etc.) Tcl/Perl scripting Willing to handle technical deliveries with a small team of engineers. Strong problem-solving skills. Applicants :Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries). Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law. To all Staffing and Recruiting Agencies :Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications. If you would like more information about this role, please contact Qualcomm Careers.

Good communication skills, Should have exposure of VLSI teaching. Knowledge of advance digital design, Verilog, System Verilog, VHDL, FPGA, CMOS. Hands on experience with industry Standard Tools Having experience of min 3 years in relevant field.

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: "¢ Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. Additional About The Role : 7-14 yrs experience in Physical Design and timing signoff for high speed cores. Should have good exposure to high frequency design convergence for physical design with PPA targets and PDN methodology. Masters/Bachelors Degree in Electrical/Electronics science engineering with at least 7+ years of experience in IC design. Experience in leading block level or chip level Physical Design, STA and PDN activities. Work independently in the areas of RTL to GDSII implementation. Ability to collaborate and resolve issues wrt constraints validation, verification, STA, Physical design, etc. Knowledge of low power flow (power gating, multi-Vt flow, power supply management etc.) Circuit level comprehension of time critical paths in the design Understanding of deep sub-micron design problems and solutions (leakage power, signal integrity, DFM etc.) Tcl/Perl scripting Willing to handle technical deliveries with a small team of engineers. Strong problem-solving skills.

You will be part of ACE India , in the P- Core design team driving Intel's latest CPU's in the latest process technology. In this position, you will be responsible for timing analysis and convergence of complex partitions. Your responsibilities will include but not limited to: 1. Responsible for timing execution and convergence including setup and hold for over 5GHz Freq and low-power digital designs. 2. Deep understanding of Static timing analysis concepts 3. Timing Convergence across all HVM targets4. Closely work with SD, Integration and Floor plan teams Qualifications You must possess a Masters Degree in Electrical or Electronics Engineering with at least 4 or more years of experience in related field or a Bachelor's Degree with at least 6 years of experience. Technical Expertise in Static Timing Analysis is preferred. Preferred additional skills :- Experience of handle complex core design, high-speed designs - Timing signoff flows/tools experience both/either Synopsys/Cadence tools - Very good knowledge on Timing tools, flows and methodology - Ability to handle new feature feasibility studies - SD flow knowledge would be plus- Familiarity with Verilog/VHDL - Tcl, Perl, Python scripting - Strong verbal and written communication skills