86 Cmos Jobs - Page 2

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: In this highly cross functional role, you will be part of the Global Design Enablement team responsible for various aspects of PDK development across Custom, Analog and RF technology nodes. As a member of the CAD team, you will be working closely with Custom, Analog & RF Engineering design community to develop & support customized tools and flows for Schematic & Layout design, Circuit Simulation, IP characterization, Custom/Analog P&R and transistor-level EM/IR flows. You will also have the responsibility to collaborate with our Foundry and EDA partners to deploy best-in class EDA tools and flows in addition to developing in-house productivity & QoR automation solutions for improving overall design methodology. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. Minimum Qualifications Bachelors or masters in electrical engineering, Computer Science, or related field. 6+ years of industry experience in CAD/EDA or PDK development Knowledge of Virtuoso suite of tools- Schematic, Layout, Analog Design Environment etc. Proficiency in one or more of the programming/scripting languages- , Python, Perl and TCL. Good understanding of CMOS fundamentals and Circuit Design Concepts Strong aptitude for programming and automation Good communication skills and ability to work collaboratively in a team environment Preferred Qualifications Familiarity with SPICE simulation tools (Hspice, SpectreX/APS, AFS/Solido SPICE , PrimeSim SPICE, ADS, GoldenGate etc.) Experience with Electromagnetic tools, like Peakview and EMX, is a plus. Knowledge of FinFet & SOI processes is a plus Educational Requirements RequiredBachelor's, Electrical Engineering Applicants Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries). Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law. To all Staffing and Recruiting Agencies Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications. If you would like more information about this role, please contact Qualcomm Careers.

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field. Working experience (2+ years) in preferably Memory design Compiler approach of developing embedded SRAM/ROM development Fundamental know how on bit cell and its characteristics (SNM, WM, Cell current, Standby current, data retention) Fundamentals of process variability and its effect on memory design Strong understanding of Digital/Memory circuit design/layouts Critical path modeling concept, various type of models ( RC, C, Pai, ladder, distributive, etc) Good knowledge of semiconductor physics in general. Knowledge of and affinity to IC technology and IP design is mandatory Applicants Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries). Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law. To all Staffing and Recruiting Agencies Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications. If you would like more information about this role, please contact Qualcomm Careers.

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. Roles and Responsibilities Work closely with CAD and custom macro/memory design leads to understand the design methodology and high level requirements and develop flows. Develop efficient analysis and model generation methodologies for timing and noise to achieve tight correlation. Determine key areas where automation and leading methodologies can help improve PPA. Define, innovate and implement new infrastructure capabilities that can be used to accelerate design and development, and improve user experience. Preferred qualifications MS degree in Computer Engineering; 5+ years of practical experience Strong skills in transistor level signoff tools for timing, emir, simulations, extraction and IPQA. Experience in flow development at high scale (multithreading, ml capabilities, hyperscaling, schedulers, filer hot-spot management etc.). Direct experience with efficient visualization tools to analyze results, log parsers, web views, error/warning scanners etc. Strong fundamentals in scripting languages (python, tcl, sh. others), automation, general purpose CAD infrastructure and flows. Good understanding of stdcell or memory design fundamentals. Excellent partner collaborating with design team in flow debug and support. Experience with signing off accuracy and correlation of analysis flows (compare to spice, foundry models, etc.) Tool knowledge in any of these is a plus- nanotime, xa/spectre, liberate, primelib, totem Applicants Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries). Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law. To all Staffing and Recruiting Agencies Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications. If you would like more information about this role, please contact Qualcomm Careers.

Job Area: Engineering Services Group, Engineering Services Group > Layout Engineer General Summary: Develops block, macro, or chip level layouts and floorplans according to project requirements, specifications, and design schematics. Applies understanding of design manuals, established processes, layout elements, and basic electronic principles to create accurate designs that meet project needs. Conducts analyses, tests, and verifies designs using different tools and techniques to identify and troubleshoot issues, and stays abreast of new verification methods. Works with multiple internal and external stakeholders to align on projects, provide updates, and resolve issues. Minimum Qualifications: "¢ Bachelor's degree in Electrical Engineering, Computer Science, Mathematics, Electronic Engineering, or related field and 3+ years of experience designing custom layouts in relevant domain (e.g., analog, mixed signal, RF, digital design), or related work experience. OR Associate's degree in Computer Science, Mathematics, Electrical Engineering or related field and 5+ years of experience designing custom layouts in relevant domain (e.g., analog, mixed signal, RF, digital design), or related work experience. OR High School diploma or equivalent and 7+ years of experience designing custom layouts in relevant domain (e.g., analog, mixed signal, RF, digital design), or related work experience. "¢ 3+ years of experience using layout design and verification tools (e.g., cadence, LVS, rmap). SRAM Mask Layout Designer Qualcomm is a company of inventors seeking to revolutionize the CPU market in an age of new possibilities. Are you interested in joining Qualcomm"™s high performance CPU team as an SRAM Mask Layout Designer? You will have the opportunity to work with some of the most talented and passionate engineers in the world to create designs that push the envelope on performance, energy efficiency and scalability. We offer a fun, creative and flexible work environment, with a shared vision to build products to change the world. As a Mask Layout Designer, you will develop block or macro level layouts and floorplans for high performance custom memories according to project requirements, specifications, and design schematics. Minimum qualifications — 5+ years of experience and a high school diploma or equivalent — OR 5+ years experience and BS in Electrical Engineering — OR 3+ years experience and MS in Electrical Engineering — Direct experience with custom SRAM layout — Experience in industry standard custom design tools and flows. — Knowledge of leading-edge FinFET and/or nanosheet processes (5nm or newer). — Experience in Layout design of library cells, datapaths, memories in deep sub-micron technologies. — Knowledge of all aspects of Layout floorplanning and hierarchical assembly. — Knowledge of Cadence Virtuoso and Calibre LVS/DRC. Preferred qualifications — Good understanding of device parasitics and reliability considerations during layout. — Good understanding of critical circuits and layout styles. — Ability to write Skill code for layout automation. — Knowledge of improving EMIR in layout. — Good communication skills to work with different teams to accurately describe issues and follow them through for completion. Roles and Responsibilities — Design layout for custom memories and other digital circuits based on provided schematics. — Read and interpret design rule manuals to create optimal and correct layout. — Own the entire layout process from initial floorplanning to memory construction to physical verification. — Use industry standard verification tools to validate LVS, DRC, ERC etc. — Interpret the results from the verification suite and perform layout fixes as needed. — Provide layout fixes as directed by the circuit design engineers. — Work independently and execute memory layout with little supervision. — Provide realistic schedules for layout completion. — Provide insight into strategic decisions regarding memory layout and

Work Profile : - Work on development of custom Analog circuit boards for applications related to RF, interfaces etc. - Implement new features and bug fixes - Verify analog/mixed-signal integrated circuits - Develop test cases to verify new features and bug fixes - Review and update the user manuals for software tools. - Supporting digital modelling of analog circuits for mixed-signal verification - Creating design specifications and circuit schematics - Work both independently and in a team environment, with the opportunity to provide technical leadership to other members of the engineering team - Create and/or modify specification documents detailing system design and enhancements to meet marketing requirements - Collaborate with others in the creation of technical reports, whitepapers, and user documentation Requisites : - EE/EEE/ECE graduate, undergraduate degree from reputed Tier 1 or Tier 2 colleges . - Strong knowledge of analog integrated circuit design fundamentals - Proven experience taking designs from concept to production - Experience in analog/mixed-signal IC design & verification - Understanding of BJT, CMOS and Op-Amp technologies. - Good understanding of analog/mixed-signal design flows (Cadence, Synopsys) - Transistor and system level simulation skills - Discrete time and continuous time signal processing skills - Strong lab and silicon validation skills - Verilog based digital design and test bench development, is a plus - Strong communication skills, both written and verbal

We Are: At Synopsys, we drive the innovations that shape the way we live and connect Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content Join us to transform the future through continuous technological innovation, You Are: You are a highly skilled and experienced Analog Design Engineer with a passion for developing cutting-edge technology With a strong foundation in Electrical or Computer Engineering, you have honed your expertise in transistor-level circuit design and are adept at working with high-speed analog integrated circuits Your deep understanding of CMOS design fundamentals and familiarity with various SerDes sub-circuits make you an invaluable asset to any team You thrive in collaborative environments, working seamlessly with cross-functional teams of analog and digital designers Your meticulous approach ensures optimal power, area, and performance targets are met, and your innovative design strategies push the boundaries of what is possible You are not only technically proficient but also possess excellent communication and documentation skills, allowing you to effectively share your ideas and results with peers and customers Your proactive attitude and problem-solving abilities make you a go-to person for post-silicon design updates and electrical characterization In summary, you are a seasoned professional ready to take on the challenges of high-speed analog integrated circuit design in the latest FinFET process nodes, What Youll Be Doing: Review SerDes standards to develop analog sub-block specifications, Identify and refine circuit architectures to achieve optimal power, area, and performance targets, Propose design and verification strategies that efficiently use simulator features to ensure the highest quality design, Oversee physical layout to minimize the effect of parasitics, device stress, and process variation, Present simulation data for peer and customer review, Document design features and test plans, Consult on the electrical characterization of your circuit within the SerDes IP product, Propose solutions for post-silicon design updates, The Impact You Will Have: Drive innovation in high-speed analog integrated circuit design, Ensure optimal performance, power efficiency, and area utilization of our products, Contribute to the development of industry-leading SerDes IP, Enhance the reliability and quality of our analog sub-blocks, Support the successful integration of SerDes IP into customer products, Foster collaboration and knowledge sharing within the R&D team, Influence design strategies and best practices within the organization, What Youll Need: BE with 8+ years of relevant experience or MTech with 6+ years of relevant experience in Electrical Engineering or Computer Engineering, In-depth familiarity with transistor-level circuit design and sound CMOS design fundamentals, Detailed design experience with at least one, and familiarity with several other SerDes sub-circuits, Awareness of ESD issues and circuit techniques for addressing them, Familiarity with custom digital design and high-speed logic paths, Knowledge of design for reliability, including EM, IR, and aging considerations, Experience with tools for schematic entry, physical layout, and design verification, Hands-on experience with physical layout of high-speed circuits is a plus, Proficiency with SPICE simulators and simulation methods, Knowledgeable in Verilog-A for analog behavioral modeling and simulation-control/data-capture, Experience with scripting languages such as TCL, Perl, C, Python, or MATLAB is desired, Who You Are: Collaborative and able to work effectively in a team environment, Detail-oriented with a strong focus on quality and reliability, Proactive problem-solver with innovative design strategies, Excellent communicator with strong documentation skills, Adaptable and able to thrive in a fast-paced, dynamic environment, The Team Youll Be A Part Of: You will be part of a fast-growing analog and mixed-signal R&D team dedicated to developing high-speed analog integrated circuits in the latest FinFET process nodes Our team is composed of talented analog and digital designers from diverse backgrounds, working collaboratively to push the boundaries of technology We leverage a full suite of IC design tools, supplemented by custom, in-house tools supported by an experienced software/CAD team, to create industry-leading SerDes IP, Rewards and Benefits: We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs Our total rewards include both monetary and non-monetary offerings Your recruiter will provide more details about the salary range and benefits during the hiring process,

Alternate Job Titles: Senior Layout Design Engineer Analog Mixed-Signal Layout Engineer Staff Engineer, Layout Design We Are: At Synopsys, we drive the innovations that shape the way we live and connect Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content Join us to transform the future through continuous technological innovation, You Are: You are a seasoned professional with over 6 years of experience in Analog Mixed-Signal layout and verification You possess a robust understanding of deep submicron effects and mitigation, advanced tool usage, floor-planning, and routing Your expertise extends to CMOS and FinFET layouts and process technology in 28nm and below You are familiar with the layout design flow, including top-level verification flow, DRC/LVS, LPE, and have a good grasp of basic ESD and latch-up layout design considerations You understand power routes, EM and IR considerations, and DFM You have exposure to Analog/Mixed Signal circuit layout (e-g , RX, TX, PLL) Your excellent written and verbal communication skills enable you to interact effectively with internal development teams You are passionate about technology and thrive in a collaborative environment where your skills contribute to groundbreaking innovations, What Youll Be Doing: Designing and verifying complex Analog Mixed-Signal layouts, ensuring high-quality and reliable IPs, Collaborating with cross-functional teams to optimize layout designs for performance and manufacturability, Utilizing advanced tools and methodologies to mitigate deep submicron effects, Conducting floor-planning, routing, and top-level verification, Ensuring compliance with DRC, LVS, LPE standards and addressing ESD and latch-up considerations, Optimizing power routes and addressing EM and IR considerations for robust designs, The Impact You Will Have: Enhancing the performance and reliability of our high-speed SerDes IPs and other critical components, Driving innovation in Analog Mixed-Signal layout design, contributing to cutting-edge technology developments, Ensuring seamless integration and functionality of our IPs in diverse applications, Improving design efficiency and manufacturability through advanced layout techniques, Contributing to the success of our product development lifecycle by delivering high-quality designs, Supporting our mission to lead in chip design and IP integration, shaping the future of technology, What Youll Need: 6+ years of experience in Analog Mixed-Signal layout and verification, Advanced understanding of deep submicron effects and mitigation techniques, Proficiency in using advanced layout design tools and methodologies, Solid understanding of CMOS and FinFET layouts and process technology in 28nm and below, Familiarity with layout design flow, including top-level verification flow, DRC/LVS, LPE, Who You Are: You are detail-oriented, methodical, and have a deep understanding of layout design principles Your ability to communicate effectively and work collaboratively with cross-functional teams is exceptional You are proactive, always looking for innovative solutions to complex problems, and your passion for technology drives you to stay updated with the latest industry trends and advancements, The Team Youll Be A Part Of: You will be part of a dynamic and innovative team focused on developing high-performance Analog Mixed-Signal layouts Our team collaborates closely with other engineering departments to ensure the seamless integration and functionality of our IPs We value creativity, continuous learning, and a collaborative spirit to push the boundaries of technology and innovation, Rewards and Benefits: We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs Our total rewards include both monetary and non-monetary offerings Your recruiter will provide more details about the salary range and benefits during the hiring process,

Role & responsibilities Department: Quality Assurance Skill set: 1)QA- stability & Retain sample 2) Doc cell 3) QA Regulatory Designation: Officer/ Sr. Officer/ Executive/ Sr. Executive Education: M.Sc / B.Pahrma / M.Pharma Experience: 2 to 10 Department: OSD Packing Skill set: Operate and monitor primary packing machines such as blister packing, strip packing, and bottle packing machines.,Perform in-process checks like weight variation, visual inspection, and seal integrity. Designation: Officer/Executive Education: B.Pahrm/Diploma/ITI Experience: 2 to 10 years Department: CQA Skill set: 1) Doc Team (Candidates from QC background with LIMS handling experience can apply) 2) CQA compliance + Doc cell 3) Vendor management + Artwork 4) Loan license/ Third party Designation: Officer/ Sr. officer/ Executive/ Sr. Executive/ Assistant manager/ Manager Education: B.Pharma/M.Pharma/M.sc Experience: 2 to 16 years

Job Requirements We are seeking a highly skilled and experienced Product HW Validation Engineer to join our team. As a key member of the hardware engineering team, you will be responsible for validating the performance of various sensors used in our smart wearable products, including display touch, proximity sensor, ambient light sensor, and inertial measurement units (IMUs). Your expertise will ensure that our products meet the highest standards of quality, reliability, and customer satisfaction. Work Experience Responsibilities Design and execute comprehensive validation plans for sensors used in smart wearables, including: Display touch sensors Proximity sensors Ambient light sensors Inertial Measurement Units (IMUs) Collaborate with cross-functional teams, including hardware design, software development, and manufacturing, to identify and resolve technical issues Develop and maintain test fixtures, equipment, and procedures to support sensor validation Analyze data from various sources, including lab tests, field trials, and customer feedback, to identify trends and areas for improvement Create detailed reports and presentations to communicate findings and recommendations to stakeholders Work closely with suppliers to evaluate and qualify new sensor technologies Participate in the development of product specifications, design requirements, and testing protocols Stay up-to-date with industry trends and emerging technologies in sensor development and validation Requirements Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or related field 5+ years of experience in hardware validation, preferably in the consumer electronics industry Strong knowledge of sensor technologies, including display touch, proximity, ambient light, and IMUs Experience with validation methodologies, including design of experiments, statistical analysis, and data visualization Working knowledge of Python, and LabVIEW for data processing and automation. Experience executing electrical validation on the bench. Familiarity with lab equipment such as oscilloscopes, DMM, e-load, power supply, power analyzer, spectrum analyzer, signal generator, and temp chamber. Excellent problem-solving skills, with the ability to analyze complex technical issues and develop creative solutions Understanding of board schematics and board layout. Ability to find proper probe locations and identify potential points of failure in the DUT. Effective communication and collaboration skills, with the ability to work with cross-functional teams and external partners Ability to travel occasionally for business purposes Nice to Have Experience with wearable devices and smart home products Knowledge of wireless communication protocols, including Bluetooth, Wi-Fi, and NFC Knowledge in I2C/SMBus, UART, SPI, USB, Network stack is a plus Familiarity with cloud-based platforms and data analytics tools Certification in six sigma or lean manufacturing methodologies Experience with scripting languages, such as Perl or Ruby What We Offer Competitive salary and benefits package Opportunity to work on cutting-edge technology products Collaborative and dynamic work environment Professional development opportunities, including training and education programs Flexible work arrangements. If you are passionate about sensor technology and have a strong background in hardware validation, we encourage you to apply for this exciting opportunity.

Design and development of analog and mixed-signal IC blocks such as amplifiers, ADCs/DACs, voltage regulators, PLLs, bandgap references, and filters. Perform transistor-level circuit design, simulations (pre- and post-layout), using cadence Virtuoso.

Basics nand , nor , latches , flops , building blocks , tools - finesim , spectre; DRAM/ SRAM is Mandatory Simulation tools: Cadence/Spectre/ primesim - Must Have Experience: 3-5 Yrs Onsite: Hyderabad

RF, Analog & Mixed Signal level designs for various applications using CMOS, BiCMOS and GaAs processes on industry standard EDA tools.Must be an efficient user of Cadence (Virtuoso)/Agilent ADS tools. Good knowledge of IC design,simulations & Layout

Defining and developing ASIC RTL design and verification at both chip and block levels. Writing and modifying test cases, checkers, and scoreboards in a system Verilog-based test environment. Collaborating with cross-functional teams to ensure seamless integration of analog and digital components. Conducting AMS verification, particularly for high-speed SerDes designs supporting multi-protocols. Utilizing Synopsys analog mixed-signal design tools for efficient design and verification processes. Programming and scripting using TCL, Perl, and Python to automate and streamline workflows. The Impact You Will Have: Enhancing the performance and reliability of our high-performance silicon chips. Contributing to the development of innovative technologies that drive the Era of Pervasive Intelligence. Improving the efficiency and effectiveness of our design and verification processes. Ensuring the seamless integration of analog and digital components in our products. Supporting the creation of cutting-edge solutions for self-driving cars, learning machines, and more. Driving continuous technological innovation within Synopsys and the broader industry. What You ll Need: Looking for 2+yrs experience with BTech / MTech in VLSI / Electronics/ Microelectronics Knowledge or hands-on expertise/analysis of Analog and digital CMOS circuit designs Knowledge on electrical circuit networks and analysis Knowledge or hands-on Verilog/System Verilog languages and supported methodologies like VMM, UVM Must be able write/modify testcases, checkers, scoreboards in a system Verilog based test environment AMS verification experience in high speed Serdes designs supporting multi-protocols is an advantage. Experience with the Synopsys Analog mixed-signal design tool set is an advantage. Modelling languages Verilog-a/ams can be an advantage Programming/scripting know-how e. g. tcl, perl, python Experience with Linux Good communication skills, ability to take ownership Self-organized to ensure that project timescales are met Who You Are: Excellent communicator with strong interpersonal skills. Proactive and able to take ownership of projects. Self-organized and capable of managing time effectively. Collaborative team player who thrives in a dynamic environment. Detail-oriented and committed to delivering high-quality results.

Skills :. Experience in project management, with a focus on the front-end stages of semiconductor chip design, technical background in digital design, verification, and synthesis,EDA Tools Required Candidate profile Notice Period: immediate Education: Masters in VLSI design from reputed universities like IIT/NIT with background in Bachelors in Electronics and Communication, or a related field

Responsibilities may be quite diverse of a technical nature. Need to understand VLSI testing and vectors for ATE . Vectors/Content stabilization, implementation and validation of various DFT features. Understand the system level testing and work towards meeting DPM requirements. Need to work towards automation. Qualifications Pursuing Master Degree in Electronics or Computer Engineering and available for 1 year internship program to work Intel's chipsets. Need to have good understanding of CMOS, VLSI design and Test. Knowledge of Scripting in Perl, shell, Python . A very good team player with good interpersonal, planning and excellent communication skills. Preferred colleges Any IIT, Any NIT, MIT, VIT, Thapar Eng College, Delhi College of Engineering , PES, Punjab Eng College ,RVCE.

• Expertise in Cadence VLE/VXL and Mentor Graphic Calibre DRC/LVS is a must. • Perform layout verification like LVS/DRC/Antenna, quality check and support documentation. TSMC 3nm/5nm7nm/16nm Finfet & 3+ exp 3nm Provident fund Health insurance Annual bonus

About The Role This position is for an experienced, motivated, and passionate circuit design engineer with expertise in the area of custom circuits memories, SSARF SRAM, Register File, ROM design for GHI CCG SAI Circuits Team. In this position you will be working in a team responsible for delivering high quality designs for graphics projects. You would also be involved in key decisions finalizing the memory architecture that best meets the design requirements of the program, technical readiness involving circuit simulations and responsibility for implementation as well as convergence of the design while meeting high circuit quality. The key responsibilities include ownership of tools, flows, methodologies as well as coming up with innovative design implementations with focus on power and area reduction. The role would require deep understanding of transistor and circuit behavior, strong communication, problem solving skills, time management and multitasking skills. The team members have also an opportunity to diversify their skills into other custom circuits as well as working with the client in integration of the custom circuits. Qualifications Minimum QualificationsMinimum 4-7 years of experience in designing and delivering of SRAM's/RF's/ROM's. Understanding of semiconductor device physics; VLSI Technology and VLSI circuits (analog/digital), Familiarity with spice simulations and Verilog and other tools for design and development of memory IP's like ESPCV, Nanotime, Nova, Totem etc. Knowledge of scripting (PERL/TCL/Python) is desirable, Preferred Educational QualificationsME/Mtech/MS in Microelectronics/VLSI Inside this Business Group The Client Computing Group (CCG) is responsible for driving business strategy and product development for Intel's PC products and platforms, spanning form factors such as notebooks, desktops, 2 in 1s, all in ones. Working with our partners across the industry, we intend to deliver purposeful computing experiences that unlock people's potential - allowing each person use our products to focus, create and connect in ways that matter most to them. As the largest business unit at Intel, CCG is investing more heavily in the PC, ramping its capabilities even more aggressively, and designing the PC experience even more deliberately, including delivering a predictable cadence of leadership products. As a result, we are able to fuel innovation across Intel, providing an important source of IP and scale, as well as help the company deliver on its purpose of enriching the lives of every person on earth.

Gain hands-on experience in RFIC design, working with advanced EDA tools. This internship offers real-world experience and learning from industry experts to enhance your skills. Network and build your professional portfolio.

About The Role Works in the area of Software Engineering, which encompasses the development, maintenance and optimization of software solutions/applications. 1. Applies scientific methods to analyse and solve software engineering problems. 2. He/she is responsible for the development and application of software engineering practice and knowledge, in research, design, development and maintenance. 3. His/her work requires the exercise of original thought and judgement and the ability to supervise the technical and administrative work of other software engineers. 4. The software engineer builds skills and expertise of his/her software engineering discipline to reach standard software engineer skills expectations for the applicable role, as defined in Professional Communities. 5. The software engineer collaborates and acts as team player with other software engineers and stakeholders. Works in the area of Software Engineering, which encompasses the development, maintenance and optimization of software solutions/applications.1. Applies scientific methods to analyse and solve software engineering problems.2. He/she is responsible for the development and application of software engineering practice and knowledge, in research, design, development and maintenance.3. His/her work requires the exercise of original thought and judgement and the ability to supervise the technical and administrative work of other software engineers.4. The software engineer builds skills and expertise of his/her software engineering discipline to reach standard software engineer skills expectations for the applicable role, as defined in Professional Communities.5. The software engineer collaborates and acts as team player with other software engineers and stakeholders. About The Role - Grade Specific Is fully competent in it's own area and has a deep understanding of related programming concepts software design and software development principles. Works autonomously with minimal supervision. Able to act as a key contributor in a complex environment, lead the activities of a team for software design and software development. Acts proactively to understand internal/external client needs and offers advice even when not asked. Able to assess and adapt to project issues, formulate innovative solutions, work under pressure and drive team to succeed against its technical and commercial goals. Aware of profitability needs and may manage costs for specific project/work area. Explains difficult concepts to a variety of audiences to ensure meaning is understood. Motivates other team members and creates informal networks with key contacts outside own area. Skills (competencies) Verbal Communication

Description: Job Title: Memory Circuit Design Verification Engineer Memory Circuit Design Verification Engineer Description As a Memory Circuit Design Verification Engineer, you will work in a highly innovative, motivated, young and dynamic design team capable of verifying complete products using state of the art memory technologies. You will need to have the ability to evaluate full chip and/or block level functionality and provide solutions to help the timely delivery of a functionally correct design. Unique Opportunities Complete ownership of verification and end to end analysis of complex full chip gate level custom designs with advanced low power and power management technologies spread across multiple categories such as DDR4,LPDDR4,DDR5 and LPDDR5 that are capable of operating at high speeds of up to 6400MT/s. Collaborate closely with design and verification team members spread across the globe, many of whom have decades of experience in memory design. Work on cross functional tasks that can widen your skill set. Responsibilities Provide verification support to design projects by simulating, analyzing and debugging pre-silicon full chip designs. Develop Test cases/Stimulus to increase the functional coverage for all DRAM and emerging memory architectures and features. Develop and maintain test benches and test vectors using simulation tools and run regressions for coverage analysis and improvements. Co-work with international colleagues on developing new verification flows to take on the challenges in DRAM and emerging memory design. Participate in developing verification methodology and verification environments for advanced DRAM and emerging memory products. Core Requirements Basic understanding of CMOS and gate level circuit designs Familiarity with SPICE Familiarity with Verilog simulations Good communication skills and ability to work well in a team Preferred Qualities Analytical capability for complex gate level circuit designs Experience in SystemVerilog, PLI coding Experience in UVM Test Bench Experience in DRAM, SRAM or other memory related fields Experience in AMS verification and co-sim Experience Level 3-7+ years Education Bachelors or Post Graduate Degree in Electronics Engineering or related engineering field required

Description: Role and Responsibilities Collaborating with the global team to coordinate the complete layout of the plant while maintaining effective team. • Excellent communication skills, along with hands-on expertise, are required, and being a team player is crucial. • Responsible for Layout design and development of critical analog and custom digital block. • Perform layout verification like LVS/DRC/Antenna, quality check and documentation. • Responsible for on-time delivery of block-level layouts with acceptable quality. • Demonstrate leadership Skill in planning, area/time estimation, scheduling, delegation, and execution to meet project schedule/milestones in multiple project environment. • Guide junior team-members in their execution of Sub block-level layouts & review their work. • Contribute to effective project-management. • Effectively communicating with Global engineering teams to assure the success of layout project. Qualification/Requirements 7 to 8-year experience in memory/analog/custom layout design in advanced CMOS process. • A strong understanding of memory design methodology and related issues is important. • The candidate should be well-versed in various levels of memory layouts, including custom memory bits, leaf cells, control blocks, read-write components, sense amplifiers, and decoders. • Should have hands on experience in creating layout of critical blocks such as Temperature sensor, PLL, ADC, DAC, LDO, Bandgap, Ref Generators, Charge Pump, Current Mirrors, Comparator, Differential Amplifier etc., • Expertise in Cadence VLE/VXL and Mentor Graphic Calibre DRC/LVS is a must. • Good understanding of Analog Layout fundamentals (e.g., Matching, Electro-migration, Latch-up, coupling, crosstalk, IR-drop, active and passive parasitic devices etc.) • Understanding layout effects on the circuit such as speed, capacitance, power, and area etc., • Ability to understand design constraints and implement high-quality layouts. • Excellent command and problem-solving skills in physical verification of custom layout. • Multiple Tape out support experience will be an added advantage. • Excellent verbal and written communication skills. Education BE or MTech in Electronic/VLSI Engineering Must Haves: MANDATE: • A strong understanding of memory design methodology and related issues is important. • The candidate should be well-versed in various levels of memory layouts, including custom memory bits, leaf cells, control blocks, read-write components, sense amplifiers, and decoders.

Description: Experience : 5yrs to 8yrs. Responsible for Design and development of critical analog, mixed-signal, custom digital block, and full chip level integration support. • Expertise in Cadence VLE/VXL and Mentor Graphic Calibre DRC/LVS is a must. • Perform layout verification like LVS/DRC/Antenna, quality check and support documentation. • Responsible for on-time delivery of block-level layouts with acceptable quality. • Excellent problem-solving skills in physical verification of custom layout. • Demonstrate high quality and accurate execution to meet project schedule/milestones in multiple project environment. • Ability to guide junior team-members in their execution of Sub block-level layouts & review critical items. • Contribute to effective project-management. • Effectively communicating with Local engineering teams to assure the success of layout project. Educational Background • BE or MTech in Electronic/VLSI Engineering • 5 + year experience in analog/custom layout design in advanced CMOS process. NOTE: **custom layout or analog layout with TSMC 3nm/5nm7nm/16nm Finfet & 5+ exp **** TSMC 3nm Exp - MANDATORY.

Job Description Responsibilities may be quite diverse of a technical nature. Need to understand VLSI testing and vectors for ATE . Vectors/Content stabilization, implementation and validation of various DFT features. Understand the system level testing and work towards meeting DPM requirements. Need to work towards automation. Qualifications Pursuing Master Degree in Electronics or Computer Engineering and available for 1 year internship program to work Intel's chipsets. Need to have good understanding of CMOS, VLSI design and Test. Knowledge of Scripting in Perl, shell, Python .A very good team player with good interpersonal, planning and excellent communication skills.Preferred colleges Any IIT, Any NIT, MIT, VIT, Thapar Eng College, Delhi College of Engineering , PES, Punjab Eng College ,RVCE

Role & responsibilities Responsible for Design and development of critical analog, mixed-signal, custom digital block, and full chip level integration support. • Expertise in Cadence VLE/VXL and Mentor Graphic Calibre DRC/LVS is a must. • Perform layout verification like LVS/DRC/Antenna, quality check and support documentation. • Responsible for on-time delivery of block-level layouts with acceptable quality. • Excellent problem-solving skills in physical verification of custom layout. • Demonstrate high quality and accurate execution to meet project schedule/milestones in multiple project environment. • Ability to guide junior team-members in their execution of Sub block-level layouts & review critical items. • Contribute to effective project-management. • Effectively communicating with Local engineering teams to assure the success of layout project. Educational Background • BE or MTech in Electronic/VLSI Engineering • 5 + year experience in analog/custom layout design in advanced CMOS process. NOTE: **custom layout or analog layout with TSMC 3nm/5nm7nm/16nm Finfet & 5+ exp **** TSMC 3nm Exp - MANDATORY Preferred candidate profile Only Immediate Joiner Perks and benefits

Skills/Experience: Experience with high speed circuits like serializer, deserializer, Rx, Tx,PLL, ADC etc Strong VLSI Fundamentals, Circuits design & Digital Systems deep submicron CMOS design based on FinFETs technology. Solid fundamentals in circuit analysis and Clock/Memory Circuit design. Experience (years) : 2+ Year Education Qualification: BE/B-Tech/ME/M-Tech degree in Electronics and Communication, Electrical Engineering, or related field.