92 Cmos Jobs - Page 2

Role & responsibilities JD: Advanced memory layout design (SRAM, ROM, custom) Hands-on with FinFET, Virtuoso, Calibre, PVS Tight collaboration with circuit & verification teams Mastery in DRC/LVS, parasitic optimization, and layout efficiency Experience with foundry tech files and tapeout is a huge plus!

You will be part of a big MNC as a Semiconductor Domain Consultant, responsible for utilizing your expertise in semiconductor manufacturing processes, chip design, and testing methodologies. Your role will require a strong understanding of semiconductor technologies such as CMOS, memory devices, RF, power semiconductors, and sensors. Additionally, you will need experience with semiconductor supply chain management, market analysis, and knowledge of industry standards, regulations, and certifications. Your responsibilities will include effective communication, presentation, and client relationship management. You should be able to work both independently and collaboratively as part of a team. Project management experience would be beneficial for this role. It would be advantageous to have experience with advanced semiconductor packaging technologies, familiarity with semiconductor EDA tools and software, knowledge of semiconductor equipment and infrastructure, and experience in emerging fields like AI/ML hardware accelerators, quantum computing, and IoT. Join us at this exciting opportunity located PAN India and contribute your skills to the dynamic world of semiconductor technology.,

Good communication skills, Should have exposure of VLSI teaching. Knowledge of advance digital design, Verilog, System Verilog, VHDL, FPGA, CMOS. Hands on experience with industry Standard Tools Having experience of min 3 years in relevant field.

Role Purpose The purpose of this role is to perform the development of VLSI system by defining the various functionalities, architecture, layout and implementation for a client Do 1. Conduct verification of the module/ IP functionality and provide customer support a. Understand the architecture of the module or the IP and create verification environment and the development plan as per Universal Verification Methodology b. Create test bench development and test case coding of the one or multiple module c. Write the codes or check the code as required d. Execute the test cases and debug the test cases if required e. Conduct functional coverage analysis and document the test cases including failures and debugging procedures on SharePoint/ JIRA or any other platform as directed f. Test the entire IP functionality under regression testing and complete the documentation to publish to client g. Troubleshoot, debug and upgrade existing systems on time & with minimum latency and maximum efficiency h. Write scripts for the IP i. Comply with project plans and industry standards 2. Ensure reporting & documentation for the client a. Ensure weekly, monthly status reports for the clients as per requirements b. Maintain documents and create a repository of all design changes, recommendations etc c. Maintain time-sheets for the clients d. Providing written knowledge transfer/ history of the project Mandatory Skills: VLSI Physical Design Planning. Experience: 1-3 Years.

Role & responsibilities: Outline the day-to-day responsibilities for this role. Preferred candidate profile: Specify required role expertise, previous job experience, or relevant certifications.

Job Title: AI/ML Engineer - Time Series Forecasting & Clustering Location: Bangalore Experience: 2+ Years Job Type: Full-Time Mandatory Skills: AI/ML Engineer with Time Series Forecasting & Clustering experience Responsibilities in Brief: Time Series Forecasting : Build models to predict trends from time series data. Clustering : Develop algorithms to group and analyze data segments. Data Insights : Analyze data to enhance model performance. Team Collaboration : Work with teams to integrate models into products. Stay Updated : Apply the latest AI techniques to improve solutions. Qualifications: Education : Bachelors/Masters in Computer Science or related field. Experience : Hands-on experience with time series forecasting and clustering. Skills : Proficient in Python, R, and relevant ML tools Perks & Benefits: Health and Wellness: Healthcare policy covering your family and parents. Food: Enjoy scrumptious buffet lunch at the office every day. Professional Development: Learn and propel your career. We provide workshops, funded online courses and other learning opportunities based on individual needs. Rewards and Recognitions: Recognition and rewards programs in place to celebrate your achievements and contributions. Why join Relanto? Health & Family: Comprehensive benefits for you and your loved ones, ensuring well-being. Growth Mindset: Continuous learning opportunities to stay ahead in your field. Dynamic & Inclusive: Vibrant culture fostering collaboration, creativity, and belonging. Career Ladder: Internal promotions and clear path for advancement. Recognition & Rewards: Celebrate your achievements and contributions. Work-Life Harmony: Flexible arrangements to balance your commitments. To find out more about us, head over to our Website and LinkedIn

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field. Working experience (2+ years) in preferably Memory design Compiler approach of developing embedded SRAM/ROM development Fundamental know how on bit cell and its characteristics (SNM, WM, Cell current, Standby current, data retention) Fundamentals of process variability and its effect on memory design Strong understanding of Digital/Memory circuit design/layouts Critical path modeling concept, various type of models ( RC, C, Pai, ladder, distributive, etc) Good knowledge of semiconductor physics in general. Knowledge of and affinity to IC technology and IP design is mandatory

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: In this highly cross functional role, you will be part of the Global Design Enablement team responsible for various aspects of PDK development across Custom, Analog and RF technology nodes. As a member of the CAD team, you will be working closely with Custom, Analog & RF Engineering design community to develop & support customized tools and flows for Schematic & Layout design, Circuit Simulation, IP characterization, Custom/Analog P&R and transistor-level EM/IR flows. You will also have the responsibility to collaborate with our Foundry and EDA partners to deploy best-in class EDA tools and flows in addition to developing in-house productivity & QoR automation solutions for improving overall design methodology. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. Minimum Qualifications Bachelors or master’s in electrical engineering, Computer Science, or related field. 6+ years of industry experience in CAD/EDA or PDK development Knowledge of Virtuoso suite of tools – Schematic, Layout, Analog Design Environment etc. Proficiency in one or more of the programming/scripting languages – , Python, Perl and TCL. Good understanding of CMOS fundamentals and Circuit Design Concepts Strong aptitude for programming and automation Good communication skills and ability to work collaboratively in a team environment Preferred Qualifications Familiarity with SPICE simulation tools (Hspice, SpectreX/APS, AFS/Solido SPICE , PrimeSim SPICE, ADS, GoldenGate etc.) Experience with Electromagnetic tools, like Peakview and EMX, is a plus. Knowledge of FinFet & SOI processes is a plus Educational RequiredBachelor's, Electrical Engineering

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. Roles and Responsibilities Work closely with CAD and custom macro/memory design leads to understand the design methodology and high level requirements and develop flows. Develop efficient analysis and model generation methodologies for timing and noise to achieve tight correlation. Determine key areas where automation and leading methodologies can help improve PPA. Define, innovate and implement new infrastructure capabilities that can be used to accelerate design and development, and improve user experience. Preferred qualifications MS degree in Computer Engineering; 5+ years of practical experience Strong skills in transistor level signoff tools for timing, emir, simulations, extraction and IPQA. Experience in flow development at high scale (multithreading, ml capabilities, hyperscaling, schedulers, filer hot-spot management etc.). Direct experience with efficient visualization tools to analyze results, log parsers, web views, error/warning scanners etc. Strong fundamentals in scripting languages (python, tcl, sh. others), automation, general purpose CAD infrastructure and flows. Good understanding of stdcell or memory design fundamentals. Excellent partner collaborating with design team in flow debug and support. Experience with signing off accuracy and correlation of analysis flows (compare to spice, foundry models, etc.) Tool knowledge in any of these is a plus – nanotime, xa/spectre, liberate, primelib, totem

Role Purpose The purpose of this role is to perform the development of VLSI system by defining the various functionalities, architecture, layout and implementation for a client Do 1. Conduct verification of the module/ IP functionality and provide customer support a. Understand the architecture of the module or the IP and create verification environment and the development plan as per Universal Verification Methodology b. Create test bench development and test case coding of the one or multiple module c. Write the codes or check the code as required d. Execute the test cases and debug the test cases if required e. Conduct functional coverage analysis and document the test cases including failures and debugging procedures on SharePoint/ JIRA or any other platform as directed f. Test the entire IP functionality under regression testing and complete the documentation to publish to client g. Troubleshoot, debug and upgrade existing systems on time & with minimum latency and maximum efficiency h. Write scripts for the IP i. Comply with project plans and industry standards 2. Ensure reporting & documentation for the client a. Ensure weekly, monthly status reports for the clients as per requirements b. Maintain documents and create a repository of all design changes, recommendations etc c. Maintain time-sheets for the clients d. Providing written knowledge transfer/ history of the project Deliver No. Performance Parameter Measure 1. Verification Timeliness Quality of Code/ Number of defects Customer responsiveness Project documentation (scripts, test cases etc) 2. Self-development Skill test for next level clearance on Trend Nxt Mandatory Skills: VLSI Physical Design Planning. Experience3-5 Years.

90/130/150nm and higher node with PMIC layout experience. Performs layout and takes corrective actions in such a way that the final result meets all requirements as stated in the Design document, section layout, including all remarks from review, the customer and back annotation. Performs layout in such a way that the final result meets all general layout guidelines and matches 1-to-1 with parameter devices and hierarchy used in simulations. Create floorplan Performs DRC and takes corrective actions if needed until DRC is error free Performs LVS and takes corrective actions if needed until result is successful Performs layout in such a way that final result meets the foundry layout rules. Provides extracted netlist for back annotation to DE as specified in the Design document, section layout. Translates sub block schematics to sub block layouts, taking care of the same hierarchical build-up and respecting the guidelines of the Block review document, section layout. Adds extra useful information to the Block review document, section layout.

Design and develop RF and analog circuits such as LNAs, mixers, power amplifiers, VCOs, PLLs, and ADC/DACs. Perform system-level analysis to optimize RF performance parameters like gain, noise figure, linearity, and phase noise. Conduct circuit simulations using tools like Cadence Spectre, ADS, HFSS, Momentum, and EMX. Collaborate with layout engineers to ensure optimal floorplanning, parasitic extraction, and RF routing. Conduct post-layout verification and EM simulations for high-frequency designs. Participate in lab validation and characterization of fabricated ICs, debugging issues, and improving performance. Work closely with system architects and digital design teams for mixed-signal integration. Support product engineering and test development for production ramp-up. Qualifications: 2 to 5 years of experience in RF/analog IC design. Strong understanding of RF circuit design principles, including impedance matching, S-parameters, and nonlinearity analysis. Hands-on experience with Cadence Virtuoso, Spectre RF, ADS, HFSS, or similar EDA tools. Knowledge of CMOS/BiCMOS process technologies and parasitic-aware design methodologies. Experience in EM simulation and modeling of on-chip passives (inductors, transmission lines, baluns). Familiarity with RF lab equipment (network analyzers, spectrum analyzers, signal generators). Strong problem-solving skills and ability to work in a fast-paced startup environment. Excellent communication and teamwork skills.

Lead the design, development, and verification of RF and analog IC blocks, including LNAs, mixers, power amplifiers, PLLs, VCOs, and ADC/DACs. Drive system architecture decisions for RF front-end and transceiver designs. Guide and mentor junior engineers, ensuring high-quality design practices. Perform top-level integration, ensuring seamless connectivity and performance of RF, analog, and mixed-signal circuits. Oversee simulation, layout reviews, and post-layout verification, optimizing for performance and manufacturability. Collaborate with layout, test, and product engineering teams for silicon validation and characterization. Define and execute design methodologies for efficiency, robustness, and first-pass success. Work closely with customers and cross-functional teams to define product specifications and roadmaps. Provide technical leadership in tape-out planning, foundry interactions, and process node selection. Requirements: 7+ years of experience in RF/analog IC design, with a track record of silicon success. Strong understanding of RF system design principles, including impedance matching, noise figure optimization, and linearity. Expertise in Cadence Virtuoso, Spectre RF, ADS, HFSS, and EMX. Deep knowledge of CMOS/BiCMOS technologies and layout-aware design methodologies. Experience in full-chip integration and packaging considerations for RF ICs. Hands-on experience with RF lab characterization and debugging. Strong leadership, mentorship, and project management skills. Excellent communication and ability to work in a fast-paced startup environment.

Lead and manage the analog and RF layout team for high-performance semiconductor products Oversee layout planning, floorplanning, and routing for RF, analog, and mixed-signal IC designs. Work closely with circuit design teams to optimize layouts for performance, area, and manufacturability. Ensure DFM (Design for Manufacturability), DRC (Design Rule Check), LVS (Layout vs. Schematic), and EM (Electromigration) compliance. Drive automation and layout methodologies to improve efficiency and quality. Collaborate with foundry partners for process design kits (PDKs), layout guidelines, and tape-out requirements. Provide technical mentorship to layout engineers and review critical blocks. Own full-chip layout integration and support post-layout simulations. Qualifications: 8+ years of experience in analog/mixed-signal/RF IC layout. Strong expertise in FinFET (e.g., 16nm, 7nm, 5nm) or advanced CMOS nodes. Hands-on experience with Cadence Virtuoso, Calibre DRC/LVS, and Mentor Graphics tools. Knowledge of high-frequency layout techniques, parasitic-aware layout design, and shielding strategies. Experience in power management, high-speed SerDes, RF front-ends, or ADC/DAC layouts is a plus. Proven ability to lead teams, review layouts, and drive tape-out schedules. Strong understanding of wafer-level packaging and chip integration. Excellent problem-solving and communication skills.

Must have experience in working with MNC clients Must be good at Honouring Committed Schedules, Quality delivery, Clarity in Communication Familiarity with Serdes components like serializer or de-serializer circuits Strong fundamentals and knowledge of AMS design flow Must have familiarity with layout issues, working with layout team to fix them Must be good at preparing the Review PPT, run through the review meeting and closing all action items Must ensure the design meets PPA goals Good at debugging to ensure meeting all performance simulation issues Must be able to pass QA checks as demanded by the client Must be able to generate all relevant design views using sign-off tools Qualification BE/BTech from any reputed University Masters Preferred Experience Between 3 to 10 years Hands on with any of the spice simulators (Hspice/ Spectre)

Experience into STA and timing closure/signoff experience with PD domain skill-set/knowledge. Candidate should be able to understand the timing constraints, analyze design details, analyze timing reports from prepcts to postcts stages, in-depth concepts of 14nm technode STA analysis, DCD knowledge. Candidate is preferably expert in PT and Tempus tools. Education Requirements B. Tech / M. Tech (ECE) Shift General Work Week Monday to Friday Joining time Immediate to 90 Days

Responsible for Memory Compiler layout development and verification. Responsible for Layout design and development of Memory blocks such as Array, Row/ Column decoder, sense amplifier, pre-charge, Control blocks for SRAM. Perform layout verification like LVS/ DRC/ Latchup, quality check and documentation. Responsible for on-time delivery of block-level layouts with acceptable quality. Demonstrate leadership Skill in planning, area/time estimation, scheduling, delegation and execution to meet project schedule/milestones in multiple project environment. Guide junior team-members in their execution of Sub block-level layouts & review their work. Contribute to effective project-management. Effectively communicate with engineering teams in the India & Korea teams to assure the success of the layout project.

Exciting opportunity for freshers to work on RFIC Circuit, Layout & PCB Design using industry-grade EDA tools. Get industry exposure, grow technically, and build your semiconductor career.

Design analog and mixed-signal modules in CMOS and Power Technologies ,with a particular focus on DC-DC converter for power management ICs ; Design analog and mixed-signal system resource blocks including POR, Bandgap, LDO, Oscillator ; Assist in defining the requirements for analog and mixed-signal blocks, aligning them with IP Module architecture, and ensuring compliance with requirements through documentation. Provide essential support to physical design engineers, post-sili convalidation, production testing, and other critical activities extending beyond the design phase. Ability to lead the project, mentor the team and execute the project working with cross functional team You are best equipped for this task if you have: A masters Degree in Electrical/Electronic Engineering, Physics orequivalent field of studies; Experience in analog and mixed-signal circuit design, particularly in CMOS and Power Technologies; Good Analytical skills and very good understanding of Analog Design Familiarity with high-efficiency power conversion, such as DC DC converters, is highly desirable; Experience in post silicon debug ; Proficiency in computer-aided design tools and methodologies;

Location- Novo Nordisk Global Business Services (GBS), Ahmedabad, India Department- GCM Operations Drug Product Are you ready to take charge and make a difference in the pharmaceutical industryIf you’re a dynamic person with a passion for quality and operational efficiency, you might be our new Operations Manager. The position is based in Ahmedabad in India and will report directly to GCM organization based in Denmark. Apply today and get life changing career! Apply now! The position As an Operations Manager, you will be responsible for ensuring Novo Nordisk’s interests with regards to short to midterm capacity, compliance, quality, manufacturing readiness and activities at the CMO. You will have a substantial impact on the business with the CMO with regards to strategy input, prioritization and following up on agreed actions and improvements. Your other responsibilities will be to: Responsible for short to midterm capacity, compliance, quality, manufacturing readiness and activities at selected CMOs ensuring timely delivery of products to downstream customers with a strong focus on production performance and quality. Developing and following up on joint KPI’s and creating a robust working relation with the CMOs. Identify and implement changes and process improvements at CMOs in order to create a strong and solid foundation for future growth in this area. Develop new work standards and setups for collaboration between GCM DP and relevant CMO’s delivering aseptic manufacturing activities. Participate in project work to the extent needed to ensure new projects/CMOs enter operations in a satisfactory manner. Approximately 3–5 weeks of travel per year is expected as part of this role. Qualifications To be successful in this role, you should have: Master’s or Bachelor’s degree in Engineering, Pharmacy, or a Supply Chain-related field, with excellent written and verbal communication skills and a strong command of English 10 years of experience within pharmaceutical manufacturing / packaging and cGMP and 5 years of experience with outsourcing or managing global CMOs. Experience in Production, Manufacturing Operations, Project management or Supply Chain management. Experienced in handling Changes, Deviations, and Customer Complaints, with strong knowledge of regulatory guidelines in the pharmaceutical industry, excellent relationship management skills, and a solid understanding of GxP principles. Team player demonstrating collaborative behavior, effective communicator providing clear and timely information to stakeholders, with a technical, analytical, and structured approach to problem-solving. About the Department Global Contract Manufacturing Drug Products (GCM DP) oversees all aspects of commercial external production, including filling, assembly and packaging. We prioritize diversity, encourage empowerment, and pride ourselves with a varied workforce, comprising a range of professional profiles such as project managers, supply chain professionals, specialists and operation managers.

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field. As a digital ASIC R&D Engineer, you will play a vital role in addressing challenges with Performance, Power, and Area (PPA) scaling tradeoffs to qualify technology entitlement of advance process nodes. You will be responsible for research and develop methods to improve efficiency of digital design, power and chip quality/yield. The job scope includes design automation, Design-Device/process Interaction Analysis, post-silicon yield debug and data mining. Required Skills Coding with Python, Perl, TCL and/or C Strong fundamental and working knowledge of SPICE, Parametric Testing Basic fundamental of Post Si Bring Up/Wafer Probing and System Level Testing Strong fundamentals in CMOS Device Physics, Process Engineering & Digital Design Working knowledge of digital VLSI implementation (netlist to GDS) with expertise in STA Expected Experience 1 –3 years of relevant industry experience

Knowledge of Analog and Digital Circuit Design, Verilog, System Verilog, VHDL, FPGA, CMOS. Hands on experience with Simulation and Verification, Timing and Power Analysis industry Standard Tools. Knowledge of Electronic Design Automation tools

Join our team and unlock your potential in the world of Semiconductor. We are looking for #TrainedFresher and. #internship in #analogLayout. Preferred Qualifications:. Knowledge of SiGe and CMOS technology nodes 45/32/28nm and below is an advantage. Hands-on knowledge of state-of-the-art analog design flows and knowledge of ADC, DACs is a plus. Good publication and patent record. Dedication and the ability to work within a very dynamic interdisciplinary environment. Ability to communicate as well as work efficiently in an international multi-disciplinary environment.. Exceptional spoken and written Proficiency in English. Strong analytical and problem-solving skills.. Percentage : min 70%,. internship completed engineers with hands on exp on layout will be preferred. #Intern and #trained candidates only considerable.. Explore exciting career opportunities at www.Digicommsemi.com. Show more Show less

About the Role: We are seeking a talented and experienced Analog Layout Engineer to join our team in Bangalore. The ideal candidate will have a strong background in analog layout design and will contribute to the development of cutting-edge semiconductor products. If you are passionate about VLSI design and eager to work in a collaborative, innovation-driven environment, this opportunity is for you! Location: Bangalore Experience: 3 to 10 Years Employment Type: Full-Time Notice Period: 90 Days Key Responsibilities: 1. Design and implementation of custom analog and mixed-signal layouts for circuits such as amplifiers, ADC/DACs, PLLs, and more. 2. Perform layout verification tasks, including DRC, LVS, and parasitic extraction using industry-standard tools. 3. Optimize layout designs for performance, area, and power while ensuring compliance with design rules and process constraints. 4. Collaborate closely with circuit design engineers to interpret specifications and requirements. 5. Participate in design reviews and contribute to the enhancement of layout methodologies. 6. Work on advanced nodes, ensuring high-quality layouts for high-performance, low-power designs. Required Skills and Qualifications: 1. Experience: 3 to 10 years in analog layout design, with expertise in full-custom IC design. 2. Proficiency in layout tools such as Cadence Virtuoso, Synopsys Custom Compiler, or equivalent. 3. Strong knowledge of semiconductor process technologies, including FinFETs and advanced nodes (e.g., 7nm, 5nm). 4. Hands-on experience with parasitic-aware design, matching, and signal integrity. 5. Familiarity with EDA tools for verification, such as Calibre or Assura. 6. Excellent analytical and problem-solving skills with attention to detail. 7. Strong communication and interpersonal skills to work effectively in a team environment. What We Offer: 1. Competitive compensation package and benefits. 2. Opportunity to work on innovative and challenging projects. 3. Dynamic and collaborative work environment. 4. Career growth and learning opportunities.

As a Logic Design Engineer in the IBM Systems division, you wi be responsibe for the microarchitecture design and deveopment of features to meet Secure, high performance & ow power targets of the Mainframe and / or POWER customers. Deep expertise in the impementation of functiona units within the core / cache / Memory controer / Interrupt / crypto / PCIE / DLL Additiona responsibiities: ogic (RTL) design, timing cosure, CDC anaysis etc. Understand and Design Power efficient ogic. Agie project panning and execution. Masters in VLSI with demonstrated experience in the micro architecture and design of state of art Processor features to enhance high performance secure system performance. Required education Bacheor's Degree Preferred education Master's Degree Required technica and professiona expertise Minimum 8+ years of experience in Chip design and deveopment. Understand CPU / GPU / RISC V architectures. Expertise in one of the architecture and design of Core units (Fetch, Decode, arithmetic units -adders, mutipiers, L1/L2/L3 cache , Mem , IO ) Understand RISC V core Experience with VLSI Design in VHDL / Veriog