4 Clocksreset Jobs

As a member of the team at this organization, you will play a crucial role in the development of custom silicon solutions that will drive the future of Google's direct-to-consumer products. Your contributions will be instrumental in the innovation process that leads to the creation of products that are beloved by millions around the globe. Your expertise will be key in shaping the next generation of hardware experiences, ensuring exceptional performance, efficiency, and integration. With a Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience, and a minimum of 3 years of experience in Register-Transfer Level (RTL) design and integration using Verilog/System Verilog, microarchitecture, and automation, you are well-equipped to excel in this role. Additionally, you should have 3 years of experience with Register-Transfer Level quality check tool flows such as Lint, Clock Domain Crossing, Reset Domain Crossing, and Synthesis. Preferred qualifications include experience with methodologies for RTL quality checks, IP integration methodology, IP Design, ARM-based SoCs, ARM-protocols, and ASIC methodology. Additionally, experience with methodologies for low power estimation, timing closure, synthesis, and knowledge in areas such as Interconnects, Debug and Trace, Security, Interrupts, Clocks/Reset, Power/Voltage Domains, and Pin Multiplexing would be advantageous. Your responsibilities will involve defining microarchitecture details for the integration of Intellectual Property's (IPs) at the macro/Sub-System Workload Requirements Plan (SSWRP) level. You will be engaged in RTL development using SystemVerilog, debugging functional/performance simulations, and conducting RTL quality checks including Lint, Clock Domain Crossing (CDC), Synthesis, and Unified Power Format (UPF) checks. Furthermore, you will participate in synthesis, timing/power estimation, and FPGA/silicon bring-up processes. Join us in our mission to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create experiences that are radically helpful. By researching, designing, and developing new technologies and hardware, we aim to make computing faster, seamless, and more powerful, ultimately improving people's lives through technology.,

As an ASIC RTL Engineer at Google, you will be part of a team that is dedicated to developing custom silicon solutions for Google's direct-to-consumer products. Your role will involve pushing boundaries and contributing to the innovation that drives products loved by millions worldwide. Your expertise will play a crucial role in shaping the next generation of hardware experiences, focusing on delivering unparalleled performance, efficiency, and integration. In this role, you will lead a team of ASIC RTL engineers, overseeing sub-system and chip-level integration activities. Your responsibilities will include planning tasks, conducting code and design reviews, and developing complex features. You will collaborate closely with the architecture team to develop implementation strategies that meet quality, schedule, performance, power, and area requirements for sub-system/chip-level integration. Additionally, you will work with a cross-functional team comprising Verification, Design for Test, Physical Design, and Software teams. Your role will involve making design decisions and representing project status throughout the development process. Your contributions will be essential in ensuring the successful execution of projects and meeting the goals set for each stage of development. If you have a Bachelor's degree in Electrical Engineering or Computer Science, along with 8 years of experience in high-performance design and multi-power domains with clocking, and have worked on multiple SoCs with silicon success, this role could be an exciting opportunity for you. Experience with Verilog or System Verilog language is essential, and familiarity with ASIC design methodologies for front quality checks and chip design flow will be advantageous. Join us at Google, where we combine the best of Google AI, Software, and Hardware to create radically helpful experiences. Our mission is to make the world's information universally accessible and useful, and your contributions as an ASIC RTL Engineer will play a significant role in achieving this goal.,

As an Electrical Engineer or Computer Science professional with a Bachelor's degree and 3 years of experience in design, multi-power domains with clocking, and SoCs with silicon, you will have the opportunity to contribute to the innovation behind Google's direct-to-consumer products. Your expertise will be crucial in shaping the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration. Your responsibilities will include defining the microarchitecture of IPs, Subsystems, or SOCs, working with cross-functional teams to ensure quality, schedule compliance, and PPA optimized design. You will collaborate with Verification, Design for Test, Physical Design, and Software teams to make design decisions and represent project status throughout the development process. Additionally, you will define block-level design documents such as interface protocols, block diagrams, transaction flows, and pipelines. You will be responsible for RTL coding for SS/SOC integration, function/performance simulation debug, and Lint/CDC/FV/UPF checks. Working with key design collaterals such as SDC and UPF, you will negotiate the right collateral quality and identify solutions in collaboration with stakeholders. Preferred qualifications include a Master's degree or PhD in Electrical Engineering or equivalent practical experience, experience with chip design flow and cross-domain involving DV, DFT, Physical Design, and software. Experience in STA closure, DV test-plan review, and coverage analysis of the sub-system and chip-level verification will be advantageous. Knowledge in areas such as Processor Cores, Interconnects, Debug and Trace, Security, Interrupts, Clocks/Reset, Power/Voltage Domains, and Pin-muxing is also beneficial. Join a team that pushes boundaries and works towards developing custom silicon solutions that power the future of Google's products, loved by millions worldwide. Contribute your skills and expertise to create radically helpful experiences by combining the best of Google AI, Software, and Hardware. Be a part of a team that aims to make people's lives better through technology.,

As an ASIC RTL Engineer at Google, you will be part of a team that is dedicated to developing custom silicon solutions to power Google's direct-to-consumer products. Your role will involve contributing to the innovation that drives the creation of products loved by millions worldwide, shaping the next generation of hardware experiences for unparalleled performance, efficiency, and integration. Your responsibilities will include: - Contributing as an ASIC RTL engineer to sub-system and chip-level integration activities. This will involve task planning, conducting code and design reviews, and contributing to sub-system/chip-level integration. - Working closely with the architecture team to develop implementation strategies that meet quality, schedule, and power performance area requirements for sub-system/chip-level integration. - Collaborating with the subsystem team to plan SOC milestones, quality checks, and guide subsystem teams with SOC level requirements such as IPXACT, CSR, Lint, CDC, SDC, UPF, etc. - Engaging with a cross-functional team of verification, design for test, physical design, emulation, and software teams to make design decisions and provide project status updates throughout the development process. To be successful in this role, you should have a Bachelor's degree in Electrical Engineering, Computer Science, or equivalent practical experience. You should also have at least 3 years of experience in RTL coding using Verilog or SystemVerilog language, with experience in high-performance design, multi-power domains with clocking. Preferred qualifications include experience with multiple SoCs with silicon success, knowledge of ASIC design methodologies for front quality checks, and domain expertise in areas such as Process Cores, Interconnects, Debug and Trace, Security, Interrupts, Clocks/Reset, Power/Voltage Domains, PinMux. Additionally, an understanding of cross-domain activities involving domain validation, design for testing, physical design, and software will be beneficial. Join us at Google and be part of a team that combines the best of Google AI, Software, and Hardware to create radically helpful experiences. Help us research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful, ultimately aiming to make people's lives better through technology.,