6 Clocking Circuits Jobs

You are urgently hiring for the position of Analog Mixed Signal Design-Staff Engineer based in Hyderabad. With 7-10 years of experience, you will be responsible for various aspects of Analog and Mixed Signal Design, focusing on PMIC blocks like DC-DC converter (BUCK, BOOST), LDOs, and clocking circuits. Your role will involve circuit design, validation, mixed signal validation, and reliability validation. As an Analog Mixed Signal Design-Staff Engineer, you are expected to possess a strong understanding of CMOS design, active filter design, passive RC circuits, and switched cap circuits. You will work on high-speed digital circuit design and analysis, ensuring timing and flow closure. Additionally, you will utilize digitally assisted analog circuit and techniques to develop high-speed, low-power, and reliable analog and digital circuits for various areas of PLL. Your responsibilities will span across the design and development of cutting-edge foundry process development nodes. It is essential to have good knowledge of control systems, Bandgap reference, bias, op-amps, feedback, compensation techniques, and experience in LC VCO/DCO design. You will also gain exposure to the performance parameters of VCO and complete PLL architecture.,

Company Description Sandisk understands how people and businesses consume data and we relentlessly innovate to deliver solutions that enable todays needs and tomorrows next big ideas. With a rich history of groundbreaking innovations in Flash and advanced memory technologies, our solutions have become the beating heart of the digital world were living in and that we have the power to shape. Sandisk meets people and businesses at the intersection of their aspirations and the moment, enabling them to keep moving and pushing possibility forward. We do this through the balance of our powerhouse manufacturing capabilities and our industry-leading portfolio of products that are recognized globally for innovation, performance and quality. Sandisk has two facilities recognized by the World Economic Forum as part of the Global Lighthouse Network for advanced 4IR innovations. These facilities were also recognized as Sustainability Lighthouses for breakthroughs in efficient operations. With our global reach, we ensure the global supply chain has access to the Flash memory it needs to keep our world moving forward. Job Description Will be technically driving team Custom Circuit IO and Datapath solutions for next generation Memory in advanced CMOS technology nodes. Will work on architecture of High speed IO and DataPath solutions to meet the specifications and product requirements Work closely with team and actively participate in technical discussions and reviews. Pro-actively get design issues/problems solved. Contribute to or propose innovative design solutions and design methodologies. Qualifications Bachelors/Masters degree in Electronics & Telecommunication/Electrical engineering Hand-on design knowledge on both analog & mixed signal design environment. 8+ years of Experience on IO circuit blocks used in memory products like DDR4, DDR5, LPDDR4, LPDDR5, GDDR5, GDDR6 is desirable. Familiar with custom design methodology & flow, Calibration, JTAG design requirements, understanding of High-speed IO circuit and Datapath design including LDO, PLL, DLL, Rx, Tx and clocking circuits Knowledge of analog layout techniques, including floor-planning, matching, shielding and parasitic optimization Understanding Datapath circuits like pipelining, digital design, STA, fan-out and load estimation, FIFO design etc.. Familiarity with package/board/Power integrity /signal integrity constraints is a plus. Strong communication skills & circuit design knowledge is preferred. Tool knowledge: spice tools: spectre, finesim, hspice & other flows Good automation & scripting knowledge is plus. Additional Information Sandisk thrives on the power and potential of diversity. As a global company, we believe the most effective way to embrace the diversity of our customers and communities is to mirror it from within. We believe the fusion of various perspectives results in the best outcomes for our employees, our company, our customers, and the world around us. We are committed to an inclusive environment where every individual can thrive through a sense of belonging, respect and contribution. Sandisk is committed to offering opportunities to applicants with disabilities and ensuring all candidates can successfully navigate our careers website and our hiring process. Please contact us at [HIDDEN TEXT] to advise us of your accommodation request. In your email, please include a description of the specific accommodation you are requesting as well as the job title and requisition number of the position for which you are applying. Show more Show less

Company Description Sandisk understands how people and businesses consume data and we relentlessly innovate to deliver solutions that enable todays needs and tomorrows next big ideas. With a rich history of groundbreaking innovations in Flash and advanced memory technologies, our solutions have become the beating heart of the digital world were living in and that we have the power to shape. Sandisk meets people and businesses at the intersection of their aspirations and the moment, enabling them to keep moving and pushing possibility forward. We do this through the balance of our powerhouse manufacturing capabilities and our industry-leading portfolio of products that are recognized globally for innovation, performance and quality. Sandisk has two facilities recognized by the World Economic Forum as part of the Global Lighthouse Network for advanced 4IR innovations. These facilities were also recognized as Sustainability Lighthouses for breakthroughs in efficient operations. With our global reach, we ensure the global supply chain has access to the Flash memory it needs to keep our world moving forward. Job Description Will be technically driving team Custom Circuit IO and Datapath solutions for next generation Memory in advanced CMOS technology nodes. Will work on architecture of High speed IO and DataPath solutions to meet the specifications and product requirements Work closely with team and actively participate in technical discussions and reviews. Pro-actively get design issues/problems solved. Contribute to or propose innovative design solutions and design methodologies. Qualifications Bachelors/Masters degree in Electronics & Telecommunication/Electrical engineering Hand-on design knowledge on both analog & mixed signal design environment. 8+ years of Experience on IO circuit blocks used in memory products like DDR4, DDR5, LPDDR4, LPDDR5, GDDR5, GDDR6 is desirable. Familiar with custom design methodology & flow, Calibration, JTAG design requirements, understanding of High-speed IO circuit and Datapath design including LDO, PLL, DLL, Rx, Tx and clocking circuits Knowledge of analog layout techniques, including floor-planning, matching, shielding and parasitic optimization Understanding Datapath circuits like pipelining, digital design, STA, fan-out and load estimation, FIFO design etc.. Familiarity with package/board/Power integrity /signal integrity constraints is a plus. Strong communication skills & circuit design knowledge is preferred. Tool knowledge: spice tools: spectre, finesim, hspice & other flows Good automation & scripting knowledge is plus. Additional Information Sandisk thrives on the power and potential of diversity. As a global company, we believe the most effective way to embrace the diversity of our customers and communities is to mirror it from within. We believe the fusion of various perspectives results in the best outcomes for our employees, our company, our customers, and the world around us. We are committed to an inclusive environment where every individual can thrive through a sense of belonging, respect and contribution. Sandisk is committed to offering opportunities to applicants with disabilities and ensuring all candidates can successfully navigate our careers website and our hiring process. Please contact us at [HIDDEN TEXT] to advise us of your accommodation request. In your email, please include a description of the specific accommodation you are requesting as well as the job title and requisition number of the position for which you are applying. Show more Show less

You will be responsible for designing and leading the development of high-speed IP such as GDDR7, DDR5, and LPDDR6. As a strong individual contributor in the analog domain, you will actively participate in all aspects of development including analog design, layout, digital design, documentation, and silicon validation. Your role will also involve engaging in customer-facing discussions to address their requirements and concerns. To qualify for this position, you should hold a B.Tech / BE / ME / Mtech degree with at least 5 to 15+ years of experience. It is essential to have hands-on design experience and leadership skills in GDDR/DDR/LPDDR IPs. A successful candidate must have been involved in the entire cycle of analog IP creation, from specification to silicon debugging and characterization. Good communication skills and the ability to work effectively in a team are crucial for this role. Moreover, expertise in areas such as PLL, high-speed circuits like TX, RX, clocking circuits, etc., is mandatory. Experience with other common IP blocks like BGR, LDO, POC, temperature sensor, etc., would be considered advantageous.,

The ideal candidate should possess experience in Analog and Mixed Signal Design, focusing on PMIC blocks such as DC-DC converter (BUCK, BOOST), LDOs, and clocking circuits. A strong foundation in CMOS design and active filter design is essential for this role. Responsibilities will include circuit design, validation, mixed signal validation, and reliability validation. Exposure to PMIC designs, high-speed digital circuit design, and analysis with timing and flow closure is required. Additionally, knowledge of digitally assisted analog circuits and techniques is preferred. The candidate will be entrusted with developing high-speed, low-power, and reliable analog and digital circuits for various PLL areas. Proficiency in control systems, Bandgap reference, bias, op-amps, feedback, and compensation techniques is necessary. Joining an expanding analog/mixed-signal circuit design team involved in cutting-edge foundry process development nodes, the selected candidate will be expected to focus on Analog blocks and clocking circuits. Proficiency in CMOS design, passive RC circuits, and switched-cap circuits is crucial for success in this role. Task responsibilities will encompass circuit design, validation, mixed signal validation, and reliability validation. Additionally, the candidate should be adept in high-speed digital circuit design and analysis with timing and flow closure, as well as digitally assisted analog circuit and techniques. The role will involve the development of high-speed, low-power, and reliable analog and digital circuits for various PLL areas, requiring a good understanding of control systems, band gaps, bias, op-amps, LDOs, feedback, compensation techniques, as well as experience in LC VCO/DCO design. Exposure to VCO performance parameters and complete PLL architecture is highly desirable.,

Job Title: AMS Layout Design Engineer Job Description 90/130/150nm and higher node with PMIC layout experience. Performs layout and takes corrective actions in such a way that the final result meets all requirements as stated in the Design document, section layout, including all remarks from review, the customer and back annotation. Performs layout in such a way that the final result meets all general layout guidelines and matches 1-to-1 with parameter devices and hierarchy used in simulations. Create floorplan Performs DRC and takes corrective actions if needed until DRC is error free Performs LVS and takes corrective actions if needed until result is successful Performs layout in such a way that final result meets the foundry layout rules. Provides extracted netlist for back annotation to DE as specified in the Design document, section layout. Translates sub block schematics to sub block layouts, taking care of the same hierarchical build-up and respecting the guidelines of the Block review document, section layout. Adds extra useful information to the Block review document, section layout.