CPU Physical Design Verification(PDV) Engineer, Staff Qualcomm

8.0 - 12.0 years

0 Lacs

karnataka

On-site

Qualcomm India Private Limited is a leading technology innovator that pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment, packaging, test systems, FPGA, and/or DSP systems in order to launch cutting-edge, world-class products. Collaboration with cross-functional teams is essential to develop solutions and meet performance requirements. This position is focused on floor-planning expertise at both block and top levels for industry-leading CPU core designs, emphasizing scalability and achieving aggressive Power, Performance, and Area (PPA) targets. Working on cutting-edge technology nodes and applying advanced physical design techniques to enhance CPU performance and efficiency is a key aspect of this role. Key responsibilities include driving floorplan architecture and optimization in collaboration with PD/RTL teams, engaging in cross-functional collaboration with Physical design, timing, power, and packaging teams, partnering with EDA tool vendors and internal CAD teams for improved design efficiency, making strategic trade-offs in design decisions to achieve optimal PPA outcomes, and ensuring end-to-end Physical verification closure for subsystem. The ideal candidate will have experience in physical design including floor-planning, placement, clock implementation, and routing for complex, big, and high-speed designs. Knowledge of physical synthesis and implementation tools such as Cadence Innovus/Genus and Synopsys Fusion Compiler is preferred, along with a good understanding of CMOS circuit design, static timing analysis, reliability, and power analysis. Strong collaboration skills, innovative thinking for power and performance improvements, scripting skills, and expertise in Physical Verification flow are required. Preferred skills for this role include clock implementation, power delivery network design choices, process technology knowledge, experience in flow and methodology development, hands-on experience with Synthesis, DFT, Place and Route, and Timing and Reliability Signoff. Interaction with design and architecture teams, working with sub-micron technology process nodes, and prior experience in flow and methodology development are advantageous. Minimum qualifications include a Bachelor's degree in Electrical/Computer Engineering, 8+ years of direct top-level floor-planning experience, a strong background in VLSI design, physical implementation, and scripting, as well as experience working with industry-standard Synthesis and Place and Route tools. Self-motivation, time management skills, and a commitment to abide by all applicable policies and procedures are expected from applicants. Qualcomm is an equal opportunity employer committed to providing reasonable accommodations for individuals with disabilities during the application/hiring process. Staffing and recruiting agencies are advised not to submit unsolicited profiles, applications, or resumes. For more information about this role, please contact Qualcomm Careers.,

Posted 1 week ago

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