32 Clock Gating Jobs - Page 2

As a skilled ASIC/SoC Verification Engineer, you will be responsible for defining and implementing a power-aware verification strategy using UPF (IEEE 1801). Your role will involve integrating power intent into simulation environments, verifying power management features, and developing power-aware test benches and test cases in System Verilog/UVM. You will run simulations, debug failures, and ensure design functionality across power states. Collaboration with RTL designers and architects to ensure correct power domain partitioning and isolation will be a key aspect of your responsibilities. Additionally, you will perform static checks for power intent correctness using tools such as Synopsy...

As an ASIC Design Engineer specializing in UPF and Low Power Design, you will be responsible for owning and driving RTL design for complex digital blocks with multiple power domains. Your role will involve defining, implementing, and validating power intent using UPF 2.0/3.0 for ASIC and SoC designs. Collaboration with verification and physical design teams will be crucial to ensure correct propagation and verification of power intent across the flow. You will work closely with architecture teams to define low power design strategies including power gating, clock gating, and multi-voltage domains. Additionally, analyzing and debugging power-related issues during RTL and gate-level simulation...

As a Silicon Design Engineer 2 at AMD, your role involves collaborating with formal experts and designers to verify formal properties and drive convergence. You will have the opportunity to work on modern, complex processor architecture, digital design, and verification in a team-oriented environment. Your strong analytical and problem-solving skills will be pivotal in understanding design specifications and creating scenarios to verify the design effectively. Communication skills are essential as you coordinate with RTL engineers to implement logic design for improved clock gating and verify different aspects of the design. Your responsibilities will include writing tests, sequences, and te...

Sr. Engineer - ASIC Digital Design (Physical Implementation/Design/STA, 2+ years of exp) We Are: At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation. You Are: You are a highly skilled and experienced ASIC Digital Design Engineer passionate about working on the latest processes for STA and physical implementation flows on cutting-edge technology node...

As a candidate for this position, you should hold a Bachelor's degree in Electronics or Computer Engineering/Science, or possess equivalent practical experience. With a minimum of 8 years of experience in SoC power modeling and analysis, you should also have a solid understanding of SOC architecture and power techniques. A Master's degree or PhD in Electronics, Computer Engineering, or Computer Science would be considered a preferred qualification. Additionally, experience with ASIC design flows and knowledge of low power architecture and power optimization techniques such as multi Vth/power/voltage domain design, clock gating, power gating, and Dynamic Voltage Frequency Scaling would be adv...

We are seeking a skilled and detail-oriented Engineer specializing in Synthesis, Physical Synthesis, and pre-layout Static Timing Analysis (STA). The ideal candidate will have strong expertise in various aspects of digital design implementation, including UPF generation, synthesis optimizations, and constraint development. This role is crucial for ensuring the functional correctness, performance, and power efficiency of our semiconductor designs. Key Responsibilities: Perform Synthesis, Physical Synthesis, and pre-layout Static Timing Analysis (STA) for complex digital designs. Responsible for UPF (Unified Power Format) generation from scratch to define power intent for low-power designs. Ex...

Qualcomm India Private Limited is looking for a passionate STA and Synthesis Engineer to join their Engineering Group in Chennai. As an integral part of the cross-functional engineering teams, you will be engaged in all phases of design and development cycles, specifically focusing on Synthesis, Static Timing Analysis, and LEC of SoC/Cores. Your responsibilities will include full chip and block level timing closure, IO budgeting for blocks, logical equivalence checks between RTL to Netlist and Netlist to Netlist, as well as implementing low-power techniques such as clock gating, power gating, and MV designs. Additionally, you will be involved in ECO timing flow and should be proficient in sc...