ASIC Physical Design, Sr Engineer Synopsys Inc

2.0 - 4.0 years

0 Lacs

noida, uttar pradesh, india

On-site

Alternate Job Titles: Senior ASIC Physical Design Engineer Physical Implementation Engineer Senior Level IC Physical Design Specialist Senior SoC Physical Design Engineer We Are: At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation. You Are: You are a passionate and driven engineer with a solid foundation in integrated circuit (IC) design and physica...

Posted 1 month ago

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Senior Physical Design Lead Engineer ACL Digital

8.0 - 12.0 years

0 Lacs

karnataka

On-site

You should be a PNR Lead with over 8 years of experience, based in Bangalore. Your role will involve handling Full chip PnR tasks such as timing, congestion, and CTS issues, with an understanding of IO ring, package support, and multi-voltage design. It is crucial to have a deep understanding of synthesis, place & route, CTS, timing convergence, IR/EM checks, and signoff DRC/LVS closure. Your responsibilities will include independently planning and executing all aspects of physical design, such as floor planning, place and route, Clock Tree Synthesis, Clock Distribution, extraction, Timing closure, Power and Signal Integrity Analysis, Physical Verification, and DFM. You must have experience ...

Posted 3 months ago

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Principal Engineer, Physical Design Clocking Intel Corporation

18.0 - 22.0 years

0 Lacs

karnataka

On-site

You will be part of the SoC Clocking team, focusing on next-generation Networking and Edge SoC designs. Your responsibilities will include product pathfinding, end-to-end clocking architecture, clock distribution, and overseeing SoC clock implementation and Sign off. You should have experience in SoC Clock Architecture, clock distribution, and system-level clocking. Additionally, hands-on experience with spice, clock jitter simulations, and different jitter components is required. You will work on clocking methodologies and guidelines for IPs or SoCs and create scalable flows for clocking infrastructure to enhance performance and power in the design. Collaboration with Platform, package, IP,...

Posted 3 months ago

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