Senior Physical Design Lead Engineer ACL Digital

8.0 - 12.0 years

0 Lacs

karnataka

On-site

You should be a PNR Lead with over 8 years of experience, based in Bangalore. Your role will involve handling Full chip PnR tasks such as timing, congestion, and CTS issues, with an understanding of IO ring, package support, and multi-voltage design. It is crucial to have a deep understanding of synthesis, place & route, CTS, timing convergence, IR/EM checks, and signoff DRC/LVS closure. Your responsibilities will include independently planning and executing all aspects of physical design, such as floor planning, place and route, Clock Tree Synthesis, Clock Distribution, extraction, Timing closure, Power and Signal Integrity Analysis, Physical Verification, and DFM. You must have experience participating in all design stages including floor planning, placement, CTS, routing, physical verification, and IREM. Furthermore, your expertise should cover timing closure methodologies, DRC, LVS, ERC, and PERC rule files for lower tech node layout verification. Experience in lower tech nodes (<7nm) is required, along with strong automation skills in PERL, TCL, and EDA tool-specific scripting. You should be capable of taking complete ownership of a Block/sub-system throughout the execution cycle and possess out-of-the-box thinking to meet tighter PPA requirements.,

Posted 2 days ago

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Principal Engineer, Physical Design Clocking Intel Corporation

18.0 - 22.0 years

0 Lacs

karnataka

On-site

You will be part of the SoC Clocking team, focusing on next-generation Networking and Edge SoC designs. Your responsibilities will include product pathfinding, end-to-end clocking architecture, clock distribution, and overseeing SoC clock implementation and Sign off. You should have experience in SoC Clock Architecture, clock distribution, and system-level clocking. Additionally, hands-on experience with spice, clock jitter simulations, and different jitter components is required. You will work on clocking methodologies and guidelines for IPs or SoCs and create scalable flows for clocking infrastructure to enhance performance and power in the design. Collaboration with Platform, package, IP, and SoC design teams is essential to drive best-in-class clocking solutions. A good understanding of Physical design and SoC timing analysis would be beneficial. Proficiency in Perl, TCL Scripting Skills is necessary. Qualifications - Bachelors (B.Tech) or Masters (M.Tech) in Electrical Engineering or related areas. - At least 18+ years of experience in SoC clock architecture, clock distribution, and clock implementation. - Hands-on experience with Synopsys, cadence APR/Clock implementation tools. - Good understanding of System-level clocking. - Proficient in scripting languages (Tcl, Perl, Python). - Ability to communicate effectively with multiple global cross-functional teams. This is an Experienced Hire job role with a requirement for on-site presence at Shift 1 (India). The primary location for this role is in India, Bangalore. Xeon and Networking Engineering (XNE) business group focuses on the development and integration of XEON and Networking SOC's and critical IP's to sustain Intel's Xeon and 5G networking roadmap. Please note that this role is a Position of Trust, requiring consent to and successful completion of an extended Background Investigation, which includes various checks. The work model for this role is subject to change.,

Posted 6 days ago

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