3.0 - 8.0 years

3 - 8 Lacs

Hyderabad / Secunderabad, Telangana, Telangana, India

On-site

Designing and optimizing standard cell libraries to achieve targeted PPA. Developing complex circuits including flip-flops, clock gating cells, level shifters, and power gating cells. Collaborating with layout designers to optimize layout parasitics. Engaging in layout extraction and understanding layout-dependent parameters. Conducting timing and power characterization of standard cells. Working closely with cross-functional teams for optimization across the design chain. The Impact You Will Have: Enhancing the performance, power, and area of standard cell libraries. Contributing to the development of high-impact, cutting-edge technology. Driving innovation in complex circuit design and opt...

Posted 3 months ago

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