431 Chip Design Jobs - Page 15

Developing CMOS embedded memories such as SP SRAM, DP SRAM, Register File, TCAM, and ROM. Leading and mentoring a team of engineers, enhancing workflows and methodologies. Designing architecture and circuit implementation for ultra-high-speed, ultra-low-power, or high-density designs. Performing schematic entry, circuit simulation, layout planning, and supervision. Verifying and validating designs to ensure high quality and performance. Interfacing with CAD and Frontend engineers to automate memory compilers and generate EDA models. Developing and verifying bit cells, driving physical layout design and verification. Providing support and performing additional duties as required. The Impact Y...

Reviewing Die, package, and PCB physical layout designs Modeling, simulating, and verifying high-speed interface performance against specifications Participating in the improvement of SI/PI methodology flows Collaborating and networking with other teams on task-oriented projects Independently driving SI/PI research and development activities Ensuring designs meet stringent performance, power, and size requirements The Impact You Will Have: Enhance the performance and reliability of high-speed interfaces Contribute to the development of cutting-edge technology in chip design Improve SI/PI methodology flows, increasing efficiency and accuracy Foster collaboration and innovation across globally...

Take ownership and drive on-time delivery of patches and releases for small products. Assist other Release Managers on larger products and assignments. Independently drive commitments and convergence of patches and releases as per established processes, welcoming new ideas. Act as the interface between R&D, DevOps, management, and Application Engineers. Utilize excellent interpersonal, communication, and follow-up skills to ensure team collaboration and success. Apply hands-on experience in C/C++ software development to enhance project outcomes. The Impact You Will Have: Ensure timely delivery of product patches and releases, contributing to overall project success. Support the scalability a...

Design and develop software for interface IP systems Perform Device level and System level, validation and debug, in post-silicon Software Development for new validation methodologies Customer interface to capture requirement and post release support Maximize software productivity and faster time to knowledge Qualifications: Qualification: B.Tech in ECE/CS or equivalent with 4+ year of relevant experience ECE background with experience is software is preferred Skills: Excellent programming and testing skills using C/C++ Experience with embedded or resource-constrained environments Development experience on Unix, Linux and Windows Ability to pick up new flow, learn on the Job MATLAB & PYTHON ...

Designing software to support large-scale geometric data analysis and high-performance computing for OPC solutions. Optimizing infrastructure for distributed computing, ensuring seamless GPU integration. Collaborating with development teams to ensure efficient data handling and computational resource allocation. Debugging and troubleshooting infrastructure issues related to production line integration. Maintaining and troubleshooting the tool to meet performance and scalability requirements. Regularly contributing to the cutting-edge of semiconductor development by enhancing software performance and scalability. The Impact You Will Have: Advancing the development of high-performance silicon ...

Leading the development of next-generation DDR/HBM/UCIe IP. Providing guidance and mentorship to team members, ensuring project schedules are met and problems are resolved efficiently. Acting as a project leader, contributing to complex aspects of IP development. Developing and maintaining project schedules, collaborating with cross-functional teams. Designing and verifying CMOS circuits and layouts. Implementing analog mixed-signal simulation strategies and ensuring signal integrity. The Impact You Will Have: Driving the development of cutting-edge IP that powers the future of technology. Enhancing the capabilities of SoCs, enabling faster integration and reduced risk for customers. Contrib...

* Collaborate with cross-function al teams to develop and implement layout designs for analog and mixed-signal (A&MS) integrated circuits. * Create and optimize layout designs using industry-stand ard EDA tools. * Perform physical verification and design rule checks to ensure design integrity and manufacturabil ity. * Participate in design reviews and provide feedback to improve design quality. * Work closely with circuit designers to understand design specifications and constraints. * Contribute to the development and enhancement of layout design methodologies and best practices. * Stay updated with the latest industry trends and advancements in A&MS layout design. The Impact You Will Have:...

Developing CMOS embedded memories such as SP SRAM, DP SRAM, Register File, and ROM. Designing architecture and circuit implementation, focusing on ultra-high speed, ultra-low power, or high-density design portfolios. Performing schematic entry, circuit simulation, layout planning, layout supervision, design verification, and validation. Interfacing with CAD and Frontend engineers for memory compiler automation, EDA model generation, and full verification flow. Performing bit cell development and verification, and driving physical layout design and verification. Providing support and/or performing other duties as assigned and required. The Impact You Will Have: Driving innovation in CMOS embe...

Design and develop analog/mixed-signal blocks for PCIe 6 and PCIe 7 PHY designs. Ensure designs meet PCIe protocol standards, optimizing for performance, power, and area targets. Support the porting of PHY designs to different technology nodes, maintaining signal integrity and performance. Collaborate with cross-functional teams to integrate analog circuits into larger SerDes PHY systems. Implement verification strategies for high-speed analog/mixed-signal circuits using advanced simulation tools. Work closely with physical layout teams to minimize parasitics, device stress, and process variation impacts. Analyze simulation and measurement data for design validation and compliance with PCIe ...

An Emulation Expert with deep knowledge of IP interfaces such as PCIe and DDR, and experience with Zebu. You have a proven track record in IP product development focused on emulation and verification. You thrive in a matrixed, international, and team-oriented environment with multiple stakeholders. Your hands-on approach, collaborative mindset, and proactive attitude drive results. You are passionate about right-first-time development, ensuring traceability of all verification requirements and covering the entire ecosystem of Controller and PHY. What You ll Be Doing: Bridging and closing gaps between the available or required Emulation IP feature set and the Design IP verification of all its...

Developing SignOff ECO optimization algorithms and heuristics. Debugging issues related to design loading and timing/power optimization. Striving for continuous improvements in QoR to achieve faster timing convergence with optimal power overhead. Collaborating with a team of engineers to develop technical solutions to complex problems. Communicating with product engineers to understand and define problem scope. Ensuring strict performance and quality requirements are met. The Impact You Will Have: Enhancing the performance and efficiency of PrimeClosure, the industrys first AI-driven signoff ECO solution. Contributing to the development of cutting-edge algorithms that optimize timing and pow...

An experienced Verification Engineer who is passionate about technology and innovation. You are a problem-solver at heart with a strong foundation in digital design concepts and hands-on experience in programming with C++ and HDL languages. You thrive in collaborative environments and are comfortable taking on individual contributor or tech-lead roles. You are eager to work on cutting-edge technology, particularly in the field of emulation mode development and deployment for Zebu. Your technical expertise is complemented by excellent communication skills and a team-oriented mindset. What You ll Be Doing: * Developing and deploying emulation models for Zebu, focusing on bus protocols like PCI...

You are a highly skilled and motivated GenAI/LLM Researcher/Engineer with a passion for pioneering advancements in the field of General Artificial Intelligence and Large Language Models. With a strong foundation in AI/ML and software development, you are adept at leveraging your expertise to revolutionize the Electronic Design Automation (EDA) domain. Your in-depth understanding of UVM and EDA tools is complemented by your ability to collaborate effectively with cross-functional teams. You thrive in a dynamic environment, where your innovative mindset and problem-solving abilities drive the development of cutting-edge solutions. Your proactive approach to staying updated with industry trends...

At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation. You Are: Strong desire to learn and explore new technologies. Demonstrates good analysis and problem-solving skills. Prior knowledge and experience in tools like DC, ICC2, PT-SI,FC is a definite advantage. Should be a strong team player, excellent communicator as the role involves daily technical ...

Implementing and power signoff of world-class DDRs at cutting-edge technology nodes. Achieving timing closure above ~2GHz and integrating mixed signal macro IPs. Building efficient clock trees with very tight skew balancing. Providing regular updates to your manager on project status. Guiding junior peers with aspects of their job and contributing to their development. Representing the organization on business unit and/or company-wide projects. The Impact You Will Have: Driving the implementation of cutting-edge DDR technology, contributing to the advancement of high-performance computing. Ensuring the power efficiency and performance of our silicon chips, crucial for our competitive edge. E...

Floor planning, power planning, placement, and optimization Clock tree building and optimization Routing and optimization Timing constraints closure, synthesis, and formal verification Extraction, IR drop analysis, EM analysis, and signal integrity Physical verification and flow development for advanced technology nodes The Impact You Will Have: Enhance the best practices of the physical design flow Contribute to the successful implementation of high-performance digital designs Drive innovations in low-power design and high-speed clock distribution Ensure the integrity and reliability of complex IC designs Support the development of cutting-edge technology that shapes the future Collaborate ...

At minimum, a Bachelor s degree in engineering is required with 12+ years of digital design experience using Verilog. Strong background in RISC architectures required. Working experience in RISC microprocessor IP design, programming at assembly and C/C++ level, DSP skills, an understanding of multi-core architectures and development techniques are a plus. Experience with multi-site development is helpful. The successful candidate is expected to: Design embedded RISC microprocessor IP at architectural and RTL level Write High-level architecture and micro-architecture specifications of the design Optimize design for performance, speed, area and power, generate hardware benchmarks and analyze r...

You are a seasoned professional with a passion for analog design and a knack for solving complex problems With a strong foundation in CMOS processes and deep submicron technologies, you bring a wealth of knowledge and experience to the table You thrive in a collaborative environment, where your excellent communication skills enable seamless interactions with internal development teams You are adept at executing circuit design tasks with precision, ensuring the highest product quality and efficiency Your familiarity with ASIC design flow and JEDEC standards for DDR interfaces sets you apart, and you are always eager to learn and adapt to new challenges Your technical acumen, combined with you...

As an ideal candidate, you are a passionate and highly skilled engineer with a keen interest in ASIC physical design. You possess a strong foundation in electronics engineering or computer science, ideally with a Bachelors degree and a minimum of 3 years of related experience. You have a methodical approach to problem-solving and are proficient in scripting languages like Unix, Perl, and TCL. Your exposure to Verilog/VHDL and understanding of microprocessor design make you a valuable asset to any team. You are a team player with excellent written and verbal communication skills, capable of working in a collaborative international environment. Your enthusiasm for learning and applying new tec...

Implementing DDR and HBM PHYs for customer ASICs and SOCs in the DDR and HBM PHY Hardening service line. Performing synthesis, physical design, verification, design for test, and ATPG. Contributing as a senior member of a design team or as a project design engineer working with both internal and external design teams. Providing regular updates to the manager on project status. Representing the organization on business unit and/or company-wide projects. Guiding more junior peers with aspects of their job and frequently networking with senior internal and external personnel in your area of expertise. The Impact You Will Have: Enhancing the reliability and performance of DDR and HBM PHYs for cu...

Hands-on experience of implementing digital block using state of the art gate to GDSII ASIC flows mainly including Design Initialization, Power planning, Floor planning/Macro placement, Scan-chain reordering, CTS, Route and chip finishing steps Perform Physical Implementation of blocks starting from gate netlist till gds out Perform signoff verifications including Layout verifications (DRC, LVS, Antenna) and Reliability verifications (EMIR, ESD) of the implemented blocks Ownership of writing MCMM and UPF for the block designs Provide handoff data to other signoff closure like STA, Formality, Layout and Reliability verification Job Requirements In-depth understanding of the ASIC Physical desi...

As Staff Application Engineer (AE) , you will be Working on latest Synopsys implementation technologies ( Machine Learning , Physical Synthesis , Multi Source CTS etc ) to solve complex PPA challenges faced by Synopsys customers. Working on benchmarks to displace competition implementation solutions Working with customers to develop and debug RTL-GDS implementation methodologies and flows. Providing technical solutions by identifying the design and/or EDA tool issues and provide appropriate solution for customers Effectively translate the findings into requirements for R&D to improve both tool behaviour with enhancements as adaptive long-term solutions. Involved in deployment of new technolo...

Our Silicon IP business is all about integrating more capabilities into an SoC faster. We offer the world s broadest portfolio of silicon IP predesigned blocks of logic, memory, interfaces, analog, security, and embedded processors. All to help customers integrate more capabilities. Meet unique performance, power, and size requirements of their target applications. And get differentiated products to market quickly with reduced risk. Responsibilities: DDR I/O Circuit design Requirements- Qualification: BTech/MTech Skills/Experience: MTech+3years / BTech+5years Knowledge of CMOS processes and issues in deep submicron process technologies. CMOS circuit design and layout methodology & flow; basi...

Working on benchmarks to displace competition implementation solutions. Working on developing and debugging RTL-GDS implementation methodologies and flows. Providing technical solutions by identifying the design and/or EDA tool issues and provide an appropriate solution for customers. Effectively translate the findings into requirements for R&D to improve both tool behavior with enhancements as adaptive long-term solutions. Involved in deployment of new technologies on latest EDA versions and enable customers to migrate to newer versions achieving best PPA. Coming up with a proactive understanding of customers pain point and coming up with innovative solutions to address the same. Closely in...

Application Engineering : Staff Engineer , you will be Working on latest Synopsys implementation technologies ( Machine Learning , Synthesis, Physical Synthesis , Multi Source CTS etc ) to solve complex PPA challenges faced by Synopsys customers Working on benchmarks to displace competition implementation solutions Working on developing and debugging RTL-GDS implementation methodologies and flows by collaborating with key stake holders Providing technical solutions by identifying the design and/or EDA tool issues and provide appropriate solution for customers Effectively translate the findings into requirements for R&D to improve both tool behaviour with enhancements as adaptive long-term so...