291 Chip Design Jobs - Page 11

You are a seasoned professional with a passion for analog design and a knack for solving complex problems With a strong foundation in CMOS processes and deep submicron technologies, you bring a wealth of knowledge and experience to the table You thrive in a collaborative environment, where your excellent communication skills enable seamless interactions with internal development teams You are adept at executing circuit design tasks with precision, ensuring the highest product quality and efficiency Your familiarity with ASIC design flow and JEDEC standards for DDR interfaces sets you apart, and you are always eager to learn and adapt to new challenges Your technical acumen, combined with your dedication and innovative mindset, makes you an ideal fit for our team What You ll Be Doing: - Ownership of complete physical implementation at block level & chip level. Responsible for delivering timing clean blocks/chip level that meet design targets. - DRC, LVS & IR closure. Evaluates all aspects of the physical design flow from place and route, timing, PV & IR and is able to setup these flows. - Experience in all chip level tasks (P&R, STA, PV, IR) . Work closely with the frontend design team to resolve design issues . The Impact You Will Have: * Enhancing the performance and efficiency of our silicon IP portfolio. * Contributing to the rapid integration of advanced capabilities into SoCs. * Reducing the time-to-market and risk for our customers products. * Driving innovation in analog design and setting new industry standards. * Strengthening Synopsys position as a leader in chip design and verification. * Empowering the development of high-performance, differentiated products. What You ll Need: - Candidates with MSEE/BSEE with 5+ years of related experience. Possesses in depth understanding of specialization area plus working knowledge of one other related area. - Resolves issues in creative ways. - Exercises judgement in selecting methods and techniques to obtain solutions. - Executes project responsibilities from start to completion. - Contributes to moderately complex aspects of a project. - Determines and develops recommendations to solutions. - Works on team-driven or task-oriented projects. - May guide more junior peers with aspects of their job. - Networks with senior internal and external personnel in own area of expertise. - Strong knowledge on scripting using tcl, perl . Who You Are: * A collaborative team player with a proactive approach. * Detail-oriented with a commitment to quality and efficiency. * Innovative and adaptable, always seeking to learn and grow. * Effective communicator, able to convey technical information clearly. * Problem-solver with strong analytical skills.

As an ideal candidate, you are a passionate and highly skilled engineer with a keen interest in ASIC physical design. You possess a strong foundation in electronics engineering or computer science, ideally with a Bachelors degree and a minimum of 3 years of related experience. You have a methodical approach to problem-solving and are proficient in scripting languages like Unix, Perl, and TCL. Your exposure to Verilog/VHDL and understanding of microprocessor design make you a valuable asset to any team. You are a team player with excellent written and verbal communication skills, capable of working in a collaborative international environment. Your enthusiasm for learning and applying new technologies drives you to continuously improve and contribute to cutting-edge projects. What You ll Be Doing: Contributing to the physical design and implementation of our highly optimized hardware IP for the ARC family of configurable processors. Working on the full SOC design cycle with a focus on physical design tasks, including floorplanning, placement, routing, and timing closure. Collaborating with cross-functional teams to ensure the successful integration and verification of our microprocessor IP. Assisting in customer sales and design-ins of our IP by providing technical support and expertise. Participating in in-house test chip designs and development platforms to explore potential applications of our microprocessor IP. Engaging in benchmarking and qualification activities to ensure the highest performance and reliability of our products. The Impact You Will Have: Enhancing the performance and efficiency of our microprocessor IP through innovative physical design techniques. Contributing to the development of state-of-the-art embedded designs used in various high-tech applications. Supporting the successful deployment of our IP in customer projects, leading to high customer satisfaction and repeat business. Driving continuous improvement in our implementation flows and methodologies. Helping Synopsys maintain its leadership position in the semiconductor industry by delivering top-quality products. Fostering a collaborative and innovative work environment by sharing your expertise and learning from others. What You ll Need: Bachelor s degree in electronics engineering or computer science; a Master s degree is a plus. Minimum of 3 years of related experience in ASIC physical design. Proficiency in Unix, Perl, and TCL scripting. Exposure to Verilog/VHDL and understanding of microprocessor design. Strong written, verbal, and methodical skills. Who You Are: A collaborative team player with excellent communication skills. A methodical problem-solver with a keen attention to detail. Enthusiastic about learning and applying new technologies. Adaptable and able to work in an international, multi-disciplinary team. Dedicated to continuous improvement and innovation.

Implementing DDR and HBM PHYs for customer ASICs and SOCs in the DDR and HBM PHY Hardening service line. Performing synthesis, physical design, verification, design for test, and ATPG. Contributing as a senior member of a design team or as a project design engineer working with both internal and external design teams. Providing regular updates to the manager on project status. Representing the organization on business unit and/or company-wide projects. Guiding more junior peers with aspects of their job and frequently networking with senior internal and external personnel in your area of expertise. The Impact You Will Have: Enhancing the reliability and performance of DDR and HBM PHYs for customer ASICs and SOCs. Contributing to the success of complex projects through innovative problem-solving and technical expertise. Ensuring timely delivery of high-quality design solutions to our customers. Improving the efficiency and effectiveness of the design process through your autonomous judgment and technical knowledge. Strengthening Synopsys position as a leader in chip design and verification through your contributions. Mentoring and guiding junior team members, fostering a collaborative and innovative team environment. What You ll Need: A minimum of 5+ years of related experience in ASIC Physical Design. Proficiency in state-of-the-art CAD tools such as DC, PT, ICC2/FC, and ICV. Experience with advanced technologies like FinFet. Strong problem-solving skills and the ability to autonomously resolve a wide range of issues. Excellent verbal and written communication skills. Who You Are: An innovative thinker with a passion for technology and continuous learning. A collaborative team player who excels in a dynamic and fast-paced environment. A mentor and guide for junior team members. A strong communicator with the ability to network effectively with senior personnel. A composed and reliable professional who can handle risks and uncertainty with ease.

Hands-on experience of implementing digital block using state of the art gate to GDSII ASIC flows mainly including Design Initialization, Power planning, Floor planning/Macro placement, Scan-chain reordering, CTS, Route and chip finishing steps Perform Physical Implementation of blocks starting from gate netlist till gds out Perform signoff verifications including Layout verifications (DRC, LVS, Antenna) and Reliability verifications (EMIR, ESD) of the implemented blocks Ownership of writing MCMM and UPF for the block designs Provide handoff data to other signoff closure like STA, Formality, Layout and Reliability verification Job Requirements In-depth understanding of the ASIC Physical design flow steps of starting from Gate netlist Experience in Testchip implementation and testing exposure is a plus Exposure to Synopsys Tool set (such as FC/ICC2, Primetime, Formality, ICV) is highly desirable Exposure to FinFET designs is desirable Experience in working on IO integration with Wire-bond or Flip-chip design would be big plus Experience : Min 5 years of Relevant Physical design domain Education : B.E/B.Tech/M.Tech in ECE/EE

As Staff Application Engineer (AE) , you will be Working on latest Synopsys implementation technologies ( Machine Learning , Physical Synthesis , Multi Source CTS etc ) to solve complex PPA challenges faced by Synopsys customers. Working on benchmarks to displace competition implementation solutions Working with customers to develop and debug RTL-GDS implementation methodologies and flows. Providing technical solutions by identifying the design and/or EDA tool issues and provide appropriate solution for customers Effectively translate the findings into requirements for R&D to improve both tool behaviour with enhancements as adaptive long-term solutions. Involved in deployment of new technologies on latest EDA versions and enable customers to migrate to newer versions achieving best PPA. Coming up with proactive understanding of customers pain point and come up with innovative solutions to address the same. Closely interacting with Synopsys R&D team and product development team to develop future technologies This role requires you to act as customers advocate while talking to inhouse R&D and be a product brand ambassador while engaging with customers. Requirements At-least 5 years of experience in Physical Implementation RTL-GDS. Experience in unsupervised debugging and resolving synth & PnR implementation challenges. Candidate must have good exposure towards methodology changes to achieve targeted PPA metrics for complex designs. Proficiency in Synopsys implementation tools is an advantage The person must be self-motivated and dedicated with solid debug skills. Requires proficiency in scripting (tcl / Unix / Perl / Python). Excellent communication skills including ability to interface with customers and business unit personnel are essential. Who You Are: * Proactive and solution-orien ted with a strong problem-solvin g mindset. * Excellent communicator, able to convey technical information clearly and effectively. * Collaborative team player with strong interpersonal skills. * Adaptable and able to thrive in a fast-paced, dynamic environment. * Committed to continuous learning and professional development.

Our Silicon IP business is all about integrating more capabilities into an SoC faster. We offer the world s broadest portfolio of silicon IP predesigned blocks of logic, memory, interfaces, analog, security, and embedded processors. All to help customers integrate more capabilities. Meet unique performance, power, and size requirements of their target applications. And get differentiated products to market quickly with reduced risk. Responsibilities: DDR I/O Circuit design Requirements- Qualification: BTech/MTech Skills/Experience: MTech+3years / BTech+5years Knowledge of CMOS processes and issues in deep submicron process technologies. CMOS circuit design and layout methodology & flow; basic understanding of analog/mixed signal circuitry, familiarity with basic ESD concepts is an advantage. Familiarity with ASIC design flow. Knowledge of JEDEC requirements for DDR interfaces & standards, DDR Timing, ODT and SDRAM functionality would be a plus. Ability to execute assigned circuit design tasks with best product quality and efficiency. Good written and verbal communication skills in interactions with internal development teams.

Working on benchmarks to displace competition implementation solutions. Working on developing and debugging RTL-GDS implementation methodologies and flows. Providing technical solutions by identifying the design and/or EDA tool issues and provide an appropriate solution for customers. Effectively translate the findings into requirements for R&D to improve both tool behavior with enhancements as adaptive long-term solutions. Involved in deployment of new technologies on latest EDA versions and enable customers to migrate to newer versions achieving best PPA. Coming up with a proactive understanding of customers pain point and coming up with innovative solutions to address the same. Closely interacting with Synopsys R&D team and product development team to develop future technologies. This role requires you to act as customers advocate while talking to inhouse R&D and be a product brand ambassador while engaging with customers. The candidate must have good exposure to methodology changes to achieve targeted PPA metrics for complex designs. At least 5 years of experience in Physical Implementation RTL-GDS. Experience in autonomously debugging and resolving synth & PnR implementation challenges. Proficiency in Synopsys implementation tools is an advantage. The individual must be self-motivated and dedicated with strong debugging skills. Requires proficiency in scripting (tcl / unix / perl). Excellent communication skills including the ability to interface with customers and business unit personnel are essential.

Application Engineering : Staff Engineer , you will be Working on latest Synopsys implementation technologies ( Machine Learning , Synthesis, Physical Synthesis , Multi Source CTS etc ) to solve complex PPA challenges faced by Synopsys customers Working on benchmarks to displace competition implementation solutions Working on developing and debugging RTL-GDS implementation methodologies and flows by collaborating with key stake holders Providing technical solutions by identifying the design and/or EDA tool issues and provide appropriate solution for customers Effectively translate the findings into requirements for R&D to improve both tool behaviour with enhancements as adaptive long-term solutions. Involved in deployment of new technologies on latest EDA versions and enable customers to migrate to newer versions achieving best PPA Coming up with proactive understanding of customers pain point and come up with innovative solutions to address the same. Closely interacting with Synopsys R&D team and product development team to develop future technologies This role requires you to act as customers advocate while talking to inhouse R& D, and be a product brand ambassador while engaging with customers. Requirements At-least 5+ years of experience in Physical Implementation RTL-GDS. Experience in independently debugging and resolving Synth & PnR implementation challenges. Ability to handle complete project independently through timely successful outcome.. Candidate must have good exposure towards methodology changes to achieve targeted PPA metrics for complex designs. Proficiency in Synopsys implementation tools is an advantage The individual must be self-motivated and dedicated with strong debug skills Requires proficiency in scripting ( tcl / unix / perl ) Excellent communication skills including ability to interface with customers and business unit personnel are essential.

Designing and verifying complex Analog Mixed-Signal layouts, ensuring high-quality and reliable IPs. Collaborating with cross-functional teams to optimize layout designs for performance and manufacturability. Utilizing advanced tools and methodologies to mitigate deep submicron effects. Conducting floor-planning, routing, and top-level verification. Ensuring compliance with DRC, LVS, LPE standards and addressing ESD and latch-up considerations. Optimizing power routes and addressing EM and IR considerations for robust designs. The Impact You Will Have: Enhancing the performance and reliability of our high-speed SerDes IPs and other critical components. Driving innovation in Analog Mixed-Signal layout design, contributing to cutting-edge technology developments. Ensuring seamless integration and functionality of our IPs in diverse applications. Improving design efficiency and manufacturability through advanced layout techniques. Contributing to the success of our product development lifecycle by delivering high-quality designs. Supporting our mission to lead in chip design and IP integration, shaping the future of technology. What You ll Need: 6+ years of experience in Analog Mixed-Signal layout and verification. Advanced understanding of deep submicron effects and mitigation techniques. Proficiency in using advanced layout design tools and methodologies. Solid understanding of CMOS and FinFET layouts and process technology in 28nm and below. Familiarity with layout design flow, including top-level verification flow, DRC/LVS, LPE.

You are a seasoned professional with a strong background in Custom Analog Design, possessing over 5 years of experience in the field. You have a deep understanding of analog circuit building blocks such as amplifiers, reference circuits, and clock generators. Your expertise extends to working closely with design and CAD teams to develop and deploy simulation methodologies that enhance design verification efficiency. You are adept at using industry-standard design verification and simulation tools like HSPICE, Primesim, and VCS. Additionally, you have a knack for scripting and automation using tools such as Perl, Python, and TCL. You are passionate about providing support and training to your peers, fostering a collaborative and innovative environment. What You ll Be Doing: Designing, developing, modifying, and evaluating physical IP such as SERDES, DDR, and Memory. Collaborating with design and CAD teams to develop and deploy simulation methodologies. Using existing tools and scripting skills to automate design and simulation flows/tasks. Providing support and training to enhance team capabilities. Analyzing and optimizing analog circuit building blocks like amplifiers, reference circuits, and clock generators. Ensuring efficient use of tools to improve design verification time. The Impact You Will Have: Enhancing the efficiency and accuracy of analog design verification processes. Contributing to the development of high-performance silicon chips and software content. Driving innovation in analog circuit design and simulation methodologies. Improving the overall design and development cycle within the team. Providing valuable training and support to team members, fostering a collaborative environment. Playing a key role in the success of Synopsys technology and product offerings. What You ll Need: BE/MTech in Electronics or a related field. 5+ years of experience in Custom Analog Design. Proficiency in industry-standard design verification and simulation tools (HSPICE, Primesim, VCS). Strong scripting skills using Perl, Python, and TCL. In-depth knowledge of analog circuit building blocks like amplifiers, reference circuits, and clock generators. Who You Are: A collaborative team player with excellent communication skills. A problem solver with a keen eye for detail and a passion for innovation. A proactive learner who stays updated with the latest industry trends and technologies. A mentor who enjoys sharing knowledge and helping others grow. An analytical thinker who can evaluate complex problems and develop effective solutions.

Developing next-generation high-speed memory interface PHY IPs (DDR/HBM/UCIe) Executing projects in advanced technologies with a focus on analytical and problem-solving skills Designing high-speed IOs for memory interface PHY IP in CMOS/FinFET/GAA Collaborating with cross-functional teams globally to achieve project goals Ensuring product quality and efficiency in all design tasks Staying updated with the latest industry standards and technological advancements The Impact You Will Have: Driving the development of innovative high-speed memory interface PHY IPs Contributing to the integration of advanced capabilities in SoCs Enhancing the performance, power efficiency, and size optimization of target applications Reducing risk and accelerating time-to-market for differentiated products Collaborating with global teams to deliver high-quality products Setting industry benchmarks for advanced analog design technologies What You ll Need: BTech/MTech degree in a relevant field 3+ years of experience in analog design fundamentals and device physics Proficiency in high-speed IO designs in advanced technologies Experience with ESD and reliability concepts Knowledge of JEDEC requirements for memory interfaces and standards Familiarity with signal integrity and/or power integrity is a plus Who You Are: An analytical thinker with strong problem-solving skills A collaborative team player with excellent communication and interpersonal skills Detail-oriented and capable of executing tasks with high precision and efficiency Adaptable and eager to learn new technologies and industry standards Passionate about innovation and technological advancement

"> Search Jobs Find Jobs For * Designing and developing DDR I/O circuits to meet performance and power specifications. * Collaborating with cross-functional teams to integrate analog circuitry into SoCs. * Executing circuit design tasks with a focus on product quality and efficiency. * Conducting layout reviews and ensuring adherence to design methodologies. * Participating in design reviews and providing technical insights. * Staying updated with the latest advancements in CMOS processes and deep submicron technologies. The Impact You Will Have: * Enhancing the performance and efficiency of our silicon IP portfolio. * Contributing to the rapid integration of advanced capabilities into SoCs. * Reducing the time-to-market and risk for our customers products. * Driving innovation in analog design and setting new industry standards. * Strengthening Synopsys position as a leader in chip design and verification. * Empowering the development of high-performance, differentiated products. What You ll Need: * BTech/MTech in Electrical Engineering or a related field. * 4+ years of experience in CMOS circuit design and layout methodology. * Strong knowledge of deep submicron process technologies. * Familiarity with ASIC design flow and JEDEC standards for DDR interfaces. * Excellent written and verbal communication skills. Who You Are: * A collaborative team player with a proactive approach. * Detail-oriented with a commitment to quality and efficiency. * Innovative and adaptable, always seeking to learn and grow. * Effective communicator, able to convey technical information clearly. * Problem-solver with strong analytical skills.

We are looking for a seasoned and enthusiastic professional who thrives on problem-solving, is committed to ongoing learning, and is eager to work with advanced technologies. You possess outstanding communication skills and enjoy working in a dynamic team of highly talented engineers. As the Manager- Analog Design, you have a deep understanding of deep understanding of high-speed circuit design. You are experienced in leading teams, designing and analyzing analog circuits, combined with your knowledge of network/transmission line/SI analysis and semiconductor devices/physics, makes you a valuable asset. managing regression analysis and collaborating closely with design, layout and other stakeholders. You have experience in modeling complex/non-linear circuit behavior to linear models for stability and jitter analysis. Your ability to micro-architect circuits from specifications and focus on enhancing PPA targets and reducing turnaround time sets you apart. You possess a strong grip on design reliability analysis and can work effectively both independently and lead the team. Your excellent communication skills and collaborative nature enable you to work seamlessly with cross-functional teams to achieve project goals. You are dedicated to staying updated with the latest advancements in analog design and are eager to contribute to innovative solutions that shape the future of technology. What You ll Be Doing: * Collaborate with design, Layout, ESD teams to align requirements and resolve bottlenecks effectively. * Innovate and refine design methodologies to enhance scalability, efficiency, and reliability. * Design, develop, and verify high-speed analog and mixed-signal integrated circuits. * Collaborate with cross-functional teams to define design specifications and requirements. * Model complex/non-linear circuit behavior to linear models for stability and jitter analysis. * Perform circuit simulations and layout verification to ensure design accuracy and performance. * Optimize designs for power, performance, and area (PPA) and reduce turnaround time. * Contribute to the development of design methodologies and best practices. The Impact You Will Have: * Advance the design and verification of high-speed analog and mixed-signal integrated circuits. * Ensure the accuracy and reliability of analog designs through rigorous verification and testing. * Collaborate with cross-functional teams to deliver innovative solutions that meet market demands. * Contribute to the continuous improvement of design methodologies and processes. * Support the development of cutting-edge technologies that enhance our products and services. * Drive innovation and excellence in analog design at Synopsys. What You ll Need: * Bachelor s degree in electrical engineering, Computer Engineering, or a related field. * 10+ years of experience in analog circuit design and analysis. * Deep understanding of analog circuits design and analysis techniques. * Experience in modeling complex/non-linear circuit behavior to linear models for stability and jitter analysis. * Good understanding of network/transmission line/SI analysis and semiconductor devices/physics. * Strong grip on design reliability analysis. * Ability to micro-architect circuits from specifications. * Focus on enhancing PPA targets and reducing turnaround time. Who You Are: * A strong leader with excellent communication and mentoring skills. * Innovative and committed to continuous improvement. * Detail-oriented with a strategic mindset. * Collaborative, with the ability to work effectively in a team environment. * Passionate about technology and eager to work on cutting-edge projects

Leading the development of next-generation high-speed memory interface IPs (DDR/HBM/UCIe). Driving projects in new technologies with a focus on analytical and problem-solving skills. Acting as a technical mentor to ensure schedules and product quality are met. Developing and maintaining project schedules, working in cross-functional settings. Demonstrating proficiency in design concepts and methodologies. Taking on people management responsibilities, guiding and developing your team. The Impact You Will Have: Contributing to the development of cutting-edge memory interface PHY IPs that drive technological advancements. Ensuring high-quality product development through effective leadership and technical expertise. Mentoring and guiding your team to achieve their full potential and meet project goals. Collaborating with cross-functional teams to drive innovation and efficiency. Maintaining Synopsys leadership position in the semiconductor industry by delivering top-notch IPs. Shaping the future of technology through continuous innovation and excellence. What You ll Need: Bachelor s or Master s degree in Electrical Engineering or related field. 10+ years of experience in analog/mixed signal design. Knowledge of deep submicron process technologies - CMOS/FinFET/GAA. In-depth understanding of JEDEC requirements for memory interfaces and standards. Familiarity with ESD concepts and signal integrity/power integrity is a plus. Proven ability to lead projects and deliver high-quality products efficiently. Excellent written and verbal communication skills. Who You Are: A visionary leader with a passion for analog design and innovation. Analytical and detail-oriented with strong problem-solving skills. An effective communicator and mentor, capable of guiding and developing your team. Proactive and adaptable, able to thrive in cross-functional settings. Committed to delivering high-quality products and driving technological advancements.

Analyze various analog circuit techniques for dynamic and static power reduction, performance enhancement, and area reduction. Develop Analog Full custom circuit macros, including Transmitters, Receivers, Clocking circuits, equalizers, serializers, de-serializers, and Analog Front End needed for High-Speed PHY IP. Leverage your understanding of circuit design and layout, along with knowledge of bipolar, CMOS, passive structure, and interconnect failure modes. Collaborate with experienced teams locally and globally to deliver high-performance silicon chips. Create simulation environments to verify circuit specifications and debug circuits as needed. Optimize layouts and parasitics to enhance circuit performance and reliability. The Impact You Will Have: Contribute to the design and verification of advanced silicon chips, accelerating their development and manufacturing processes. Enable customers to optimize their chips for power, cost, and performance, significantly reducing project schedules. Drive innovations in high-speed physical interfaces, enhancing the performance and reliability of our products. Collaborate with global teams to leverage diverse expertise and deliver cutting-edge technology solutions. Influence the development of next-generation processes and models for manufacturing high-performance silicon chips. Ensure the successful implementation of analog and mixed-signal circuit designs in advanced CMOS technologies. What You ll Need: BE with 5+ years of relevant experience or MTech with 4+ years of relevant experience in Electrical/Electronics/VLSI Engineering or a related field. Strong fundamentals in CMOS circuit design, device physics, and sub-micron design methodologies. Experience with analog transistor-level circuit design in nanometer technologies. Familiarity with Multi Gbps range high-speed designs, including PAM4 serdes architectures. Proficiency in creating simulation environments and debugging circuits. Who You Are: Detail-oriented with excellent problem-solving skills. Strong communicator, capable of collaborating with teams across different locations. Innovative thinker with a passion for technology and circuit design. Proactive and self-motivated, with the ability to work independently and as part of a team. Adaptable and open to learning new techniques and methodologies.

You are a highly skilled engineer with a strong foundation in analog and mixed signal integrated circuit design. You bring both theoretical knowledge and practical experience to the table, enabling you to contribute effectively to our fast-growing R&D team. With a background in transistor-level circuit design, CMOS fundamentals, and high-speed logic paths, you excel in a dynamic environment. Your expertise in timing analysis, characterization, and modeling sets you apart. You thrive in cross-functional teams, collaborating with diverse professionals from various backgrounds to achieve common goals. Your proficiency with IC design tools, along with your familiarity with scripting languages like TCL, Perl, C, Python, and MATLAB, makes you a valuable asset to our team. You are detail-oriented, possess excellent communication skills, and are accustomed to working in a globally diverse environment. What You ll Be Doing: Direct and guide the activities of a team of engineers characterizing timing, analyzing timing results, and generating timing models of high-speed SERDES IP. Develop and align timing flow and methodology to ensure efficiency and quality of the team s deliverables. Conduct design reviews and evaluate final results of timing views and reports. Present results of timing assessments or critical issue investigations and make recommendations for actions necessary to achieve desired results. Ensure the team follows processes for maximum design quality. Consult on the timing characteristics of the SerDes IP product and propose solutions for STA timing closure. The Impact You Will Have: Enhance the performance and reliability of high-speed analog integrated circuits through meticulous timing analysis and characterization. Contribute to the development of cutting-edge SERDES IP, driving advancements in high-speed data communication. Improve the efficiency and quality of deliverables through optimized timing flow and methodology. Ensure maximum design quality by adhering to established processes and best practices. Provide critical insights and recommendations to address timing issues and achieve desired results. Collaborate with cross-functional teams to deliver innovative solutions that meet the evolving needs of the semiconductor industry. What You ll Need: MSc in Electrical Engineering or related field with 2 years of experience in IC design. Familiarity with transistor-level circuit design and CMOS design fundamentals. In-depth knowledge of setup and hold timing analysis. Experience in timing characterization, modeling, simulation, and verification. Familiarity with custom digital design (i.e., high-speed logic paths). Experience with timing tools such as Primetime, NanoTime, or equivalent. Hands-on experience with the physical layout of high-speed circuits is a plus. Knowledge of SPICE simulators and simulation methods. Proficiency in scripting languages such as TCL, Perl, C, Python, MATLAB. Who You Are: Detail-oriented and capable of conducting thorough analyses. Strong communicator with excellent documentation skills. Collaborative team player comfortable in a cross-functional, globally diverse environment. Creative problem solver with the ability to think critically and propose effective solutions. Adaptable and able to work at all levels of an organization

Design, develop, and verify high-speed analog and mixed-signal integrated circuits. Collaborate with cross-functional teams to define design specifications and requirements. Model complex/non-linear circuit behavior to linear models for stability and jitter analysis. Perform circuit simulations and layout verification to ensure design accuracy and performance. Optimize designs for power, performance, and area (PPA) and reduce turnaround time. Contribute to the development of design methodologies and best practices. The Impact You Will Have: Advance the design and verification of high-speed analog and mixed-signal integrated circuits. Ensure the accuracy and reliability of analog designs through rigorous verification and testing. Collaborate with cross-functional teams to deliver innovative solutions that meet market demands. Contribute to the continuous improvement of design methodologies and processes. Support the development of cutting-edge technologies that enhance our products and services. Drive innovation and excellence in analog design at Synopsys. What You ll Need: Bachelor s degree in electrical engineering, Computer Engineering, or a related field. 4+ years of experience in analog circuit design and analysis. Deep understanding of analog circuits design and analysis techniques. Experience in modeling complex/non-linear circuit behavior to linear models for stability and jitter analysis. Good understanding of network/transmission line/SI analysis and semiconductor devices/physics. Strong grip on design reliability analysis. Ability to micro-architect circuits from specifications. Focus on enhancing PPA targets and reducing turnaround time.

Leading the development of next-generation DDR/HBM/UCIe IPs. Advising team members to meet schedules and resolve problems effectively. Taking on project leadership roles and contributing to complex project aspects. Developing and maintaining project schedules, ensuring timely delivery. Collaborating in cross-functional settings to drive project success. Demonstrating proficiency in design and verification processes. The Impact You Will Have: Driving innovation in next-generation DDR/HBM/UCIe IP development. Enhancing the performance and capabilities of our Silicon IP portfolio. Ensuring high-quality and efficient project execution. Mentoring and guiding team members to achieve their full potential. Contributing to the rapid integration of advanced technologies into SoCs. Helping Synopsys maintain its leadership in the semiconductor industry. What You ll Need: Bachelor s or Master s degree in Electrical Engineering or a related field. 8+ years of experience in CMOS circuit design and layout methodology. In-depth understanding of analog/mixed-signal circuitry and ESD concepts. Familiarity with analog mixed-signal simulation strategies. Knowledge of JEDEC standards for DDR interfaces and ASIC design flow. Who You Are: Visionary leader with strong problem-solving skills. Excellent communicator with the ability to lead and mentor teams. Detail-oriented and proficient in project management. Adaptable and able to thrive in cross-functional settings. Committed to achieving high standards of product quality and efficiency

You are a highly skilled and motivated Gen AI Platform Engineer with a passion for leveraging modern architectures, tools, and technologies. You excel in designing and developing scalable, modular solutions that enhance the efficiency and effectiveness of R&D efforts. Your deep understanding of distributed computing, cloud services, and container technologies allows you to create robust and secure platforms. You are collaborative, with excellent problem-solving and organizational skills. Your ability to incorporate AI and machine learning into your work sets you apart, and you are always looking to stay ahead of industry trends. Your effective communication skills enable you to work effectively with cross-functional teams and stakeholders, ensuring that user feedback is incorporated into the development process. What You will Be Doing: Designing and developing scalable, modular platform solutions that promote reuse and are easily integrated into our diverse product suite. Collaborating with cross-functional teams to understand their needs and incorporate user feedback into the platforms development. Establishing and Implementation of best practices for modern software architecture, including microservices, serverless computing, and API-first strategies and CI/ CD. Driving the strategy for containerization and orchestration using Docker, Kubernetes, or equivalent technologies. B enchmarking LLM models with varying loa d profile s to evaluate model performance. Developing Cloud native solutions for GenAI apps including Helm development, CRD, working with Kubernetes APIs, Storage class , PVCs, Services , Ingress controllers etc Handson Kubernetes monitoring Architecture including building Grafana dashboards, custom metrics, autoscaling etc. Hands on GPU Administration on Kubernetes including monitoring, multi-instance GPU etc. Incorporating AI and machine learning capabilities into the platform to facilitate smarter workflows and predictive analytics. The Impact You Will Have: Enhancing the efficiency and effectiveness of our R&D product development processes. Keeping our products at the forefront of the industry through the adoption of advanced technologies. Promoting reuse and integration across our diverse product suites . Promoting Automation of various applications build processes. Play a key role in cloud native transformation journey of legacy application stacks. Facilitating smarter workflows and predictive analytics through AI and machine learning. Ensuring the robustness, security, and compliance of our platform infrastructure. Driving innovation and continuous improvement within the platform engineering team. What You will Need: Bachelors or M asters degree in computer science , Engineering, or a related field. A minimum of 5 years of experience in software development. Strong development experience in Go (highly preferred) Python. Model management, etc ,. Deep understanding of distributed computing, CAP theorem, and system design tradeoffs. Proven expertise in cloud computing services (AWS, Azure, GCP), container technologies (Docker, Kubernetes). Linux Foundation certifications: CKA, CKAD , CKS (highly preferred). Experience with Generative AI, along with a working knowledge of various aspects such as GPUs, models, inference serving, and LLM Gateways, is highly desirable. Familiarity with AI/machine learning frameworks and tools, coupled with a keen interest in staying updated with emerging innovations, is also greatly valued. Background in working with CI/CD pipelines and familiarity with modern software delivery ecosystem (GitHub Actions, Azure DevOps, Harness.io, GitLab CI, etc.). Excellent problem-solving, organizational, and leadership skills. Effective communication abilities to effectively collaborate with internal teams and stakeholders. Who You Are: A proactive and self-motivated individual. A creative thinker with strong problem-solving skills. Highly organized and detail oriented. A team player with excellent interpersonal skills. Adaptable and able to thrive in a fast-paced environment.

"> Search Jobs Find Jobs For Where Search Jobs Senior Staff Product Validation Engineer - PD Formality Bengaluru, Karnataka, India Engineering Employee Apply Save Job Share Email LinkedIn X Facebook Jump to Overview Job Description Benefits Culture How We Hire Overview Our Hardware Engineers at Synopsys are responsible for designing and developing cutting-edge semiconductor solutions. They work on intricate tasks such as chip architecture, circuit design, and verification to ensure the efficiency and reliability of semiconductor products. These engineers play a crucial role in advancing technology and enabling innovations in various industries. Play Video Job Description Category Engineering Hire Type Employee Job ID 10887 Remote Eligible No Date Posted 24/04/2025 We Are: You Are: You are a passionate and highly skilled engineer with a deep understanding of digital implementation and logic equivalence checking and a strong desire to lead product validation efforts. Your exceptional debugging skills and proficiency in software and scripting languages such as Perl, Tcl, and Python set you apart. With a keen eye for detail, you maintain high standards of product quality and excel in communication and leadership roles. You thrive in collaborative environments, working closely with cross-functional teams to develop and execute comprehensive validation plans. Your analytical mindset allows you to perform in-depth root cause analysis and proactively address potential issues, ensuring the readiness of products for customer deployment. You are an experienced professional with a B.Tech or M.Tech degree and a minimum of 6-8 years of related experience, ready to make a significant impact on our Formality tool. What You ll Be Doing: Execute and lead product validation of Synopsyss Formality tool by understanding requirements specifications, functional specifications, and customer use cases Lead a team of 5 or more product validation engineers Collaborate with cross-functional teams such as R&D, Product Engineering to develop, implement, and execute comprehensive validation plans based on our technical roadmap and specifications Define and manage scope, schedule, and risks associated with the validation objectives Perform in-depth customer incoming root cause analysis to understand the product weak areas and hot spots and execute proactive testing to improving product quality Use product expertise to provide technical recommendations, identify, diagnose and troubleshoot issues, and propose solutions to ensure quality and readiness of the product/solution for customer deployment Analyze product validation data to identify trends, discrepancies, and areas for improvement Prepare detailed validation reports for presenting to multi-functional teams and management The Impact You Will Have: Ensuring the quality and reliability of Synopsyss Formality product to keep standing out as a leading LEC solution in the industry Enabling timely and successful deployment of high-performance designs for our customers Contributing to the innovation and advancement of LEC and product validation technologies Strengthening collaboration and communication across R&D, Product Engineering, and Field teams What You ll Need: B.Tech or equivalent and a minimum of 8 years of related experience or M.Tech or equivalent and a minimum of 6 years of related experience Self-motivated individual with deep domain knowledge in Logic Equivalence Checking (LEC) including expertise in debugging and resolving LEC failures using Synopsys s Formality tool Experience and sound knowledge in design implementation including datapath optimization, CTS, UPF and DFT instrumentation Sound knowledge in HDL including SystemVerilog and VHDL Exceptional debugging skills Proficiency in software and scripting skills (Perl, Tcl, Python) Experience in cross-functional teamwork, driving projects and mentoring Who You Are: Details oriented with a focus on maintaining high standards of product quality Excellent communication, organizational, risk assessment/mitigation, and time management skills Ability to abstract up and communicate meaningful conclusions and define next steps Excellent communication and leadership skills The Team You ll Be A Part Of: You will be part of a dedicated product validation team for Formality, working closely with R&D, product engineering and field applications engineering teams. Your team focuses on ensuring the high quality of new releases and features of Formality tool, enabling customers to accurately and timely validate their high-performance designs. Together, you will tackle complex technical challenges and drive continuous improvement in our product validation processes. Rewards and Benefits: We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process. ======================== At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability. Apply Save Job test Share Email LinkedIn X Facebook Benefits At Synopsys, innovation is driven by our incredible team around the world. We feel honored to work alongside such talented and passionate individuals who choose to make a difference here every day. Were proud to provide the comprehensive benefits and rewards that our team truly deserves. Visit Benefits Page Health & Wellness Comprehensive medical and healthcare plans that work for you and your family. Time Away In addition to company holidays, we have ETO and FTO Programs. Family Support Maternity and paternity leave, parenting resources, adoption and surrogacy assistance, and more. ESPP Purchase Synopsys common stock at a 15% discount, with a 24 month look-back. Retirement Plans Save for your future with our retirement plans that vary by region and country. Compensation Competitive salaries. *Benefits vary by country and region - check with your recruiter to confirm Get an idea of what your daily routine around the office can be like Explore Bengaluru View Map Hiring Journey at Synopsys Apply When you apply to join us, your resume, skills, and experience are first reviewed for consideration. Phone Screen Once your resume has been selected, a recruiter and/or hiring manager will reach out to learn more about you, share more about the role, and answer any questions you might have. Interview Next up is interviewing (in person or virtual). You ll be invited to meet with members of the hiring team to discuss your skills and experience, and what you re looking for in your next role. Offer Congratulations! When you have been selected for the role, your recruiter will reach out to make you a verbal offer (a written offer will follow your conversation), and we hope you accept! Onboarding There will be some steps you need to take before you start to ensure a smooth first day, including new hire documentation. Welcome! Once you ve joined, your manager, team, and a peer buddy will help you get acclimated. Over the next few weeks, you ll be invited to join activities and training to help you ramp up for a successful future at Synopsys!

An enthusiastic and detail-oriented individual with a passion for electronics and hardware testing. You have a diploma or bachelors degree in Electrical or Electronics Engineering and are eager to apply your knowledge in a dynamic lab environment. Your hands-on experience with lab instruments and your understanding of high-speed interfaces like Ethernet and PCIe make you a strong candidate for this role. You are meticulous in your work, ensuring that all lab activities are executed seamlessly. You enjoy troubleshooting and solving technical challenges, and you are comfortable working in a fast-paced, collaborative environment. What You ll Be Doing: Configure, calibrate, and maintain test equipment such as oscilloscopes, logic analyzers, signal generators, and power supplies. Assist in assembling and setting up test benches for silicon validation, ensuring signal integrity and proper connectivity. Support high-speed interface testing, particularly for PCIe, Ethernet, and other serial communication protocols. Perform PCB rework, soldering, and desoldering of surface-mount (SMD) and through-hole components. Work closely with validation engineers to execute pre-silicon and post-silicon validation tests. Capture, analyze, and document test data using lab measurement tools. Troubleshoot hardware issues, connectivity problems, and signal integrity challenges related to PCIe and Ethernet interfaces. Maintain detailed logs of test results, test setups, and debugging activities. Assist in generating test reports and summaries for engineering teams. Ensure compliance with ESD protection guidelines and ISO standards for lab operations. Organize lab space and maintain an inventory of test equipment, components, and accessories. Ensure lab equipment is functional and regularly serviced for optimal performance. Follow standard operating procedures (SOPs) for equipment handling and storage. Manage procurement requests for test equipment and consumables, coordinating with vendors and internal teams. The Impact You Will Have: Ensure the seamless execution of validation activities, contributing to the high-quality standards of our products. Support the development and validation of cutting-edge silicon technologies, pushing the boundaries of innovation. Maintain a well-organized and efficient lab environment, enabling the engineering team to focus on core development tasks. Provide critical data and insights through meticulous documentation and reporting, aiding in informed decision-making. Enhance the reliability and performance of our hardware through thorough testing and troubleshooting. Contribute to the continuous improvement of lab operations and processes, ensuring compliance with industry standards. What You ll Need: Bachelors degree (B.Tech/B.E.) in Electrical, Electronics. 2 years of experience in a semiconductor validation or hardware testing lab. Hands-on experience with electronic lab equipment (oscilloscopes, multimeters, power analyzers, etc.). Basic understanding of PCB schematics, signal integrity, and electrical debugging. Familiarity with high-speed interfaces, including Ethernet and PCIe. Working knowledge of Python, MATLAB, and C for test automation is a plus. Strong problem-solving skills and attention to detail.

You are a passionate and detail-oriented engineer with a deep understanding of Static Timing Analysis (STA). You thrive in a collaborative environment, working closely with cross-functional teams to solve complex technical challenges. Your expertise in Synopsys PrimeTime and related technologies allows you to diagnose issues and propose innovative solutions that enhance product quality. You are self-motivated, with a proven track record of executing comprehensive validation plans and delivering high-quality results. Your exceptional debugging skills and proficiency in scripting languages like Perl, Tcl, and Python enable you to streamline processes and improve efficiency. You are committed to continuous learning and staying up-to-date with the latest industry trends and advancements. What You ll Be Doing: Execute and lead product validation of Synopsyss PrimeTime tool by understanding requirements specifications and functional specifications, customer use cases. Perform in-depth customer incoming root cause analysis to understand the product weak areas and hot spots and execute proactive testing to reduce customer incoming thereby improving product quality. Collaborate with cross-functional teams such as R&D, Product Engineering, Field and Customers, recommend improvements in implementation and validation. Use product expertise to provide technical recommendations, identify, diagnose and troubleshoot issues and propose solutions to ensure quality and readiness of the product/solution for customer deployment. Demonstrate a high level of attention to detail and accuracy in all tasks. Perform risk assessments and develop mitigation strategies to address potential product validation issues. Analyze validation data to identify trends, discrepancies and areas for improvement. Prepare detailed validation reports to present to multi-functional teams and management. The Impact You Will Have: Ensure the high quality and reliability of Synopsyss PrimeTime tool, contributing to its success in the market. Enhance customer satisfaction by proactively identifying and addressing potential issues before they impact users. Collaborate with R&D and Product Engineering teams to drive continuous improvements in product design and functionality. Provide valuable insights and recommendations that influence the development and validation of future product releases. Contribute to the overall success of Synopsys by ensuring that our tools meet the highest standards of performance and reliability. Support the deployment of cutting-edge technologies in high-performance designs, shaping the future of the semiconductor industry. What You ll Need: Deep domain knowledge in Static Timing Analysis. BSEE or equivalent and a minimum of 2 years of related experience or MSEE or equivalent and a minimum of 1 year of related experience. Experience with Synopsys PrimeTime, timing analysis, ECO flows, Extraction, power, SDC constraints, advanced OCV concepts, derates, PBA timing, distributes, hierarchical STA flows, and/or physical design closure. Exceptional debugging skills. Proficient in software and scripting skills (Perl, Tcl, Python). Detail-oriented with a focus on maintaining high standards of product quality. Who You Are: Collaborative team player with excellent communication skills. Analytical thinker with a problem-solving mindset. Proactive and self-motivated individual. Adaptable and flexible in a fast-paced environment. Strong attention to detail and accuracy.

Creating System verification solutions for Arm AMBA5 protocols such as CHI, AXI5/ACE5 for on-chip, chip-to-chip, die-to-die, coherent, and non-coherent design topologies. Responsible for functional verification involving coherent and non-coherent IP designs. Collaborating with market leaders in High Performance Computing, Data Centre, Mobile/Client, Automotive, and IoT segments to define and develop products that meet complex verification requirements. Architecting and building SystemVerilog UVM-based verification components, testbenches, checkers, scoreboards, and verification IPs. Developing verification plans and driving functional coverage-driven verification closure of real designs. Debugging and resolving issues in verification environments to ensure robust and reliable verification processes. The Impact You Will Have: Enhancing the reliability and performance of high-performance computing and data center systems through rigorous verification processes. Contributing to the advancement of mobile and client devices by ensuring the integrity and functionality of their verification protocols. Driving innovation in the automotive sector by developing robust verification solutions for automotive systems. Supporting the growth of IoT applications by providing reliable and efficient verification for IoT devices. Collaborating with industry leaders to shape the future of system verification and contribute to technological advancements. Ensuring the successful implementation and integration of verification IPs, thereby enhancing the overall quality of our products. What You ll Need: B.E/B.Tech in Electrical Engineering/Electronics & Communications Engineering with 5-8 years of relevant experience, OR M.E/M.Tech in VLSI Design/Microelectronics with 4-8 years of relevant experience. Hands-on experience in architecting and building SystemVerilog UVM-based verification components, testbenches, checkers, scoreboards, and verification IPs. In-depth understanding of cache coherency protocols such as Arm AMBA AXI/ACE, CHI; CCIX or CXL Cache. Experience in creating verification plans and achieving functional coverage-driven verification closure of real designs. Proficiency in writing scripts using Perl, Python, and Shell scripting. Who You Are: Excellent problem-solving, debugging, and analytical skills. Strong programming skills and familiarity with object-oriented programming concepts. Creative and innovative mindset. Excellent verbal and written communication skills. A collaborative team player with a passion for functional verification.

* Responsible for functional verification involving coherent and non-coherent IP designs. * Collaborating with market leaders in High Performance Computing, Data Centre, Mobile/Client, Automotive, and IoT segments to define and develop products that meet complex verification requirements. * Architecting and building SystemVerilog UVM-based verification components, testbenches, checkers, scoreboards, and verification IPs. * Developing verification plans and driving functional coverage-driven verification closure of real designs. * Debugging and resolving issues in verification environments to ensure robust and reliable verification processes. The Impact You Will Have: * Enhancing the reliability and performance of high-performance computing and data center systems through rigorous verification processes. * Contributing to the advancement of mobile and client devices by ensuring the integrity and functionality of their verification protocols. * Driving innovation in the automotive sector by developing robust verification solutions for automotive systems. * Supporting the growth of IoT applications by providing reliable and efficient verification for IoT devices. * Collaborating with industry leaders to shape the future of system verification and contribute to technological advancements. * Ensuring the successful implementation and integration of verification IPs, thereby enhancing the overall quality of our products. What You ll Need: * B.E/B.Tech in Electrical Engineering/Electronics & Communications Engineering with 5-8 years of relevant experience, OR M.E/M.Tech in VLSI Design/Microelectronics with 4-8 years of relevant experience. * Hands-on experience in architecting and building SystemVerilog UVM-based verification components, testbenches, checkers, scoreboards, and verification IPs. * You will be involved in creating System verification solutions for Arm AMBA5 protocols such as CHI, AXI5/ACE5 for on-chip, chi-to-chip, die-to-die, coherent and non-coherent design topologies. * You will be responsible for functional verification involving coherent and non-coherent IP designs. * Proficiency in writing scripts using Perl, Python, and Shell scripting. Who You Are: * Excellent problem-solving, debugging, and analytical skills. * Strong programming skills and familiarity with object-oriented programming concepts. * Creative and innovative mindset. * Excellent verbal and written communication skills. * A collaborative team player with a passion for functional verification.

Characterizing and modeling standard cells for various technologies and foundries. Conducting quality analysis of characterized liberty and Verilog models in terms of timing, power, and functionality. Validating characterization and simulation tool versions including PrimeLib, Hspice, PrimeSim, and Finesim. Providing daily status updates on project progress. Ensuring timely and quality releases of projects. Collaborating with cross-functional teams to enhance design and verification processes. The Impact You Will Have: Enhancing the accuracy and efficiency of standard cell models across various technologies. Improving the quality and reliability of characterized models in terms of timing, power, and functionality. Streamlining validation processes for characterization and simulation tools, ensuring robust tool versions. Contributing to the timely delivery of high-quality releases, meeting project deadlines and standards. Supporting technological innovation through meticulous analysis and validation. Fostering collaboration and knowledge sharing within cross-functional teams for continuous improvement. What You ll Need: 5 Years of experience in Standard Cell Characterization Thorough knowledge of MOSFET and FINFET technologies. Experience with PrimeLib, Hspice, PrimeSim, and Finesim tools. Strong analytical skills for quality analysis of characterized models. Proficiency in characterizing and modeling standard cells for various technologies. Excellent communication skills for providing daily status updates and collaborating with teams. Who You Are: A detail-oriented professional with a strong analytical mindset. A proactive communicator, able to provide clear and concise updates. A collaborative team player, ready to work with cross-functional teams. A dedicated individual committed to delivering high-quality work on time. An innovative thinker, always looking for ways to improve processes and outcomes.